Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14542921	1			T1	284		T2	14653		T7	1276
all_pins[1]	14542921	1			T1	284		T2	14653		T7	1276
all_pins[2]	14542921	1			T1	284		T2	14653		T7	1276

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43252207	1			T1	804		T2	43305		T7	3812
values[0x1]	376556	1			T1	48		T2	654		T7	16
transitions[0x0=>0x1]	374493	1			T1	48		T2	654		T7	16
transitions[0x1=>0x0]	374519	1			T1	48		T2	654		T7	16

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14469637	1			T1	236		T2	14503		T7	1262
all_pins[0]	values[0x1]	73284	1			T1	48		T2	150		T7	14
all_pins[0]	transitions[0x0=>0x1]	73272	1			T1	48		T2	150		T7	14
all_pins[0]	transitions[0x1=>0x0]	5221	1			T7	2		T22	27		T34	36
all_pins[1]	values[0x0]	14537688	1			T1	284		T2	14653		T7	1274
all_pins[1]	values[0x1]	5233	1			T7	2		T22	27		T34	36
all_pins[1]	transitions[0x0=>0x1]	4992	1			T7	2		T22	27		T34	36
all_pins[1]	transitions[0x1=>0x0]	297798	1			T2	504		T15	9944		T23	2882
all_pins[2]	values[0x0]	14244882	1			T1	284		T2	14149		T7	1276
all_pins[2]	values[0x1]	298039	1			T2	504		T15	9944		T23	2882
all_pins[2]	transitions[0x0=>0x1]	296229	1			T2	504		T15	9878		T23	2882
all_pins[2]	transitions[0x1=>0x0]	71500	1			T1	48		T2	150		T7	14