Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	569	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5085	1			T2	11		T7	1		T22	8
len_601_800	11575	1			T2	35		T7	4		T22	18
len_401_600	7744	1			T2	25		T7	3		T22	14
len_201_400	4177	1			T2	10		T7	3		T22	6
len_65_200	9412	1			T1	14		T2	3		T22	3
len_min_for_xof_require_squeeze	103	1			T39	1		T96	1		T50	1
len_keccak_block_sizes[72]	98	1			T23	1		T38	1		T181	2
len_keccak_block_sizes[104]	101	1			T50	1		T181	1		T182	1
len_keccak_block_sizes[136]	87	1			T51	1		T181	1		T180	1
len_keccak_block_sizes[144]	36	1			T183	1		T184	1		T185	1
len_keccak_block_sizes[168]	43	1			T51	1		T186	1		T187	1
len_datapath_width	976	1			T1	1		T22	1		T34	1
len_2_63	15119	1			T1	15		T2	8		T7	2
len_1	55	1			T141	1		T113	1		T179	1