Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
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Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 0 8 100.00 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6033329 1 T1 1225 T2 17104 T7 1758
auto[1] 6033311 1 T1 1225 T2 17104 T7 1758



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 11999168 1 T1 2412 T2 34062 T7 3496
triple_byte_access 22530 1 T1 12 T2 60 T7 4
halfword_access 22466 1 T1 10 T2 38 T7 6
byte_access 22476 1 T1 16 T2 48 T7 10



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for state_mask_share_cross

Bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 5999593 1 T1 1206 T2 17031 T7 1748
auto[0] triple_byte_access 11265 1 T1 6 T2 30 T7 2
auto[0] halfword_access 11233 1 T1 5 T2 19 T7 3
auto[0] byte_access 11238 1 T1 8 T2 24 T7 5
auto[1] word_access 5999575 1 T1 1206 T2 17031 T7 1748
auto[1] triple_byte_access 11265 1 T1 6 T2 30 T7 2
auto[1] halfword_access 11233 1 T1 5 T2 19 T7 3
auto[1] byte_access 11238 1 T1 8 T2 24 T7 5

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