Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13426922	1			T1	38269		T2	71		T3	15856
all_values[1]	13426922	1			T1	38269		T2	71		T3	15856
all_values[2]	13426922	1			T1	38269		T2	71		T3	15856

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462325

1

T1

7

T2

21

T3

23

auto[1]

39818441

1

T1

114800

T2

192

T3

47545

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40065636

1

T1

114684

T2

198

T3

47166

auto[1]

215130

1

T1

123

T2

15

T3

402

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	175142	1			T2	11		T33	3120		T36	24
all_values[0]	auto[0]	auto[1]	1293	1			T2	4		T33	2		T36	4
all_values[0]	auto[1]	auto[0]	13180070	1			T1	38228		T2	55		T3	15722
all_values[0]	auto[1]	auto[1]	70417	1			T1	41		T2	1		T3	134
all_values[1]	auto[0]	auto[0]	163625	1			T1	6		T2	4		T33	3120
all_values[1]	auto[0]	auto[1]	1001	1			T1	1		T2	2		T33	2
all_values[1]	auto[1]	auto[0]	13191587	1			T1	38222		T2	62		T3	15722
all_values[1]	auto[1]	auto[1]	70709	1			T1	40		T2	3		T3	134
all_values[2]	auto[0]	auto[0]	120371	1			T3	22		T7	159		T40	51
all_values[2]	auto[0]	auto[1]	893	1			T3	1		T7	2		T40	4
all_values[2]	auto[1]	auto[0]	13234841	1			T1	38228		T2	66		T3	15700
all_values[2]	auto[1]	auto[1]	70817	1			T1	41		T2	5		T3	133