Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54888 |
1 |
|
|
T1 |
52 |
|
T2 |
2 |
|
T3 |
192 |
auto[1] |
54430 |
1 |
|
|
T2 |
4 |
|
T33 |
138 |
|
T40 |
224 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
27266 |
1 |
|
|
T1 |
7 |
|
T3 |
42 |
|
T33 |
34 |
lower_val |
27057 |
1 |
|
|
T1 |
14 |
|
T3 |
55 |
|
T33 |
40 |
zero_val |
904 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
40588 |
1 |
|
|
T1 |
24 |
|
T3 |
96 |
|
T33 |
24 |
lower_val |
41090 |
1 |
|
|
T1 |
28 |
|
T2 |
2 |
|
T3 |
96 |
zero_val |
27640 |
1 |
|
|
T2 |
4 |
|
T33 |
68 |
|
T40 |
112 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6580 |
1 |
|
|
T1 |
4 |
|
T3 |
24 |
|
T36 |
16 |
higher_val |
higher_val |
auto[1] |
3426 |
1 |
|
|
T33 |
6 |
|
T40 |
30 |
|
T8 |
17 |
higher_val |
lower_val |
auto[0] |
6802 |
1 |
|
|
T1 |
3 |
|
T3 |
18 |
|
T36 |
15 |
higher_val |
lower_val |
auto[1] |
3488 |
1 |
|
|
T33 |
11 |
|
T40 |
17 |
|
T8 |
19 |
higher_val |
zero_val |
auto[0] |
48 |
1 |
|
|
T40 |
1 |
|
T15 |
1 |
|
T39 |
1 |
higher_val |
zero_val |
auto[1] |
6922 |
1 |
|
|
T33 |
17 |
|
T40 |
36 |
|
T8 |
40 |
lower_val |
higher_val |
auto[0] |
6756 |
1 |
|
|
T1 |
5 |
|
T3 |
31 |
|
T36 |
16 |
lower_val |
higher_val |
auto[1] |
3249 |
1 |
|
|
T33 |
5 |
|
T40 |
5 |
|
T8 |
18 |
lower_val |
lower_val |
auto[0] |
6835 |
1 |
|
|
T1 |
9 |
|
T3 |
24 |
|
T36 |
10 |
lower_val |
lower_val |
auto[1] |
3418 |
1 |
|
|
T33 |
17 |
|
T40 |
13 |
|
T8 |
36 |
lower_val |
zero_val |
auto[0] |
40 |
1 |
|
|
T39 |
1 |
|
T16 |
2 |
|
T178 |
1 |
lower_val |
zero_val |
auto[1] |
6759 |
1 |
|
|
T33 |
18 |
|
T40 |
25 |
|
T8 |
44 |
zero_val |
higher_val |
auto[0] |
267 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T54 |
1 |
zero_val |
higher_val |
auto[1] |
55 |
1 |
|
|
T40 |
1 |
|
T39 |
1 |
|
T68 |
1 |
zero_val |
lower_val |
auto[0] |
307 |
1 |
|
|
T3 |
2 |
|
T12 |
1 |
|
T36 |
1 |
zero_val |
lower_val |
auto[1] |
60 |
1 |
|
|
T39 |
2 |
|
T68 |
1 |
|
T16 |
2 |
zero_val |
zero_val |
auto[0] |
149 |
1 |
|
|
T2 |
1 |
|
T33 |
1 |
|
T40 |
1 |
zero_val |
zero_val |
auto[1] |
66 |
1 |
|
|
T40 |
1 |
|
T39 |
1 |
|
T68 |
1 |