Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13426922	1			T1	38269		T2	71		T3	15856
all_pins[1]	13426922	1			T1	38269		T2	71		T3	15856
all_pins[2]	13426922	1			T1	38269		T2	71		T3	15856

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39858097	1			T1	114759		T2	212		T3	46664
values[0x1]	422669	1			T1	48		T2	1		T3	904
transitions[0x0=>0x1]	420154	1			T1	48		T2	1		T3	904
transitions[0x1=>0x0]	420178	1			T1	48		T2	1		T3	904

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13356505	1			T1	38228		T2	70		T3	15722
all_pins[0]	values[0x1]	70417	1			T1	41		T2	1		T3	134
all_pins[0]	transitions[0x0=>0x1]	70403	1			T1	41		T2	1		T3	134
all_pins[0]	transitions[0x1=>0x0]	5720	1			T1	7		T8	47		T15	76
all_pins[1]	values[0x0]	13421188	1			T1	38262		T2	71		T3	15856
all_pins[1]	values[0x1]	5734	1			T1	7		T8	47		T15	76
all_pins[1]	transitions[0x0=>0x1]	5363	1			T1	7		T8	47		T15	65
all_pins[1]	transitions[0x1=>0x0]	346147	1			T3	770		T15	5739		T23	2340
all_pins[2]	values[0x0]	13080404	1			T1	38269		T2	71		T3	15086
all_pins[2]	values[0x1]	346518	1			T3	770		T15	5750		T23	2340
all_pins[2]	transitions[0x0=>0x1]	344388	1			T3	770		T15	5714		T23	2339
all_pins[2]	transitions[0x1=>0x0]	68311	1			T1	41		T2	1		T3	134