Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	594	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	4974	1			T1	4		T3	10		T33	7
len_601_800	11571	1			T1	7		T3	31		T33	25
len_401_600	7666	1			T1	6		T3	16		T33	21
len_201_400	4364	1			T1	3		T3	8		T33	8
len_65_200	7718	1			T1	1		T3	6		T33	6
len_min_for_xof_require_squeeze	88	1			T40	1		T182	1		T18	1
len_keccak_block_sizes[72]	65	1			T145	1		T183	1		T16	3
len_keccak_block_sizes[104]	59	1			T182	1		T144	1		T137	1
len_keccak_block_sizes[136]	51	1			T87	1		T182	1		T138	1
len_keccak_block_sizes[144]	49	1			T182	1		T45	1		T184	1
len_keccak_block_sizes[168]	46	1			T104	1		T138	2		T59	2
len_datapath_width	1000	1			T1	1		T40	1		T15	11
len_2_63	15094	1			T1	1		T2	3		T3	5
len_1	54	1			T43	1		T145	1		T138	2