Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57523 |
1 |
|
|
T1 |
26 |
|
T2 |
3 |
|
T3 |
95 |
auto[1] |
3354 |
1 |
|
|
T3 |
2 |
|
T7 |
7 |
|
T8 |
31 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26863 |
1 |
|
|
T1 |
8 |
|
T3 |
25 |
|
T33 |
21 |
auto[1] |
34014 |
1 |
|
|
T1 |
18 |
|
T2 |
3 |
|
T3 |
72 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47080 |
1 |
|
|
T1 |
26 |
|
T2 |
3 |
|
T3 |
82 |
auto[1] |
13797 |
1 |
|
|
T3 |
15 |
|
T12 |
1 |
|
T7 |
13 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13797 |
1 |
|
|
T3 |
15 |
|
T12 |
1 |
|
T7 |
13 |
sw_kmac_invalid_sideload |
47080 |
1 |
|
|
T1 |
26 |
|
T2 |
3 |
|
T3 |
82 |
app_valid_sideload |
13797 |
1 |
|
|
T3 |
15 |
|
T12 |
1 |
|
T7 |
13 |
app_invalid_sideload |
47080 |
1 |
|
|
T1 |
26 |
|
T2 |
3 |
|
T3 |
82 |