Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5978364 |
1 |
|
|
T1 |
4567 |
|
T2 |
24 |
|
T3 |
14476 |
auto[1] |
5978327 |
1 |
|
|
T1 |
4567 |
|
T2 |
24 |
|
T3 |
14476 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
11893383 |
1 |
|
|
T1 |
9100 |
|
T2 |
48 |
|
T3 |
28816 |
triple_byte_access |
20918 |
1 |
|
|
T1 |
18 |
|
T3 |
54 |
|
T33 |
24 |
halfword_access |
20958 |
1 |
|
|
T1 |
10 |
|
T3 |
36 |
|
T33 |
38 |
byte_access |
21432 |
1 |
|
|
T1 |
6 |
|
T3 |
46 |
|
T33 |
42 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
5946710 |
1 |
|
|
T1 |
4550 |
|
T2 |
24 |
|
T3 |
14408 |
auto[0] |
triple_byte_access |
10459 |
1 |
|
|
T1 |
9 |
|
T3 |
27 |
|
T33 |
12 |
auto[0] |
halfword_access |
10479 |
1 |
|
|
T1 |
5 |
|
T3 |
18 |
|
T33 |
19 |
auto[0] |
byte_access |
10716 |
1 |
|
|
T1 |
3 |
|
T3 |
23 |
|
T33 |
21 |
auto[1] |
word_access |
5946673 |
1 |
|
|
T1 |
4550 |
|
T2 |
24 |
|
T3 |
14408 |
auto[1] |
triple_byte_access |
10459 |
1 |
|
|
T1 |
9 |
|
T3 |
27 |
|
T33 |
12 |
auto[1] |
halfword_access |
10479 |
1 |
|
|
T1 |
5 |
|
T3 |
18 |
|
T33 |
19 |
auto[1] |
byte_access |
10716 |
1 |
|
|
T1 |
3 |
|
T3 |
23 |
|
T33 |
21 |