Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15129965	1			T1	15614		T2	79179		T16	1477
all_values[1]	15129965	1			T1	15614		T2	79179		T16	1477
all_values[2]	15129965	1			T1	15614		T2	79179		T16	1477

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

490583

1

T1

33

T2

6351

T16

78

auto[1]

44899312

1

T1

46809

T2

231186

T16

4353

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45166545

1

T1

41193

T2

236580

T16

4032

auto[1]

223350

1

T1

5649

T2

957

T16

399

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	191437	1			T1	9		T2	12		T16	22
all_values[0]	auto[0]	auto[1]	1310	1			T1	2		T2	2		T16	2
all_values[0]	auto[1]	auto[0]	14864078	1			T1	13722		T2	78848		T16	1322
all_values[0]	auto[1]	auto[1]	73140	1			T1	1881		T2	317		T16	131
all_values[1]	auto[0]	auto[0]	163706	1			T1	9		T2	6293		T16	49
all_values[1]	auto[0]	auto[1]	1048	1			T1	2		T2	14		T16	5
all_values[1]	auto[1]	auto[0]	14891809	1			T1	13722		T2	72567		T16	1295
all_values[1]	auto[1]	auto[1]	73402	1			T1	1881		T2	305		T16	128
all_values[2]	auto[0]	auto[0]	132146	1			T1	9		T2	25		T7	91
all_values[2]	auto[0]	auto[1]	936	1			T1	2		T2	5		T7	6
all_values[2]	auto[1]	auto[0]	14923369	1			T1	13722		T2	78835		T16	1344
all_values[2]	auto[1]	auto[1]	73514	1			T1	1881		T2	314		T16	133