Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56384 |
1 |
|
|
T1 |
2 |
|
T2 |
424 |
|
T16 |
178 |
auto[1] |
57894 |
1 |
|
|
T1 |
2490 |
|
T2 |
22 |
|
T32 |
198 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
28211 |
1 |
|
|
T1 |
658 |
|
T2 |
99 |
|
T16 |
43 |
lower_val |
28196 |
1 |
|
|
T1 |
623 |
|
T2 |
103 |
|
T16 |
48 |
zero_val |
875 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
42834 |
1 |
|
|
T1 |
578 |
|
T2 |
222 |
|
T16 |
96 |
lower_val |
42394 |
1 |
|
|
T1 |
650 |
|
T2 |
210 |
|
T16 |
82 |
zero_val |
29050 |
1 |
|
|
T1 |
1264 |
|
T2 |
14 |
|
T32 |
96 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6883 |
1 |
|
|
T2 |
51 |
|
T16 |
30 |
|
T7 |
48 |
higher_val |
higher_val |
auto[1] |
3640 |
1 |
|
|
T1 |
148 |
|
T32 |
10 |
|
T7 |
26 |
higher_val |
lower_val |
auto[0] |
6789 |
1 |
|
|
T2 |
46 |
|
T16 |
13 |
|
T7 |
24 |
higher_val |
lower_val |
auto[1] |
3658 |
1 |
|
|
T1 |
182 |
|
T32 |
13 |
|
T7 |
24 |
higher_val |
zero_val |
auto[0] |
61 |
1 |
|
|
T7 |
3 |
|
T8 |
1 |
|
T15 |
1 |
higher_val |
zero_val |
auto[1] |
7180 |
1 |
|
|
T1 |
328 |
|
T2 |
2 |
|
T32 |
34 |
lower_val |
higher_val |
auto[0] |
6839 |
1 |
|
|
T2 |
45 |
|
T16 |
21 |
|
T7 |
49 |
lower_val |
higher_val |
auto[1] |
3609 |
1 |
|
|
T1 |
160 |
|
T2 |
2 |
|
T32 |
13 |
lower_val |
lower_val |
auto[0] |
7007 |
1 |
|
|
T2 |
48 |
|
T16 |
27 |
|
T32 |
1 |
lower_val |
lower_val |
auto[1] |
3588 |
1 |
|
|
T1 |
144 |
|
T2 |
2 |
|
T32 |
15 |
lower_val |
zero_val |
auto[0] |
56 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
lower_val |
zero_val |
auto[1] |
7097 |
1 |
|
|
T1 |
318 |
|
T2 |
5 |
|
T32 |
25 |
zero_val |
higher_val |
auto[0] |
271 |
1 |
|
|
T7 |
1 |
|
T34 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
56 |
1 |
|
|
T7 |
2 |
|
T52 |
2 |
|
T54 |
1 |
zero_val |
lower_val |
auto[0] |
254 |
1 |
|
|
T2 |
3 |
|
T16 |
1 |
|
T32 |
1 |
zero_val |
lower_val |
auto[1] |
62 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
2 |
zero_val |
zero_val |
auto[0] |
175 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
4 |
zero_val |
zero_val |
auto[1] |
57 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T15 |
1 |