Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	14651299	1			T2	75372		T16	22654		T7	127911
shake	6119014	1			T1	18816		T2	23564		T16	5004
sha3	1915643	1			T2	2331		T32	204531		T7	769

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8033428

1

T1

18816

T2

25889

T16

5004

auto[1]

14652528

1

T2

75378

T16

22654

T7

127915

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	16954716	1			T1	18816		T2	88522		T16	12141
depth[0x01]	828538	1			T2	4367		T16	2451		T32	12096
depth[0x02]	877758	1			T2	2557		T16	3630		T32	13452
depth[0x03]	818093	1			T2	2040		T16	3172		T32	12479
depth[0x04]	694596	1			T2	1443		T16	2225		T32	11350
depth[0x05]	543508	1			T2	1037		T16	1672		T32	5411
depth[0x06]	399125	1			T2	630		T16	996		T32	1
depth[0x07]	329497	1			T2	214		T16	407		T7	10220
depth[0x08]	321624	1			T2	58		T16	102		T7	10132
depth[0x09]	305347	1			T2	37		T16	54		T7	9751
depth[0x0a]	613154	1			T2	362		T16	808		T7	17177

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5731240

1

T2

12745

T16

15517

T32

54789

auto[1]

16954716

1

T1

18816

T2

88522

T16

12141

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22072802

1

T1

18816

T2

100905

T16

26850

auto[1]

613154

1

T2

362

T16

808

T7

17177