Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15129965	1			T1	15614		T2	79179		T16	1477
all_pins[1]	15129965	1			T1	15614		T2	79179		T16	1477
all_pins[2]	15129965	1			T1	15614		T2	79179		T16	1477

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45001156	1			T1	44961		T2	235193		T16	4300
values[0x1]	388739	1			T1	1881		T2	2344		T16	131
transitions[0x0=>0x1]	386531	1			T1	1881		T2	2331		T16	131
transitions[0x1=>0x0]	386557	1			T1	1881		T2	2331		T16	131

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15056825	1			T1	13733		T2	78862		T16	1346
all_pins[0]	values[0x1]	73140	1			T1	1881		T2	317		T16	131
all_pins[0]	transitions[0x0=>0x1]	73124	1			T1	1881		T2	317		T16	131
all_pins[0]	transitions[0x1=>0x0]	5085	1			T2	2		T7	69		T33	11
all_pins[1]	values[0x0]	15124864	1			T1	15614		T2	79177		T16	1477
all_pins[1]	values[0x1]	5101	1			T2	2		T7	69		T33	11
all_pins[1]	transitions[0x0=>0x1]	4830	1			T2	2		T7	55		T33	11
all_pins[1]	transitions[0x1=>0x0]	310227	1			T2	2025		T7	7567		T15	4560
all_pins[2]	values[0x0]	14819467	1			T1	15614		T2	77154		T16	1477
all_pins[2]	values[0x1]	310498	1			T2	2025		T7	7581		T15	4560
all_pins[2]	transitions[0x0=>0x1]	308577	1			T2	2012		T7	7535		T15	4527
all_pins[2]	transitions[0x1=>0x0]	71245	1			T1	1881		T2	304		T16	131