Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	697	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5493	1			T2	28		T16	20		T7	30
len_601_800	12501	1			T2	58		T16	27		T7	100
len_401_600	8171	1			T2	46		T16	24		T7	37
len_201_400	4628	1			T1	251		T2	27		T16	11
len_65_200	7488	1			T1	680		T2	20		T16	5
len_min_for_xof_require_squeeze	76	1			T1	10		T141	1		T142	1
len_keccak_block_sizes[72]	62	1			T1	5		T7	1		T9	1
len_keccak_block_sizes[104]	72	1			T1	5		T142	1		T44	2
len_keccak_block_sizes[136]	85	1			T1	5		T142	3		T17	2
len_keccak_block_sizes[144]	52	1			T1	5		T7	1		T44	1
len_keccak_block_sizes[168]	57	1			T1	5		T36	1		T142	2
len_datapath_width	1074	1			T1	5		T2	3		T7	7
len_2_63	15245	1			T1	310		T2	34		T16	1
len_1	47	1			T7	1		T15	1		T44	1