Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6426095 |
1 |
|
|
T1 |
39748 |
|
T2 |
31601 |
|
T16 |
15330 |
auto[1] |
6426058 |
1 |
|
|
T1 |
39748 |
|
T2 |
31601 |
|
T16 |
15330 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
12786479 |
1 |
|
|
T1 |
77624 |
|
T2 |
62916 |
|
T16 |
30526 |
triple_byte_access |
22006 |
1 |
|
|
T1 |
620 |
|
T2 |
98 |
|
T16 |
30 |
halfword_access |
21532 |
1 |
|
|
T1 |
632 |
|
T2 |
84 |
|
T16 |
56 |
byte_access |
22136 |
1 |
|
|
T1 |
620 |
|
T2 |
104 |
|
T16 |
48 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6393258 |
1 |
|
|
T1 |
38812 |
|
T2 |
31458 |
|
T16 |
15263 |
auto[0] |
triple_byte_access |
11003 |
1 |
|
|
T1 |
310 |
|
T2 |
49 |
|
T16 |
15 |
auto[0] |
halfword_access |
10766 |
1 |
|
|
T1 |
316 |
|
T2 |
42 |
|
T16 |
28 |
auto[0] |
byte_access |
11068 |
1 |
|
|
T1 |
310 |
|
T2 |
52 |
|
T16 |
24 |
auto[1] |
word_access |
6393221 |
1 |
|
|
T1 |
38812 |
|
T2 |
31458 |
|
T16 |
15263 |
auto[1] |
triple_byte_access |
11003 |
1 |
|
|
T1 |
310 |
|
T2 |
49 |
|
T16 |
15 |
auto[1] |
halfword_access |
10766 |
1 |
|
|
T1 |
316 |
|
T2 |
42 |
|
T16 |
28 |
auto[1] |
byte_access |
11068 |
1 |
|
|
T1 |
310 |
|
T2 |
52 |
|
T16 |
24 |