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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.20 97.89 92.58 99.89 76.76 95.53 98.89 97.88


Total test records in report: 870
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T125 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3733171644 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:25 PM PDT 24 378797675 ps
T761 /workspace/coverage/cover_reg_top/47.kmac_intr_test.82512552 Aug 18 04:59:40 PM PDT 24 Aug 18 04:59:41 PM PDT 24 38518365 ps
T91 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2732450138 Aug 18 04:59:22 PM PDT 24 Aug 18 04:59:23 PM PDT 24 51317507 ps
T762 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2027757522 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:23 PM PDT 24 128325985 ps
T763 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.201188060 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:11 PM PDT 24 37715457 ps
T764 /workspace/coverage/cover_reg_top/18.kmac_intr_test.1571684608 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 21792352 ps
T176 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3000195834 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:13 PM PDT 24 183130955 ps
T765 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3596885803 Aug 18 04:59:19 PM PDT 24 Aug 18 04:59:23 PM PDT 24 51859232 ps
T766 /workspace/coverage/cover_reg_top/8.kmac_intr_test.1960808062 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:10 PM PDT 24 14536567 ps
T767 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1676502618 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:24 PM PDT 24 81751266 ps
T768 /workspace/coverage/cover_reg_top/31.kmac_intr_test.190599955 Aug 18 04:59:30 PM PDT 24 Aug 18 04:59:31 PM PDT 24 24856862 ps
T769 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2568633001 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:22 PM PDT 24 135784007 ps
T770 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2410013570 Aug 18 04:58:55 PM PDT 24 Aug 18 04:59:07 PM PDT 24 2774415080 ps
T771 /workspace/coverage/cover_reg_top/45.kmac_intr_test.255166166 Aug 18 04:59:33 PM PDT 24 Aug 18 04:59:33 PM PDT 24 16839308 ps
T772 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2232301473 Aug 18 04:58:52 PM PDT 24 Aug 18 04:58:53 PM PDT 24 11089280 ps
T92 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.92018148 Aug 18 04:59:00 PM PDT 24 Aug 18 04:59:02 PM PDT 24 593243251 ps
T773 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1800123418 Aug 18 04:59:13 PM PDT 24 Aug 18 04:59:15 PM PDT 24 31195632 ps
T774 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.330078275 Aug 18 04:59:23 PM PDT 24 Aug 18 04:59:26 PM PDT 24 688806760 ps
T93 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2231112996 Aug 18 04:59:00 PM PDT 24 Aug 18 04:59:02 PM PDT 24 30709951 ps
T775 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1463787210 Aug 18 04:59:08 PM PDT 24 Aug 18 04:59:11 PM PDT 24 131390108 ps
T776 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1328564956 Aug 18 04:59:12 PM PDT 24 Aug 18 04:59:14 PM PDT 24 1634976141 ps
T777 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3072155284 Aug 18 04:59:12 PM PDT 24 Aug 18 04:59:14 PM PDT 24 381641886 ps
T94 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2844924447 Aug 18 04:59:14 PM PDT 24 Aug 18 04:59:17 PM PDT 24 105382254 ps
T778 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2257305329 Aug 18 04:59:04 PM PDT 24 Aug 18 04:59:05 PM PDT 24 25848173 ps
T779 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2626987162 Aug 18 04:59:19 PM PDT 24 Aug 18 04:59:20 PM PDT 24 19363843 ps
T780 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1653113253 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 22758279 ps
T781 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1904312452 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:12 PM PDT 24 105942623 ps
T782 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1386094044 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:11 PM PDT 24 22661109 ps
T783 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.399564561 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:05 PM PDT 24 49934920 ps
T784 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.55598015 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:04 PM PDT 24 22861594 ps
T785 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.236993240 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:11 PM PDT 24 91305888 ps
T786 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2394605007 Aug 18 04:59:19 PM PDT 24 Aug 18 04:59:20 PM PDT 24 94012427 ps
T787 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.121645536 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:22 PM PDT 24 51790737 ps
T788 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1357173297 Aug 18 04:59:12 PM PDT 24 Aug 18 04:59:13 PM PDT 24 101835245 ps
T789 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1050075220 Aug 18 04:58:54 PM PDT 24 Aug 18 04:58:55 PM PDT 24 39231765 ps
T790 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1224097453 Aug 18 04:59:08 PM PDT 24 Aug 18 04:59:10 PM PDT 24 79539683 ps
T791 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3008665759 Aug 18 04:58:53 PM PDT 24 Aug 18 04:58:56 PM PDT 24 114380224 ps
T792 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.125064821 Aug 18 04:59:00 PM PDT 24 Aug 18 04:59:03 PM PDT 24 161173095 ps
T177 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1012515667 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:14 PM PDT 24 795097874 ps
T793 /workspace/coverage/cover_reg_top/23.kmac_intr_test.43179857 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 14465561 ps
T794 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3236770478 Aug 18 04:59:11 PM PDT 24 Aug 18 04:59:12 PM PDT 24 42089326 ps
T795 /workspace/coverage/cover_reg_top/26.kmac_intr_test.3382954476 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:32 PM PDT 24 43978690 ps
T796 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1141956884 Aug 18 04:59:12 PM PDT 24 Aug 18 04:59:15 PM PDT 24 259495049 ps
T797 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3545577864 Aug 18 04:58:55 PM PDT 24 Aug 18 04:58:56 PM PDT 24 55458151 ps
T798 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1078762659 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:33 PM PDT 24 25621863 ps
T799 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3839815232 Aug 18 04:58:52 PM PDT 24 Aug 18 04:58:53 PM PDT 24 29743573 ps
T800 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.270769418 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:03 PM PDT 24 23535972 ps
T801 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2658286254 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:11 PM PDT 24 105020998 ps
T802 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2765116086 Aug 18 04:59:24 PM PDT 24 Aug 18 04:59:26 PM PDT 24 45574618 ps
T803 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2306872160 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:22 PM PDT 24 38684364 ps
T804 /workspace/coverage/cover_reg_top/33.kmac_intr_test.3864722107 Aug 18 04:59:33 PM PDT 24 Aug 18 04:59:34 PM PDT 24 21946087 ps
T805 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2029113693 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:05 PM PDT 24 94346038 ps
T806 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.469279737 Aug 18 04:59:22 PM PDT 24 Aug 18 04:59:24 PM PDT 24 135176179 ps
T807 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2209689248 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:11 PM PDT 24 44150746 ps
T808 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.63648325 Aug 18 04:59:00 PM PDT 24 Aug 18 04:59:01 PM PDT 24 25948680 ps
T809 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1185635503 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:21 PM PDT 24 131250868 ps
T810 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2227717098 Aug 18 04:59:30 PM PDT 24 Aug 18 04:59:31 PM PDT 24 41901075 ps
T811 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1539592630 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:13 PM PDT 24 622956755 ps
T812 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2207624504 Aug 18 04:59:18 PM PDT 24 Aug 18 04:59:19 PM PDT 24 84358748 ps
T813 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3001290255 Aug 18 04:59:30 PM PDT 24 Aug 18 04:59:31 PM PDT 24 39972387 ps
T814 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2950006711 Aug 18 04:59:07 PM PDT 24 Aug 18 04:59:08 PM PDT 24 30235509 ps
T815 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.843724291 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:20 PM PDT 24 3025309841 ps
T816 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1225797441 Aug 18 04:59:05 PM PDT 24 Aug 18 04:59:06 PM PDT 24 194450087 ps
T817 /workspace/coverage/cover_reg_top/37.kmac_intr_test.1132625879 Aug 18 04:59:33 PM PDT 24 Aug 18 04:59:34 PM PDT 24 16898440 ps
T818 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.155937782 Aug 18 04:59:30 PM PDT 24 Aug 18 04:59:33 PM PDT 24 100017575 ps
T819 /workspace/coverage/cover_reg_top/40.kmac_intr_test.3200085960 Aug 18 04:59:30 PM PDT 24 Aug 18 04:59:31 PM PDT 24 188636768 ps
T147 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1114544977 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:10 PM PDT 24 61588503 ps
T820 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1918138532 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:12 PM PDT 24 77732310 ps
T821 /workspace/coverage/cover_reg_top/27.kmac_intr_test.1163533582 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:32 PM PDT 24 12604759 ps
T822 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.731635256 Aug 18 04:58:55 PM PDT 24 Aug 18 04:58:58 PM PDT 24 305366351 ps
T823 /workspace/coverage/cover_reg_top/32.kmac_intr_test.4211680459 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 39244184 ps
T824 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3739154441 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:06 PM PDT 24 52007788 ps
T825 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2346375156 Aug 18 04:59:13 PM PDT 24 Aug 18 04:59:15 PM PDT 24 95964955 ps
T826 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3987547724 Aug 18 04:59:15 PM PDT 24 Aug 18 04:59:16 PM PDT 24 16711165 ps
T827 /workspace/coverage/cover_reg_top/17.kmac_intr_test.4169084068 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 15150293 ps
T828 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1987356689 Aug 18 04:59:04 PM PDT 24 Aug 18 04:59:07 PM PDT 24 223702858 ps
T829 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2375511252 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:33 PM PDT 24 40630144 ps
T830 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3627909200 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:23 PM PDT 24 46584341 ps
T831 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2879765829 Aug 18 04:59:22 PM PDT 24 Aug 18 04:59:23 PM PDT 24 23253842 ps
T832 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2157885650 Aug 18 04:58:52 PM PDT 24 Aug 18 04:58:54 PM PDT 24 104903395 ps
T833 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2710526435 Aug 18 04:59:18 PM PDT 24 Aug 18 04:59:20 PM PDT 24 152436777 ps
T834 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2572424612 Aug 18 04:59:08 PM PDT 24 Aug 18 04:59:09 PM PDT 24 91997549 ps
T835 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.451628793 Aug 18 04:58:55 PM PDT 24 Aug 18 04:58:57 PM PDT 24 205490526 ps
T836 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2890102097 Aug 18 04:59:01 PM PDT 24 Aug 18 04:59:02 PM PDT 24 15579498 ps
T837 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.206788646 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:33 PM PDT 24 148862551 ps
T838 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2639337547 Aug 18 04:59:21 PM PDT 24 Aug 18 04:59:24 PM PDT 24 413736557 ps
T839 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.162914354 Aug 18 04:59:10 PM PDT 24 Aug 18 04:59:20 PM PDT 24 3824312303 ps
T840 /workspace/coverage/cover_reg_top/44.kmac_intr_test.4164656432 Aug 18 04:59:34 PM PDT 24 Aug 18 04:59:35 PM PDT 24 40174955 ps
T841 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.306945877 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:22 PM PDT 24 386136944 ps
T178 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3000182243 Aug 18 04:59:14 PM PDT 24 Aug 18 04:59:19 PM PDT 24 97904278 ps
T842 /workspace/coverage/cover_reg_top/25.kmac_intr_test.4103600718 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:31 PM PDT 24 16475040 ps
T843 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1669414164 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:05 PM PDT 24 30095317 ps
T844 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.499348496 Aug 18 04:58:50 PM PDT 24 Aug 18 04:58:51 PM PDT 24 29933796 ps
T845 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2208559686 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:03 PM PDT 24 53951020 ps
T846 /workspace/coverage/cover_reg_top/21.kmac_intr_test.3217211650 Aug 18 04:59:33 PM PDT 24 Aug 18 04:59:34 PM PDT 24 43950870 ps
T847 /workspace/coverage/cover_reg_top/22.kmac_intr_test.3891805662 Aug 18 04:59:33 PM PDT 24 Aug 18 04:59:34 PM PDT 24 132615497 ps
T848 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1995490248 Aug 18 04:59:00 PM PDT 24 Aug 18 04:59:01 PM PDT 24 143029445 ps
T849 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1967405010 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:35 PM PDT 24 353895032 ps
T850 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4045128436 Aug 18 04:59:09 PM PDT 24 Aug 18 04:59:11 PM PDT 24 42506957 ps
T851 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2016972258 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:33 PM PDT 24 226062992 ps
T852 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2239069394 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:22 PM PDT 24 96354726 ps
T853 /workspace/coverage/cover_reg_top/11.kmac_intr_test.4005356282 Aug 18 04:59:08 PM PDT 24 Aug 18 04:59:09 PM PDT 24 19717227 ps
T854 /workspace/coverage/cover_reg_top/35.kmac_intr_test.379786281 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:32 PM PDT 24 24834189 ps
T855 /workspace/coverage/cover_reg_top/5.kmac_intr_test.2494509509 Aug 18 04:59:11 PM PDT 24 Aug 18 04:59:12 PM PDT 24 40912142 ps
T856 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.780032354 Aug 18 04:59:32 PM PDT 24 Aug 18 04:59:34 PM PDT 24 35949753 ps
T857 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.571012865 Aug 18 04:59:23 PM PDT 24 Aug 18 04:59:26 PM PDT 24 180489102 ps
T858 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1515136555 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:04 PM PDT 24 42844642 ps
T148 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3072429823 Aug 18 04:58:51 PM PDT 24 Aug 18 04:58:53 PM PDT 24 43350648 ps
T859 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.4188685080 Aug 18 04:59:22 PM PDT 24 Aug 18 04:59:23 PM PDT 24 241547439 ps
T860 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.231691500 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:08 PM PDT 24 768343362 ps
T861 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1330956431 Aug 18 04:59:12 PM PDT 24 Aug 18 04:59:13 PM PDT 24 43172058 ps
T862 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3736813304 Aug 18 04:59:02 PM PDT 24 Aug 18 04:59:03 PM PDT 24 39755225 ps
T863 /workspace/coverage/cover_reg_top/16.kmac_intr_test.2225877113 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:21 PM PDT 24 13697894 ps
T864 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.438971535 Aug 18 04:59:19 PM PDT 24 Aug 18 04:59:21 PM PDT 24 111069377 ps
T865 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.825273947 Aug 18 04:59:01 PM PDT 24 Aug 18 04:59:04 PM PDT 24 237124971 ps
T866 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3559942862 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:05 PM PDT 24 228161924 ps
T867 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1408666044 Aug 18 04:59:11 PM PDT 24 Aug 18 04:59:16 PM PDT 24 205003485 ps
T868 /workspace/coverage/cover_reg_top/19.kmac_intr_test.866402084 Aug 18 04:59:31 PM PDT 24 Aug 18 04:59:31 PM PDT 24 27452768 ps
T869 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1595109395 Aug 18 04:59:03 PM PDT 24 Aug 18 04:59:04 PM PDT 24 14284024 ps
T870 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2442754603 Aug 18 04:59:20 PM PDT 24 Aug 18 04:59:25 PM PDT 24 294879978 ps

Test location /workspace/coverage/default/48.kmac_stress_all.2431269375
Short name T7
Test name
Test status
Simulation time 54764274197 ps
CPU time 1023.85 seconds
Started Aug 18 05:07:48 PM PDT 24
Finished Aug 18 05:24:53 PM PDT 24
Peak memory 338928 kb
Host smart-2f8b2796-a071-4576-869d-7d52daf975cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2431269375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.2431269375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1408761829
Short name T84
Test name
Test status
Simulation time 450349394 ps
CPU time 3.05 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 219896 kb
Host smart-950793d1-8a6b-460e-8ef9-9c12ebb2b088
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408761829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1408761829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.280081114
Short name T13
Test name
Test status
Simulation time 107674981 ps
CPU time 1.29 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:04:14 PM PDT 24
Peak memory 226632 kb
Host smart-35e119ab-3e57-444e-87d0-64fa66a0cee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280081114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.280081114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.3954564317
Short name T42
Test name
Test status
Simulation time 2809244853 ps
CPU time 98.35 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:05:51 PM PDT 24
Peak memory 259856 kb
Host smart-96f58900-3e82-46cd-b039-0605a2154bbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954564317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.3954564317 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.443118563
Short name T26
Test name
Test status
Simulation time 4179840728 ps
CPU time 49.38 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:04:50 PM PDT 24
Peak memory 259632 kb
Host smart-b4d58dd9-52fb-4017-84c0-e5dacc5f9819
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443118563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.443118563 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/46.kmac_key_error.1014636585
Short name T5
Test name
Test status
Simulation time 1877748676 ps
CPU time 3.17 seconds
Started Aug 18 05:07:24 PM PDT 24
Finished Aug 18 05:07:27 PM PDT 24
Peak memory 226520 kb
Host smart-7ffdeafc-7415-4bc8-bd41-5014c7c55913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014636585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1014636585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.2892646505
Short name T24
Test name
Test status
Simulation time 557508586 ps
CPU time 11.67 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:05:34 PM PDT 24
Peak memory 234996 kb
Host smart-f934d2f2-848b-4b72-aeef-26dbd0746a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892646505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2892646505 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_error.1962213414
Short name T22
Test name
Test status
Simulation time 37455721184 ps
CPU time 522.31 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:14:37 PM PDT 24
Peak memory 644396 kb
Host smart-9a9a9d7d-1f95-47eb-9ff6-12e7a4522314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962213414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1962213414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.3361384884
Short name T157
Test name
Test status
Simulation time 25241548 ps
CPU time 0.82 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 215792 kb
Host smart-617a91e5-de48-4ea4-9f51-3a2d865240c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361384884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3361384884 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1560254285
Short name T367
Test name
Test status
Simulation time 123929049975 ps
CPU time 115.35 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:05:56 PM PDT 24
Peak memory 225400 kb
Host smart-667916e1-2ccb-48db-a68e-ad7464c93183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560254285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1560254285 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4099858452
Short name T118
Test name
Test status
Simulation time 672149153 ps
CPU time 4.81 seconds
Started Aug 18 04:59:15 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 215936 kb
Host smart-d8bc6b55-5d7e-43a4-bf72-e418e22b8a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099858452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.40998
58452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3010735486
Short name T30
Test name
Test status
Simulation time 211686522 ps
CPU time 2.06 seconds
Started Aug 18 05:03:48 PM PDT 24
Finished Aug 18 05:03:50 PM PDT 24
Peak memory 226608 kb
Host smart-b5e5d556-52a7-4e68-b870-3181d179e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010735486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3010735486 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.2500286420
Short name T63
Test name
Test status
Simulation time 39124574 ps
CPU time 1.16 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:04:14 PM PDT 24
Peak memory 218348 kb
Host smart-53f50cfc-6691-4794-b5c0-ea587d1a6a0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2500286420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2500286420 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.3171605812
Short name T77
Test name
Test status
Simulation time 88371411 ps
CPU time 1.49 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:05:36 PM PDT 24
Peak memory 226504 kb
Host smart-7bc87a21-25f0-4e8f-b8cd-cb20678903eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171605812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3171605812 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.464707415
Short name T29
Test name
Test status
Simulation time 4899551618 ps
CPU time 55.89 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:06:30 PM PDT 24
Peak memory 251548 kb
Host smart-e4a9662d-1039-46e8-8f14-b29bb4b06d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464707415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.464707415 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.369680769
Short name T76
Test name
Test status
Simulation time 42914209 ps
CPU time 0.83 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:03:38 PM PDT 24
Peak memory 220376 kb
Host smart-ebef436f-4b5e-4cfa-ace2-49cad34c4225
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369680769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.369680769 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.92018148
Short name T92
Test name
Test status
Simulation time 593243251 ps
CPU time 2.32 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 218564 kb
Host smart-731a99da-5070-4889-9ee4-a6d7a933f3da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92018148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_s
hadow_reg_errors_with_csr_rw.92018148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1658928120
Short name T36
Test name
Test status
Simulation time 9372617770 ps
CPU time 383.49 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:13:48 PM PDT 24
Peak memory 336868 kb
Host smart-b394ead8-f6f6-4b49-9ed9-c1f1c1050f86
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658928120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1
658928120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1114544977
Short name T147
Test name
Test status
Simulation time 61588503 ps
CPU time 1.22 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 216012 kb
Host smart-cfeb8036-5e20-4c67-8444-94f9693591c0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114544977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.1114544977 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/1.kmac_alert_test.3420332751
Short name T100
Test name
Test status
Simulation time 16388737 ps
CPU time 0.85 seconds
Started Aug 18 05:03:48 PM PDT 24
Finished Aug 18 05:03:49 PM PDT 24
Peak memory 218156 kb
Host smart-2a3f4179-fd9b-4295-9bcd-2996300c8921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420332751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3420332751 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1136804596
Short name T87
Test name
Test status
Simulation time 43751602 ps
CPU time 2.44 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 219084 kb
Host smart-f9e08e52-b1d2-4a44-bb45-df30f5967b13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136804596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1136804596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.394458566
Short name T8
Test name
Test status
Simulation time 62362226 ps
CPU time 1.23 seconds
Started Aug 18 05:03:50 PM PDT 24
Finished Aug 18 05:03:51 PM PDT 24
Peak memory 226528 kb
Host smart-0dca6689-05cd-4678-a8fb-9e34b9039aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394458566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.394458566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.788265807
Short name T50
Test name
Test status
Simulation time 328775676 ps
CPU time 16.52 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:19 PM PDT 24
Peak memory 235924 kb
Host smart-d049899f-de13-424b-bf94-efc74017ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788265807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.788265807 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.1071334870
Short name T59
Test name
Test status
Simulation time 211631127 ps
CPU time 1.27 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:12 PM PDT 24
Peak memory 226576 kb
Host smart-5ee1906d-7f38-4c2f-9df5-79cbb5e5df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071334870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1071334870 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_stress_all.305329261
Short name T15
Test name
Test status
Simulation time 155444288350 ps
CPU time 2983.08 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:53:54 PM PDT 24
Peak memory 1565892 kb
Host smart-4d2c47af-6b6b-498b-9c87-99392f86d15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=305329261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.305329261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.119769027
Short name T80
Test name
Test status
Simulation time 14253069754 ps
CPU time 57.54 seconds
Started Aug 18 05:03:49 PM PDT 24
Finished Aug 18 05:04:47 PM PDT 24
Peak memory 257936 kb
Host smart-136b862e-78ac-4f3f-9bad-e2b97e9f8de0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119769027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.119769027 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.1856440856
Short name T66
Test name
Test status
Simulation time 8111617174 ps
CPU time 97.64 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:07:43 PM PDT 24
Peak memory 288408 kb
Host smart-223f6455-9cae-4b4f-ab28-82442f63dee8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856440856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1
856440856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_app.4018026455
Short name T95
Test name
Test status
Simulation time 2961101700 ps
CPU time 128.66 seconds
Started Aug 18 05:03:48 PM PDT 24
Finished Aug 18 05:05:57 PM PDT 24
Peak memory 265192 kb
Host smart-3e9e97f7-7a07-4bf0-8332-9652f74ec361
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018026455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.4018026455 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.969175422
Short name T119
Test name
Test status
Simulation time 354019247 ps
CPU time 4.03 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 216160 kb
Host smart-1e589677-badf-42d1-88a7-63f02694abf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969175422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.969175
422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.274280970
Short name T164
Test name
Test status
Simulation time 16868818 ps
CPU time 0.78 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 215820 kb
Host smart-10aa3216-4b2b-438a-8f1e-66a5bdf88255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274280970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.274280970 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.1519171338
Short name T1
Test name
Test status
Simulation time 44782645825 ps
CPU time 472.37 seconds
Started Aug 18 05:03:39 PM PDT 24
Finished Aug 18 05:11:31 PM PDT 24
Peak memory 358908 kb
Host smart-e71fcd70-07b7-4465-92c2-5433309af716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1519171338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1519171338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_error.1352462712
Short name T163
Test name
Test status
Simulation time 23131047624 ps
CPU time 161.85 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:07:12 PM PDT 24
Peak memory 355572 kb
Host smart-cb949258-4556-4969-949f-6326351ada79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352462712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1352462712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2157885650
Short name T832
Test name
Test status
Simulation time 104903395 ps
CPU time 1.75 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:54 PM PDT 24
Peak memory 216384 kb
Host smart-30d78f13-5a8e-496a-b450-4fba9f9c29d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157885650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2157885650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1033856367
Short name T179
Test name
Test status
Simulation time 449595950 ps
CPU time 7.96 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 216092 kb
Host smart-e2a974e9-6cda-4c38-b98f-b53430ba4447
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033856367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1033856
367 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1891017525
Short name T171
Test name
Test status
Simulation time 154522697 ps
CPU time 2.57 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 215968 kb
Host smart-bcbdc2f6-f6de-4a4d-8564-b546a84ffb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891017525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.18910
17525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3000182243
Short name T178
Test name
Test status
Simulation time 97904278 ps
CPU time 4.02 seconds
Started Aug 18 04:59:14 PM PDT 24
Finished Aug 18 04:59:19 PM PDT 24
Peak memory 216060 kb
Host smart-87db0d79-e8fe-4382-aa07-ed37a64f96ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000182243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3000
182243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3618535846
Short name T174
Test name
Test status
Simulation time 693884350 ps
CPU time 3.95 seconds
Started Aug 18 04:59:23 PM PDT 24
Finished Aug 18 04:59:27 PM PDT 24
Peak memory 216064 kb
Host smart-cff334c1-7248-4c9d-9e41-555d3c010ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618535846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3618
535846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.kmac_app.1115479333
Short name T114
Test name
Test status
Simulation time 7915833627 ps
CPU time 262.5 seconds
Started Aug 18 05:04:37 PM PDT 24
Finished Aug 18 05:08:59 PM PDT 24
Peak memory 297344 kb
Host smart-7a31928d-26c6-4326-8ee5-5c75ed522e2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115479333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1115479333 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.499348496
Short name T844
Test name
Test status
Simulation time 29933796 ps
CPU time 1 seconds
Started Aug 18 04:58:50 PM PDT 24
Finished Aug 18 04:58:51 PM PDT 24
Peak memory 216368 kb
Host smart-d64d09ef-b6f9-4222-a802-ae60b855bff5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499348496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.499348496 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3733171644
Short name T125
Test name
Test status
Simulation time 378797675 ps
CPU time 4.08 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:25 PM PDT 24
Peak memory 216148 kb
Host smart-d6e948f7-1ff4-4def-85bb-4cedda956bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733171644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3733
171644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.1467744450
Short name T60
Test name
Test status
Simulation time 4584764813 ps
CPU time 108.81 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:06:20 PM PDT 24
Peak memory 301652 kb
Host smart-387cf42b-ca09-41a3-8950-e1efb014ce8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467744450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1
467744450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2410013570
Short name T770
Test name
Test status
Simulation time 2774415080 ps
CPU time 11.8 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 216208 kb
Host smart-579779c8-090d-426a-b8a6-53929fc457e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410013570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2410013
570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1050075220
Short name T789
Test name
Test status
Simulation time 39231765 ps
CPU time 1.17 seconds
Started Aug 18 04:58:54 PM PDT 24
Finished Aug 18 04:58:55 PM PDT 24
Peak memory 215960 kb
Host smart-cb2225bc-6ccf-4cb2-9baa-ab9e312b4662
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050075220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1050075
220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.187980021
Short name T131
Test name
Test status
Simulation time 186807423 ps
CPU time 2.13 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:55 PM PDT 24
Peak memory 221644 kb
Host smart-667f0470-100f-4d15-a52f-217eee41be0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187980021 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.187980021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.3500872722
Short name T718
Test name
Test status
Simulation time 27204105 ps
CPU time 0.94 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 215740 kb
Host smart-2f27fa2c-4096-4406-8d4d-6b96559273a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500872722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3500872722 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.1784732502
Short name T750
Test name
Test status
Simulation time 60217322 ps
CPU time 0.8 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:58:54 PM PDT 24
Peak memory 215688 kb
Host smart-c0c9dad7-b507-4cf7-8b44-d6ee7bbbc79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784732502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1784732502 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3072429823
Short name T148
Test name
Test status
Simulation time 43350648 ps
CPU time 1.49 seconds
Started Aug 18 04:58:51 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 216004 kb
Host smart-54f689ec-3037-4915-923c-df7eff058c39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072429823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3072429823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3839815232
Short name T799
Test name
Test status
Simulation time 29743573 ps
CPU time 0.76 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 216012 kb
Host smart-5c66547c-c6c5-43bb-b174-e024c92ec5c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839815232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3839815232
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.451628793
Short name T835
Test name
Test status
Simulation time 205490526 ps
CPU time 1.68 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:58:57 PM PDT 24
Peak memory 216192 kb
Host smart-d221c7a3-bded-4ac7-8d71-908192e47ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451628793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_
outstanding.451628793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2807730352
Short name T81
Test name
Test status
Simulation time 61611429 ps
CPU time 1.03 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 215900 kb
Host smart-1a6ef86d-bb91-4616-9222-83d6b5d0d2fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807730352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2807730352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.731635256
Short name T822
Test name
Test status
Simulation time 305366351 ps
CPU time 2.38 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:58:58 PM PDT 24
Peak memory 216224 kb
Host smart-17c51139-e1d9-4890-9d4d-ce449ece9790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731635256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.731635256 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.231691500
Short name T860
Test name
Test status
Simulation time 768343362 ps
CPU time 4.85 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:08 PM PDT 24
Peak memory 216096 kb
Host smart-d51bed56-e2e8-4bf8-ba40-ea3ec3b60bcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231691500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.23169150
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1996587251
Short name T156
Test name
Test status
Simulation time 4256980916 ps
CPU time 10.96 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 216212 kb
Host smart-8aea5d29-2bcf-469c-a702-e9a26cbfa3f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996587251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1996587
251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2890102097
Short name T836
Test name
Test status
Simulation time 15579498 ps
CPU time 1.03 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 215744 kb
Host smart-bef61399-0d10-4996-a94d-9279f0c7e2c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890102097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2890102
097 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2975608975
Short name T103
Test name
Test status
Simulation time 68419781 ps
CPU time 2.19 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 220468 kb
Host smart-2bd6b1d6-73b5-4fe4-a55e-dbfd7e8cca9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975608975 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2975608975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2208559686
Short name T845
Test name
Test status
Simulation time 53951020 ps
CPU time 0.93 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 215800 kb
Host smart-d9b15ecd-f5d8-4de9-a250-5224f7a20157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208559686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2208559686 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.1367120592
Short name T737
Test name
Test status
Simulation time 12339573 ps
CPU time 0.81 seconds
Started Aug 18 04:58:59 PM PDT 24
Finished Aug 18 04:59:00 PM PDT 24
Peak memory 215852 kb
Host smart-5c7c7843-4f0a-47ae-9320-ba209ee2d622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367120592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1367120592 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3545577864
Short name T797
Test name
Test status
Simulation time 55458151 ps
CPU time 1.19 seconds
Started Aug 18 04:58:55 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 216100 kb
Host smart-599c4413-1552-47c3-8813-819a9aed6542
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545577864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3545577864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.2232301473
Short name T772
Test name
Test status
Simulation time 11089280 ps
CPU time 0.72 seconds
Started Aug 18 04:58:52 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 215740 kb
Host smart-29a19171-79f3-4353-9186-56533e7ae03f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232301473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2232301473
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2029113693
Short name T805
Test name
Test status
Simulation time 94346038 ps
CPU time 2.37 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216160 kb
Host smart-4777eaa0-37ea-4d85-942d-c466e4547ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029113693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2029113693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3008665759
Short name T791
Test name
Test status
Simulation time 114380224 ps
CPU time 2.45 seconds
Started Aug 18 04:58:53 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 218812 kb
Host smart-50b92eaf-d967-4172-8b2b-fe9405557a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008665759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3008665759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3964746027
Short name T730
Test name
Test status
Simulation time 115504191 ps
CPU time 2.85 seconds
Started Aug 18 04:58:50 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 216384 kb
Host smart-38c4a0ed-4e09-4edd-9aa2-ccaa83f09831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964746027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3964746027 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4045128436
Short name T850
Test name
Test status
Simulation time 42506957 ps
CPU time 1.54 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 217248 kb
Host smart-1b28b7a6-ad27-4027-af70-b088a83199ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045128436 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.4045128436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2879765829
Short name T831
Test name
Test status
Simulation time 23253842 ps
CPU time 0.96 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 215828 kb
Host smart-c424d4d0-3328-4668-9ea5-6aca6c07c1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879765829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2879765829 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.335426563
Short name T739
Test name
Test status
Simulation time 10657117 ps
CPU time 0.78 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 215716 kb
Host smart-856e4ac6-a8b2-4a8a-9838-ddf7a1651dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335426563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.335426563 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1328564956
Short name T776
Test name
Test status
Simulation time 1634976141 ps
CPU time 2.35 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216060 kb
Host smart-83e23ebd-981b-4bc1-9e50-4de3d438af9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328564956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1328564956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2732450138
Short name T91
Test name
Test status
Simulation time 51317507 ps
CPU time 0.86 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 215772 kb
Host smart-ba99f32d-de09-4343-8da2-728c68a159bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732450138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.2732450138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2844924447
Short name T94
Test name
Test status
Simulation time 105382254 ps
CPU time 2.92 seconds
Started Aug 18 04:59:14 PM PDT 24
Finished Aug 18 04:59:17 PM PDT 24
Peak memory 216276 kb
Host smart-f6a12e39-4cd9-4b08-acc9-89cd6738d020
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844924447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2844924447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1539592630
Short name T811
Test name
Test status
Simulation time 622956755 ps
CPU time 4 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 216128 kb
Host smart-baa2073a-38a9-4529-a6ec-fdfccbab31eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539592630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1539592630 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.976467733
Short name T734
Test name
Test status
Simulation time 82152847 ps
CPU time 1.71 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 220176 kb
Host smart-9f96310b-23a3-4ce0-a0f3-3566dfef1ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976467733 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.976467733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2658286254
Short name T801
Test name
Test status
Simulation time 105020998 ps
CPU time 0.93 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 215888 kb
Host smart-b876f905-5b0c-447b-928d-58369b422a9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658286254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2658286254 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.4005356282
Short name T853
Test name
Test status
Simulation time 19717227 ps
CPU time 0.76 seconds
Started Aug 18 04:59:08 PM PDT 24
Finished Aug 18 04:59:09 PM PDT 24
Peak memory 215748 kb
Host smart-9ba874a7-808a-4624-8327-46a2c40505bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005356282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.4005356282 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1438540745
Short name T751
Test name
Test status
Simulation time 336708923 ps
CPU time 1.62 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 216032 kb
Host smart-14da4574-9642-42d6-a1c0-cde40e9fd721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438540745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1438540745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2880239399
Short name T83
Test name
Test status
Simulation time 76836439 ps
CPU time 1.2 seconds
Started Aug 18 04:59:13 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216288 kb
Host smart-1d982638-f190-4739-a105-15a3250dc734
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880239399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2880239399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1933795559
Short name T150
Test name
Test status
Simulation time 151831002 ps
CPU time 2.79 seconds
Started Aug 18 04:59:15 PM PDT 24
Finished Aug 18 04:59:17 PM PDT 24
Peak memory 219680 kb
Host smart-b34f8636-6d54-4092-b90c-62e3b44015e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933795559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1933795559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.2265812604
Short name T128
Test name
Test status
Simulation time 83627174 ps
CPU time 2.47 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 216092 kb
Host smart-606841aa-30e8-4646-b4e6-f30283566edb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265812604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2265812604 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3000195834
Short name T176
Test name
Test status
Simulation time 183130955 ps
CPU time 4.14 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 216156 kb
Host smart-f6d17b5a-5425-4e03-9492-7116faec55f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000195834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3000
195834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.292443872
Short name T742
Test name
Test status
Simulation time 355853009 ps
CPU time 2.78 seconds
Started Aug 18 04:59:15 PM PDT 24
Finished Aug 18 04:59:18 PM PDT 24
Peak memory 221780 kb
Host smart-6d975a75-e0b7-4ab4-a91a-f48ab3fc0d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292443872 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.292443872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.4002948348
Short name T716
Test name
Test status
Simulation time 45979015 ps
CPU time 1.09 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 216140 kb
Host smart-08daf0b4-4830-4780-bc63-686fc0fe90ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002948348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.4002948348 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.2852710721
Short name T752
Test name
Test status
Simulation time 16525342 ps
CPU time 0.79 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 215736 kb
Host smart-81afe6e1-6ad1-4a7e-bfbd-72bb9c7d5854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852710721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2852710721 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3072155284
Short name T777
Test name
Test status
Simulation time 381641886 ps
CPU time 2.71 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216032 kb
Host smart-1ea4afa5-370c-451d-9cab-b5f703e8cbff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072155284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3072155284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1357173297
Short name T788
Test name
Test status
Simulation time 101835245 ps
CPU time 1.07 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 216120 kb
Host smart-766dab2a-d1d1-400b-9802-78c916a85169
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357173297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1357173297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2247985042
Short name T90
Test name
Test status
Simulation time 63438948 ps
CPU time 1.94 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 219232 kb
Host smart-024c0f50-780f-4046-ad88-e89886b18413
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247985042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2247985042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.725686688
Short name T126
Test name
Test status
Simulation time 607361857 ps
CPU time 3.58 seconds
Started Aug 18 04:59:13 PM PDT 24
Finished Aug 18 04:59:17 PM PDT 24
Peak memory 216148 kb
Host smart-2f2598f8-2974-4f39-8748-c710b3799232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725686688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.725686688 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1408666044
Short name T867
Test name
Test status
Simulation time 205003485 ps
CPU time 4.28 seconds
Started Aug 18 04:59:11 PM PDT 24
Finished Aug 18 04:59:16 PM PDT 24
Peak memory 216052 kb
Host smart-0d2a4324-777e-43ba-b4aa-f9e4e1197e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408666044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1408
666044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1676502618
Short name T767
Test name
Test status
Simulation time 81751266 ps
CPU time 2.4 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 221156 kb
Host smart-eaa86c35-088b-45ff-99c2-a944547cb7d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676502618 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1676502618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.2626987162
Short name T779
Test name
Test status
Simulation time 19363843 ps
CPU time 1.1 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216000 kb
Host smart-70fe9c22-4f8f-4801-9e14-24e6d7e7f92f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626987162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2626987162 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2075585258
Short name T725
Test name
Test status
Simulation time 36498802 ps
CPU time 0.79 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 215840 kb
Host smart-e866f371-d4d5-4601-a2dd-404bceea9f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075585258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2075585258 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2239069394
Short name T852
Test name
Test status
Simulation time 96354726 ps
CPU time 2.4 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 216096 kb
Host smart-e241ea04-de58-45c0-8832-cf44d12b4a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239069394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2239069394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2162039507
Short name T85
Test name
Test status
Simulation time 114570482 ps
CPU time 1.62 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 216580 kb
Host smart-a19b4683-d69d-4a01-af36-8ae01ad33c02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162039507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.2162039507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3352079314
Short name T151
Test name
Test status
Simulation time 77293368 ps
CPU time 2.05 seconds
Started Aug 18 04:59:11 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 219808 kb
Host smart-e220fbde-8b7a-4a12-9a53-cf6c041ae014
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352079314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.3352079314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.438971535
Short name T864
Test name
Test status
Simulation time 111069377 ps
CPU time 2.57 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 216068 kb
Host smart-df793c68-622c-40db-bec2-18a4c1b6ac0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438971535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.438971535 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.4019228727
Short name T172
Test name
Test status
Simulation time 387864984 ps
CPU time 2.8 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 216084 kb
Host smart-c8d9d5ca-108f-4bd2-9e99-4cb08462205b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019228727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4019
228727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2233038842
Short name T757
Test name
Test status
Simulation time 857902968 ps
CPU time 1.86 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 217032 kb
Host smart-e70d91f6-ad68-4c11-972d-cb1d78808350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233038842 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2233038842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.982861970
Short name T728
Test name
Test status
Simulation time 51635260 ps
CPU time 0.96 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215572 kb
Host smart-984bd19a-381e-4ee5-8af2-c7aabede8e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982861970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.982861970 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.306945877
Short name T841
Test name
Test status
Simulation time 386136944 ps
CPU time 2.53 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 216064 kb
Host smart-8b0ad7e9-376d-4395-a5c7-1269985d82e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306945877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr
_outstanding.306945877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.121645536
Short name T787
Test name
Test status
Simulation time 51790737 ps
CPU time 1.41 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 217436 kb
Host smart-f736c51d-5e23-4c56-b79b-932599ddda5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121645536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_
errors.121645536 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1554948904
Short name T743
Test name
Test status
Simulation time 146913866 ps
CPU time 2.43 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:25 PM PDT 24
Peak memory 218720 kb
Host smart-69ee13be-0cce-451a-a16e-916088162a8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554948904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1554948904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3596885803
Short name T765
Test name
Test status
Simulation time 51859232 ps
CPU time 3.25 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 216068 kb
Host smart-630fdae5-0e11-40fa-bf69-dabaade5ab22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596885803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3596885803 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2710526435
Short name T833
Test name
Test status
Simulation time 152436777 ps
CPU time 1.47 seconds
Started Aug 18 04:59:18 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 219032 kb
Host smart-92d93540-b47e-48c0-8dd9-45b0eba73414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710526435 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2710526435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2207624504
Short name T812
Test name
Test status
Simulation time 84358748 ps
CPU time 0.86 seconds
Started Aug 18 04:59:18 PM PDT 24
Finished Aug 18 04:59:19 PM PDT 24
Peak memory 215732 kb
Host smart-d474cf92-a476-41f8-a083-1c30a0026f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207624504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2207624504 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.2373804898
Short name T741
Test name
Test status
Simulation time 25041659 ps
CPU time 0.79 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 215860 kb
Host smart-3d34f4ec-31f2-4a86-aafd-458e247f4148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373804898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2373804898 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2765116086
Short name T802
Test name
Test status
Simulation time 45574618 ps
CPU time 1.6 seconds
Started Aug 18 04:59:24 PM PDT 24
Finished Aug 18 04:59:26 PM PDT 24
Peak memory 216008 kb
Host smart-5ea957f8-2323-4757-be4b-44390a161cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765116086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.2765116086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3800823038
Short name T129
Test name
Test status
Simulation time 25313742 ps
CPU time 1 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216372 kb
Host smart-745e4f1e-c5db-4760-86cb-8fde1ab02079
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800823038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3800823038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3448698461
Short name T116
Test name
Test status
Simulation time 51577490 ps
CPU time 1.55 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 216324 kb
Host smart-3541601f-0f82-4ae0-bdb7-54f3d01cf764
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448698461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.3448698461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1759576959
Short name T115
Test name
Test status
Simulation time 27635413 ps
CPU time 1.7 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 216164 kb
Host smart-920bb4e2-3f2f-475f-9241-bb6699cea530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759576959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1759576959 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3644787608
Short name T759
Test name
Test status
Simulation time 65262933 ps
CPU time 2.6 seconds
Started Aug 18 04:59:18 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 216060 kb
Host smart-75cf2d9c-21dd-4e46-a37d-f4afeb98954d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644787608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3644
787608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2027757522
Short name T762
Test name
Test status
Simulation time 128325985 ps
CPU time 2.49 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 221980 kb
Host smart-bd26c8b6-9792-4e75-88c5-e289c02979ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027757522 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2027757522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.1185635503
Short name T809
Test name
Test status
Simulation time 131250868 ps
CPU time 1.12 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 216020 kb
Host smart-d5e2ce54-df18-4db0-8c6f-04b76b3e4f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185635503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1185635503 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2225877113
Short name T863
Test name
Test status
Simulation time 13697894 ps
CPU time 0.77 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 215640 kb
Host smart-87b9f4aa-e6c7-44f2-befe-438850a8e5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225877113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2225877113 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3627909200
Short name T830
Test name
Test status
Simulation time 46584341 ps
CPU time 1.54 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 216060 kb
Host smart-c341b33d-264b-490c-a2fe-bcd3db008639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627909200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3627909200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2306872160
Short name T803
Test name
Test status
Simulation time 38684364 ps
CPU time 1.1 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 216424 kb
Host smart-510a938e-ff2d-4050-b590-47ec817db532
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306872160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2306872160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2984961487
Short name T82
Test name
Test status
Simulation time 48387181 ps
CPU time 2.3 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 218500 kb
Host smart-64a08a51-f456-498a-937b-a2acecb9416e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984961487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2984961487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.2639337547
Short name T838
Test name
Test status
Simulation time 413736557 ps
CPU time 2.89 seconds
Started Aug 18 04:59:21 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 216320 kb
Host smart-5d2a0b6b-a99c-4f49-b40d-53757e254a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639337547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2639337547 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.780032354
Short name T856
Test name
Test status
Simulation time 35949753 ps
CPU time 1.91 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 220260 kb
Host smart-f151f20d-97d6-43bd-9287-e29b506124c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780032354 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.780032354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.1748271042
Short name T755
Test name
Test status
Simulation time 16244912 ps
CPU time 1.09 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216092 kb
Host smart-66c06c4e-0c48-4eae-a8f4-89693d04e232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748271042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1748271042 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.4169084068
Short name T827
Test name
Test status
Simulation time 15150293 ps
CPU time 0.82 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215768 kb
Host smart-5efda082-3294-4e6d-948e-896eeb25b5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169084068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.4169084068 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1967405010
Short name T849
Test name
Test status
Simulation time 353895032 ps
CPU time 2.57 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:35 PM PDT 24
Peak memory 215996 kb
Host smart-c5270faa-efe0-48d2-80c0-8951de697e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967405010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.1967405010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2394605007
Short name T786
Test name
Test status
Simulation time 94012427 ps
CPU time 1.03 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216348 kb
Host smart-4c65344d-7305-4a19-a46d-e550df089cea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394605007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2394605007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.657434082
Short name T732
Test name
Test status
Simulation time 767038926 ps
CPU time 1.74 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 219836 kb
Host smart-2b07e365-5e14-4966-af73-35f244fa1c8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657434082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac
_shadow_reg_errors_with_csr_rw.657434082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.488485980
Short name T121
Test name
Test status
Simulation time 267483515 ps
CPU time 2.28 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 216080 kb
Host smart-28645ce2-8796-44ff-9d69-1a8732d72902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488485980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.488485980 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3428625431
Short name T744
Test name
Test status
Simulation time 196885547 ps
CPU time 2.6 seconds
Started Aug 18 04:59:19 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 216080 kb
Host smart-ce463f3b-5989-4407-acf3-4a03a2851ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428625431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3428
625431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2568633001
Short name T769
Test name
Test status
Simulation time 135784007 ps
CPU time 1.56 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:22 PM PDT 24
Peak memory 219608 kb
Host smart-d2865c0e-4ad1-4e15-846b-881660d65a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568633001 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2568633001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.3329606295
Short name T723
Test name
Test status
Simulation time 15088665 ps
CPU time 0.99 seconds
Started Aug 18 04:59:24 PM PDT 24
Finished Aug 18 04:59:25 PM PDT 24
Peak memory 215900 kb
Host smart-37a8a1b7-bca1-4978-9732-6bbb5640601e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329606295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3329606295 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.1571684608
Short name T764
Test name
Test status
Simulation time 21792352 ps
CPU time 0.81 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215776 kb
Host smart-60860131-fddb-48c7-afe3-b7ba3b0f0209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571684608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1571684608 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.330078275
Short name T774
Test name
Test status
Simulation time 688806760 ps
CPU time 2.75 seconds
Started Aug 18 04:59:23 PM PDT 24
Finished Aug 18 04:59:26 PM PDT 24
Peak memory 216060 kb
Host smart-4477870a-8e53-4e1d-81bb-1dbf12ca9183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330078275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr
_outstanding.330078275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.469279737
Short name T806
Test name
Test status
Simulation time 135176179 ps
CPU time 1.4 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 216660 kb
Host smart-ca8a5181-922d-4f48-8aac-4c714f237724
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469279737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.469279737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2896006596
Short name T733
Test name
Test status
Simulation time 30732611 ps
CPU time 1.47 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215936 kb
Host smart-1222fad9-58f8-4e30-a1cd-bc7dfada1f41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896006596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2896006596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.571012865
Short name T857
Test name
Test status
Simulation time 180489102 ps
CPU time 3.16 seconds
Started Aug 18 04:59:23 PM PDT 24
Finished Aug 18 04:59:26 PM PDT 24
Peak memory 216164 kb
Host smart-0e353f05-c054-4773-8608-edfaa4d2e3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571012865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.571012865 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.2442754603
Short name T870
Test name
Test status
Simulation time 294879978 ps
CPU time 4.66 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:25 PM PDT 24
Peak memory 216184 kb
Host smart-6d728a9d-aeac-4238-a8fd-c548a316d110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442754603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2442
754603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1078762659
Short name T798
Test name
Test status
Simulation time 25621863 ps
CPU time 1.54 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 217072 kb
Host smart-372e7acd-5b54-4f73-a7e1-cd57b336e079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078762659 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1078762659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2227717098
Short name T810
Test name
Test status
Simulation time 41901075 ps
CPU time 0.88 seconds
Started Aug 18 04:59:30 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215896 kb
Host smart-f06fc58d-d186-49d4-b843-9da41be839df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227717098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2227717098 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.866402084
Short name T868
Test name
Test status
Simulation time 27452768 ps
CPU time 0.81 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215844 kb
Host smart-86da9413-f562-4fe9-9807-c2cf87daf24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866402084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.866402084 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.206788646
Short name T837
Test name
Test status
Simulation time 148862551 ps
CPU time 2.09 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 216108 kb
Host smart-18b51ad0-13d2-4f9a-b575-9125bfad967d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206788646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.206788646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.71711136
Short name T86
Test name
Test status
Simulation time 77872482 ps
CPU time 1.04 seconds
Started Aug 18 04:59:20 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 215940 kb
Host smart-12b0867b-2398-417c-8bac-d0285a0b56a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71711136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_e
rrors.71711136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2016972258
Short name T851
Test name
Test status
Simulation time 226062992 ps
CPU time 1.81 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 218916 kb
Host smart-09fb2cda-1809-48f8-83fc-2360a7be0de6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016972258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.2016972258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.1224668934
Short name T166
Test name
Test status
Simulation time 1574422387 ps
CPU time 2.72 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:35 PM PDT 24
Peak memory 216120 kb
Host smart-a833161c-3cef-4810-9a6b-6169d8a8d994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224668934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1224668934 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.155937782
Short name T818
Test name
Test status
Simulation time 100017575 ps
CPU time 2.71 seconds
Started Aug 18 04:59:30 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215988 kb
Host smart-4a635e67-f934-4bba-814e-c3ecfd28989e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155937782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.15593
7782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.162914354
Short name T839
Test name
Test status
Simulation time 3824312303 ps
CPU time 10.03 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216072 kb
Host smart-c60c6515-e4db-47fa-8e37-43396cfd1f3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162914354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.16291435
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1198231356
Short name T746
Test name
Test status
Simulation time 577896811 ps
CPU time 16.64 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216068 kb
Host smart-2e3e7dd4-916e-43d1-b576-63d07766a7be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198231356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1198231
356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2356640857
Short name T735
Test name
Test status
Simulation time 57798487 ps
CPU time 1.02 seconds
Started Aug 18 04:58:59 PM PDT 24
Finished Aug 18 04:59:00 PM PDT 24
Peak memory 216060 kb
Host smart-66080147-82f5-414d-95a1-1cc1a947114b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356640857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2356640
857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.399564561
Short name T783
Test name
Test status
Simulation time 49934920 ps
CPU time 1.63 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 217224 kb
Host smart-e743926b-89f9-4245-9a2d-dd35a5ee5d32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399564561 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.399564561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.270769418
Short name T800
Test name
Test status
Simulation time 23535972 ps
CPU time 0.92 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 215904 kb
Host smart-d78b7325-2c73-4d66-a331-491f501187fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270769418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.270769418 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1085496387
Short name T715
Test name
Test status
Simulation time 13613135 ps
CPU time 0.75 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:01 PM PDT 24
Peak memory 215852 kb
Host smart-f9816302-7968-44a8-baac-7734ed004066
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085496387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1085496387
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1330956431
Short name T861
Test name
Test status
Simulation time 43172058 ps
CPU time 1.43 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 216124 kb
Host smart-06698c40-9cc3-47b8-af22-8660b0d4821d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330956431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.1330956431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3264110297
Short name T745
Test name
Test status
Simulation time 70779598 ps
CPU time 1.1 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 216332 kb
Host smart-d2119bc0-7846-4b99-a35d-4bbd6d1d2b26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264110297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3264110297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.2257305329
Short name T778
Test name
Test status
Simulation time 25848173 ps
CPU time 1.68 seconds
Started Aug 18 04:59:04 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216136 kb
Host smart-11919828-a14f-408e-8775-973ab7c7a339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257305329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2257305329 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1987356689
Short name T828
Test name
Test status
Simulation time 223702858 ps
CPU time 2.92 seconds
Started Aug 18 04:59:04 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 215908 kb
Host smart-b621c7fd-6456-4b4e-924a-958ac6f80c21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987356689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.19873
56689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.4274374026
Short name T158
Test name
Test status
Simulation time 46698684 ps
CPU time 0.77 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215832 kb
Host smart-ecd005c5-593d-47a2-86b9-c9cf089db531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274374026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4274374026 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.3217211650
Short name T846
Test name
Test status
Simulation time 43950870 ps
CPU time 0.75 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215800 kb
Host smart-a955f468-0edb-48f4-8aa2-09125870b2e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217211650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3217211650 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.3891805662
Short name T847
Test name
Test status
Simulation time 132615497 ps
CPU time 0.82 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215860 kb
Host smart-89ed4957-1f46-470e-bc2d-801dbdc2905d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891805662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3891805662 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.43179857
Short name T793
Test name
Test status
Simulation time 14465561 ps
CPU time 0.77 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215872 kb
Host smart-22c0375c-ebff-4251-a4ed-25ee62f9ad3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43179857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.43179857 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.485354920
Short name T731
Test name
Test status
Simulation time 16018423 ps
CPU time 0.85 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215764 kb
Host smart-f955430a-fd08-4e67-8dca-74d9bbcbbd5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485354920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.485354920 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.4103600718
Short name T842
Test name
Test status
Simulation time 16475040 ps
CPU time 0.81 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215708 kb
Host smart-eb37f021-3c20-4104-99de-04aa4a487a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103600718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.4103600718 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.3382954476
Short name T795
Test name
Test status
Simulation time 43978690 ps
CPU time 0.77 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 216016 kb
Host smart-9b7cecd0-04ac-451f-aaf5-e9a246bea176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382954476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.3382954476 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.1163533582
Short name T821
Test name
Test status
Simulation time 12604759 ps
CPU time 0.78 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 215780 kb
Host smart-a2fcd301-58d6-4532-b525-2b4d14b1d220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163533582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1163533582 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1653113253
Short name T780
Test name
Test status
Simulation time 22758279 ps
CPU time 0.84 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215828 kb
Host smart-43b7abc7-1177-4a7d-89e8-eb11f6dcc97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653113253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1653113253 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.3945838593
Short name T727
Test name
Test status
Simulation time 13091622 ps
CPU time 0.79 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 215740 kb
Host smart-405644ff-510c-447f-a037-64cdba30a527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945838593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3945838593 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1170749078
Short name T748
Test name
Test status
Simulation time 277868227 ps
CPU time 4.08 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 216000 kb
Host smart-b3425936-a887-42c8-a7ab-185daf9afffc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170749078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1170749
078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.843724291
Short name T815
Test name
Test status
Simulation time 3025309841 ps
CPU time 10.06 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:20 PM PDT 24
Peak memory 216128 kb
Host smart-72887af5-b071-463e-b1a3-3912fb5fb47b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843724291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.84372429
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.55598015
Short name T784
Test name
Test status
Simulation time 22861594 ps
CPU time 0.98 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 215820 kb
Host smart-17bd5ed2-efb1-4830-8517-6a6cc95e6098
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55598015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.55598015
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.825273947
Short name T865
Test name
Test status
Simulation time 237124971 ps
CPU time 2.18 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 221004 kb
Host smart-e82d7da1-9076-4e14-adca-1192ee76ec3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825273947 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.825273947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2606047653
Short name T736
Test name
Test status
Simulation time 20854824 ps
CPU time 1 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 215824 kb
Host smart-071b95b3-ac69-4aba-a820-606a7c9bb6cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606047653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2606047653 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1595109395
Short name T869
Test name
Test status
Simulation time 14284024 ps
CPU time 0.81 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 215696 kb
Host smart-33cc96e1-3d70-4268-9e79-bf782cddbc32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595109395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1595109395 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4214755180
Short name T146
Test name
Test status
Simulation time 38338265 ps
CPU time 1.57 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 215940 kb
Host smart-f7f18c39-4f01-4987-ad9e-1be06487ce02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214755180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.4214755180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2920846758
Short name T749
Test name
Test status
Simulation time 25496710 ps
CPU time 0.75 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 215628 kb
Host smart-658745ce-8310-49ad-b930-b092faf9da1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920846758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2920846758
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.12460853
Short name T155
Test name
Test status
Simulation time 269105279 ps
CPU time 1.73 seconds
Started Aug 18 04:59:07 PM PDT 24
Finished Aug 18 04:59:09 PM PDT 24
Peak memory 216100 kb
Host smart-5486653f-f201-4bb6-9cf2-9f79dca2dabc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12460853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_o
utstanding.12460853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2231112996
Short name T93
Test name
Test status
Simulation time 30709951 ps
CPU time 1.29 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 216468 kb
Host smart-922bbdf2-85f0-4e1a-bde3-c898f1158b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231112996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2231112996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1669414164
Short name T843
Test name
Test status
Simulation time 30095317 ps
CPU time 1.59 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216176 kb
Host smart-26ccae09-976e-477f-918c-7b7567873f7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669414164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.1669414164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1907692637
Short name T753
Test name
Test status
Simulation time 81015577 ps
CPU time 2.26 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 216180 kb
Host smart-eb3f87b5-b2d6-4bfd-8943-192bf580b9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907692637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1907692637 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3507434790
Short name T173
Test name
Test status
Simulation time 118885059 ps
CPU time 2.41 seconds
Started Aug 18 04:59:07 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 216156 kb
Host smart-4281cca4-40a6-472c-a9f6-13ece9ca29de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507434790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.35074
34790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3001290255
Short name T813
Test name
Test status
Simulation time 39972387 ps
CPU time 0.82 seconds
Started Aug 18 04:59:30 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215736 kb
Host smart-f21fd59a-771d-4592-9911-b22a7430f9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001290255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3001290255 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.190599955
Short name T768
Test name
Test status
Simulation time 24856862 ps
CPU time 0.77 seconds
Started Aug 18 04:59:30 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215740 kb
Host smart-04c59f8d-18ea-460c-a873-e287688e91a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190599955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.190599955 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.4211680459
Short name T823
Test name
Test status
Simulation time 39244184 ps
CPU time 0.76 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215824 kb
Host smart-29dda0f9-6808-428e-b53b-56cffbde0384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211680459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.4211680459 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.3864722107
Short name T804
Test name
Test status
Simulation time 21946087 ps
CPU time 0.81 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215628 kb
Host smart-7328c496-eb52-4702-96a1-a66868dda785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864722107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3864722107 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.4096451748
Short name T724
Test name
Test status
Simulation time 15170374 ps
CPU time 0.8 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215712 kb
Host smart-bdbacdfe-df63-4b32-859a-2037d4236a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096451748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.4096451748 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.379786281
Short name T854
Test name
Test status
Simulation time 24834189 ps
CPU time 0.8 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 215780 kb
Host smart-4cfaba70-26f7-4806-918a-26310d6bbf7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379786281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.379786281 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2774972635
Short name T719
Test name
Test status
Simulation time 14883702 ps
CPU time 0.79 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215840 kb
Host smart-e7523042-f1d5-4721-be03-9cba6334bbcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774972635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2774972635 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1132625879
Short name T817
Test name
Test status
Simulation time 16898440 ps
CPU time 0.84 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215712 kb
Host smart-39776f9e-1a99-4a58-afa7-414ed4040f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132625879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1132625879 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2266888344
Short name T160
Test name
Test status
Simulation time 25253310 ps
CPU time 0.8 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215660 kb
Host smart-7c8b26d3-7aa4-4478-a41c-a058e45bad6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266888344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2266888344 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1639220060
Short name T165
Test name
Test status
Simulation time 40018843 ps
CPU time 0.79 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 215680 kb
Host smart-fb559a52-724c-4bce-bbc5-95f7424141ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639220060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1639220060 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.2995839949
Short name T729
Test name
Test status
Simulation time 1724119628 ps
CPU time 9.06 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:18 PM PDT 24
Peak memory 216060 kb
Host smart-ef35b311-0ca0-4942-b518-1833c2505db1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995839949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.2995839
949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.2885851543
Short name T738
Test name
Test status
Simulation time 991444018 ps
CPU time 9.69 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:19 PM PDT 24
Peak memory 216068 kb
Host smart-b5599713-4afa-49fa-a8e8-0565dd9af284
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885851543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2885851
543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1386094044
Short name T782
Test name
Test status
Simulation time 22661109 ps
CPU time 0.98 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 215808 kb
Host smart-ff0c01db-6d2e-4667-8aa5-467b6ddc2068
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386094044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1386094
044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.125064821
Short name T792
Test name
Test status
Simulation time 161173095 ps
CPU time 2.33 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 221020 kb
Host smart-3c927061-05b8-47ab-9108-a1cfc0b1f111
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125064821 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.125064821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1225797441
Short name T816
Test name
Test status
Simulation time 194450087 ps
CPU time 1.18 seconds
Started Aug 18 04:59:05 PM PDT 24
Finished Aug 18 04:59:06 PM PDT 24
Peak memory 216084 kb
Host smart-187b634d-e53a-4f16-95e9-13a6da31b1f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225797441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1225797441 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1957790474
Short name T124
Test name
Test status
Simulation time 45026255 ps
CPU time 0.78 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 215772 kb
Host smart-d5500077-461e-4876-b81c-251ba220e295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957790474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1957790474 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3736813304
Short name T862
Test name
Test status
Simulation time 39755225 ps
CPU time 1.61 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 215908 kb
Host smart-9024404f-43eb-4dae-8f5e-8ba3646e7c41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736813304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3736813304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.63648325
Short name T808
Test name
Test status
Simulation time 25948680 ps
CPU time 0.73 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:01 PM PDT 24
Peak memory 215856 kb
Host smart-10ad719d-98d6-44fc-a127-df4c2b916789
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63648325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.63648325 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1515136555
Short name T858
Test name
Test status
Simulation time 42844642 ps
CPU time 2.2 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 216104 kb
Host smart-5205cbc4-cb14-47c5-a6a5-e523867b7ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515136555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1515136555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.226232962
Short name T88
Test name
Test status
Simulation time 25217736 ps
CPU time 0.99 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216044 kb
Host smart-b7afa08e-a301-4b26-83aa-9b1bced0a6de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226232962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.226232962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1862255664
Short name T89
Test name
Test status
Simulation time 118270644 ps
CPU time 2.91 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 218760 kb
Host smart-a9732842-cb30-4062-bc04-fc1c5246bfa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862255664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.1862255664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.2209689248
Short name T807
Test name
Test status
Simulation time 44150746 ps
CPU time 2.48 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 216240 kb
Host smart-2429df10-e939-46c2-baaa-7bca8d312491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209689248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2209689248 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.1904312452
Short name T781
Test name
Test status
Simulation time 105942623 ps
CPU time 2.49 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 216004 kb
Host smart-f1046093-3455-40ba-8261-c95cd6fffe71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904312452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.19043
12452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.3200085960
Short name T819
Test name
Test status
Simulation time 188636768 ps
CPU time 0.9 seconds
Started Aug 18 04:59:30 PM PDT 24
Finished Aug 18 04:59:31 PM PDT 24
Peak memory 215872 kb
Host smart-db8d6dbb-f5b7-449e-ab6f-64843a4bdddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200085960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3200085960 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2375511252
Short name T829
Test name
Test status
Simulation time 40630144 ps
CPU time 0.78 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215656 kb
Host smart-9aa34c6d-6974-472d-9d2d-da4134beea85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375511252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2375511252 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.2473814201
Short name T123
Test name
Test status
Simulation time 18103967 ps
CPU time 0.78 seconds
Started Aug 18 04:59:31 PM PDT 24
Finished Aug 18 04:59:32 PM PDT 24
Peak memory 215684 kb
Host smart-55be1e70-e4fb-4dd0-8d22-ba45e18b03bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473814201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2473814201 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2765883763
Short name T726
Test name
Test status
Simulation time 49078327 ps
CPU time 0.73 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 215860 kb
Host smart-038ef69d-cd5f-4fa7-8189-d60f88c8189d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765883763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2765883763 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.4164656432
Short name T840
Test name
Test status
Simulation time 40174955 ps
CPU time 0.83 seconds
Started Aug 18 04:59:34 PM PDT 24
Finished Aug 18 04:59:35 PM PDT 24
Peak memory 215848 kb
Host smart-68983710-33dc-430c-ae20-c800d008e408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164656432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.4164656432 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.255166166
Short name T771
Test name
Test status
Simulation time 16839308 ps
CPU time 0.76 seconds
Started Aug 18 04:59:33 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215852 kb
Host smart-5ae155ac-5ab5-4509-b1d5-af3380d385c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255166166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.255166166 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.3933598672
Short name T122
Test name
Test status
Simulation time 50457276 ps
CPU time 0.83 seconds
Started Aug 18 04:59:32 PM PDT 24
Finished Aug 18 04:59:33 PM PDT 24
Peak memory 215800 kb
Host smart-32488b5d-5a97-4aac-918c-0115ae527217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933598672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3933598672 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.82512552
Short name T761
Test name
Test status
Simulation time 38518365 ps
CPU time 0.78 seconds
Started Aug 18 04:59:40 PM PDT 24
Finished Aug 18 04:59:41 PM PDT 24
Peak memory 215676 kb
Host smart-00c272bb-d176-418c-8851-16230844810a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82512552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.82512552 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.1024444700
Short name T722
Test name
Test status
Simulation time 14221307 ps
CPU time 0.78 seconds
Started Aug 18 04:59:43 PM PDT 24
Finished Aug 18 04:59:44 PM PDT 24
Peak memory 215840 kb
Host smart-9b2fd968-a429-42d6-b86f-da1a722253ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024444700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1024444700 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2434899239
Short name T721
Test name
Test status
Simulation time 23288439 ps
CPU time 0.79 seconds
Started Aug 18 04:59:39 PM PDT 24
Finished Aug 18 04:59:40 PM PDT 24
Peak memory 215772 kb
Host smart-1b1d7b89-88ed-46a1-a37c-1b09fc8516aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434899239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2434899239 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.72275353
Short name T130
Test name
Test status
Simulation time 169552290 ps
CPU time 1.55 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 218924 kb
Host smart-7f03b72b-f576-4ce4-932d-581b36e23032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72275353 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.72275353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.2672421334
Short name T720
Test name
Test status
Simulation time 101813949 ps
CPU time 1.18 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 216160 kb
Host smart-84344b04-6d0f-4c2b-8f4f-b4f5c4050de6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672421334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2672421334 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.2494509509
Short name T855
Test name
Test status
Simulation time 40912142 ps
CPU time 0.76 seconds
Started Aug 18 04:59:11 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 215780 kb
Host smart-fabd67ff-4542-49fb-a3e8-ac4265b3d0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494509509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2494509509 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2379521105
Short name T153
Test name
Test status
Simulation time 203362807 ps
CPU time 1.58 seconds
Started Aug 18 04:59:05 PM PDT 24
Finished Aug 18 04:59:06 PM PDT 24
Peak memory 216096 kb
Host smart-e6b00423-1fae-469d-963b-7751ec36a995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379521105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.2379521105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1995490248
Short name T848
Test name
Test status
Simulation time 143029445 ps
CPU time 1.24 seconds
Started Aug 18 04:59:00 PM PDT 24
Finished Aug 18 04:59:01 PM PDT 24
Peak memory 216336 kb
Host smart-c04f7ec2-8f79-4e00-b55f-54c72d337cbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995490248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1995490248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.683849104
Short name T754
Test name
Test status
Simulation time 116730793 ps
CPU time 3.02 seconds
Started Aug 18 04:59:01 PM PDT 24
Finished Aug 18 04:59:04 PM PDT 24
Peak memory 216156 kb
Host smart-3d03b7af-92e1-455a-868a-4ddfde5ba6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683849104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.683849104 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2141781565
Short name T760
Test name
Test status
Simulation time 56981198 ps
CPU time 2.42 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 216144 kb
Host smart-cc4fec5f-cf57-4c72-af6c-0b9a351e5e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141781565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.21417
81565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3739154441
Short name T824
Test name
Test status
Simulation time 52007788 ps
CPU time 2.28 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:06 PM PDT 24
Peak memory 221244 kb
Host smart-6ce0dc03-fc61-4c14-9bc8-1dd59d0d6d0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739154441 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3739154441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.3236770478
Short name T794
Test name
Test status
Simulation time 42089326 ps
CPU time 0.88 seconds
Started Aug 18 04:59:11 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 215808 kb
Host smart-c5e8b654-a304-445d-8682-144dd0d7ba72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236770478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3236770478 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2933119739
Short name T159
Test name
Test status
Simulation time 247041084 ps
CPU time 0.8 seconds
Started Aug 18 04:59:11 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 215740 kb
Host smart-ee12e463-7e87-4efd-9607-774ac79d1f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933119739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2933119739 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1224097453
Short name T790
Test name
Test status
Simulation time 79539683 ps
CPU time 1.45 seconds
Started Aug 18 04:59:08 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 216080 kb
Host smart-26718bfe-1ba0-41a7-a932-f338bcd82727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224097453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1224097453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2950006711
Short name T814
Test name
Test status
Simulation time 30235509 ps
CPU time 0.96 seconds
Started Aug 18 04:59:07 PM PDT 24
Finished Aug 18 04:59:08 PM PDT 24
Peak memory 216228 kb
Host smart-50803d3f-37c2-498b-9338-8aa8ea23b907
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950006711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.2950006711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2572424612
Short name T834
Test name
Test status
Simulation time 91997549 ps
CPU time 1.58 seconds
Started Aug 18 04:59:08 PM PDT 24
Finished Aug 18 04:59:09 PM PDT 24
Peak memory 218052 kb
Host smart-9edfc45a-f944-4188-92c0-33a081f02a9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572424612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.2572424612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.1390019233
Short name T127
Test name
Test status
Simulation time 58197247 ps
CPU time 3.49 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216092 kb
Host smart-dae341bd-3cdb-4da2-87dc-6a60fd69570c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390019233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1390019233 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4161425821
Short name T120
Test name
Test status
Simulation time 181093509 ps
CPU time 2.77 seconds
Started Aug 18 04:59:04 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 216056 kb
Host smart-8ae01138-e644-4068-b5d9-b09b03efd90c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161425821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.41614
25821 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2346375156
Short name T825
Test name
Test status
Simulation time 95964955 ps
CPU time 1.65 seconds
Started Aug 18 04:59:13 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 219100 kb
Host smart-f8ab49b6-45b7-48c7-ab91-a26618f9fc46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346375156 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2346375156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.4188685080
Short name T859
Test name
Test status
Simulation time 241547439 ps
CPU time 1 seconds
Started Aug 18 04:59:22 PM PDT 24
Finished Aug 18 04:59:23 PM PDT 24
Peak memory 215816 kb
Host smart-f2eaae28-8aec-40d8-92dd-98559bc65bee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188685080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.4188685080 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3987547724
Short name T826
Test name
Test status
Simulation time 16711165 ps
CPU time 0.88 seconds
Started Aug 18 04:59:15 PM PDT 24
Finished Aug 18 04:59:16 PM PDT 24
Peak memory 215652 kb
Host smart-bbd70da3-3d79-4814-a999-63941e3e2c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987547724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3987547724 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3515399631
Short name T747
Test name
Test status
Simulation time 69469417 ps
CPU time 1.73 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 215984 kb
Host smart-7852c020-709e-4726-9ca1-3638129af748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515399631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3515399631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3752174891
Short name T717
Test name
Test status
Simulation time 67548720 ps
CPU time 1.01 seconds
Started Aug 18 04:59:02 PM PDT 24
Finished Aug 18 04:59:03 PM PDT 24
Peak memory 216136 kb
Host smart-56da89f5-1a14-47d3-aed8-915e720c0071
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752174891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.3752174891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3559942862
Short name T866
Test name
Test status
Simulation time 228161924 ps
CPU time 1.77 seconds
Started Aug 18 04:59:03 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 216140 kb
Host smart-f6279d2a-5e92-4625-aa7b-1cd7f2360141
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559942862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3559942862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.1463787210
Short name T775
Test name
Test status
Simulation time 131390108 ps
CPU time 3.2 seconds
Started Aug 18 04:59:08 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 216144 kb
Host smart-1200dd8d-6589-49f5-af60-cbedf55c5587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463787210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1463787210 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1012515667
Short name T177
Test name
Test status
Simulation time 795097874 ps
CPU time 4.03 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216160 kb
Host smart-72e6774e-a624-4b21-9c45-5da2cb940d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012515667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.10125
15667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.201188060
Short name T763
Test name
Test status
Simulation time 37715457 ps
CPU time 1.56 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 217280 kb
Host smart-43c0e183-8659-4751-a9f2-9da49b9768d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201188060 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.201188060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.236993240
Short name T785
Test name
Test status
Simulation time 91305888 ps
CPU time 1.13 seconds
Started Aug 18 04:59:10 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 215956 kb
Host smart-9820005e-353e-43e8-9195-7ac50b855d8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236993240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.236993240 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.1960808062
Short name T766
Test name
Test status
Simulation time 14536567 ps
CPU time 0.79 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 215776 kb
Host smart-d3d6a834-25c9-4684-b946-941cb5af888c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960808062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1960808062 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2588887025
Short name T154
Test name
Test status
Simulation time 397587610 ps
CPU time 2.33 seconds
Started Aug 18 04:59:14 PM PDT 24
Finished Aug 18 04:59:16 PM PDT 24
Peak memory 216024 kb
Host smart-1384bc58-674d-4089-9f3a-bb164b38b2fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588887025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.2588887025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1874314035
Short name T758
Test name
Test status
Simulation time 160576745 ps
CPU time 1.16 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:13 PM PDT 24
Peak memory 216048 kb
Host smart-9405aa2c-2627-468c-ae19-939129c750fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874314035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.1874314035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1918138532
Short name T820
Test name
Test status
Simulation time 77732310 ps
CPU time 2.3 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 219008 kb
Host smart-d03c5b7d-16c5-4ef7-b463-bf2ee3d801e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918138532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.1918138532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.1469510797
Short name T117
Test name
Test status
Simulation time 129576523 ps
CPU time 3.36 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 216160 kb
Host smart-782c435b-c0d5-4bcd-bedb-42182d02ca26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469510797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1469510797 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.814104820
Short name T175
Test name
Test status
Simulation time 1674096294 ps
CPU time 4.37 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216044 kb
Host smart-b45476f3-85c2-4889-af0f-2531c33cb637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814104820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.814104
820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4290731705
Short name T161
Test name
Test status
Simulation time 331676500 ps
CPU time 2.36 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 221048 kb
Host smart-f643e79d-8e13-489a-ad1d-f62daafc377c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290731705 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.4290731705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.1800123418
Short name T773
Test name
Test status
Simulation time 31195632 ps
CPU time 1.15 seconds
Started Aug 18 04:59:13 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 216052 kb
Host smart-cbba2368-12e0-4e78-ae85-cf743fb24560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800123418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1800123418 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3490143567
Short name T756
Test name
Test status
Simulation time 40476514 ps
CPU time 0.8 seconds
Started Aug 18 04:59:09 PM PDT 24
Finished Aug 18 04:59:10 PM PDT 24
Peak memory 215748 kb
Host smart-dcbd55e5-2dde-4f39-99d4-8893acc40c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490143567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3490143567 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.1099620881
Short name T740
Test name
Test status
Simulation time 52245361 ps
CPU time 1.77 seconds
Started Aug 18 04:59:15 PM PDT 24
Finished Aug 18 04:59:16 PM PDT 24
Peak memory 215920 kb
Host smart-ce312e7a-60db-4e0a-a4a5-84be5ebe7843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099620881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.1099620881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.862082949
Short name T152
Test name
Test status
Simulation time 113712261 ps
CPU time 1.12 seconds
Started Aug 18 04:59:13 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 216188 kb
Host smart-802f7840-ff68-4180-aff8-bc1ca99e177e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862082949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_e
rrors.862082949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.1141956884
Short name T796
Test name
Test status
Simulation time 259495049 ps
CPU time 3.24 seconds
Started Aug 18 04:59:12 PM PDT 24
Finished Aug 18 04:59:15 PM PDT 24
Peak memory 216232 kb
Host smart-60e34a31-3892-4d39-a7b9-03f368083d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141956884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1141956884 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/default/0.kmac_alert_test.3210767050
Short name T702
Test name
Test status
Simulation time 19777779 ps
CPU time 0.84 seconds
Started Aug 18 05:03:39 PM PDT 24
Finished Aug 18 05:03:40 PM PDT 24
Peak memory 218292 kb
Host smart-99158251-ee65-4d04-afce-e82e4b8d980d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210767050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3210767050 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.236613562
Short name T180
Test name
Test status
Simulation time 25349883275 ps
CPU time 304.37 seconds
Started Aug 18 05:03:29 PM PDT 24
Finished Aug 18 05:08:34 PM PDT 24
Peak memory 454260 kb
Host smart-3e2eeb03-a4e0-4107-b183-a650fb08933e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236613562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.236613562 +enable_masking=1
+sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_burst_write.2073688993
Short name T642
Test name
Test status
Simulation time 892526994 ps
CPU time 89.11 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:05:07 PM PDT 24
Peak memory 226504 kb
Host smart-b218545e-58c7-4eb1-9293-6b3a1c88f764
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073688993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2073688993
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.544040319
Short name T492
Test name
Test status
Simulation time 33415840 ps
CPU time 0.93 seconds
Started Aug 18 05:03:39 PM PDT 24
Finished Aug 18 05:03:40 PM PDT 24
Peak memory 217976 kb
Host smart-53458a93-fb6f-4b6f-a4b7-b24e453da5de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544040319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.544040319 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.1909708721
Short name T529
Test name
Test status
Simulation time 9002448609 ps
CPU time 50.56 seconds
Started Aug 18 05:03:28 PM PDT 24
Finished Aug 18 05:04:19 PM PDT 24
Peak memory 226744 kb
Host smart-5dcd4726-3e13-41d9-bc94-ce53ab516061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909708721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1909708721 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.3720142990
Short name T133
Test name
Test status
Simulation time 33254463101 ps
CPU time 323 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 444580 kb
Host smart-74d9dd10-5aa8-400b-9587-0e41f9d42002
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720142990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.37
20142990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2192375487
Short name T710
Test name
Test status
Simulation time 5435244492 ps
CPU time 450.34 seconds
Started Aug 18 05:03:33 PM PDT 24
Finished Aug 18 05:11:03 PM PDT 24
Peak memory 365160 kb
Host smart-c568d951-089f-4655-b7ee-e7e893eba509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192375487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2192375487 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.722540017
Short name T351
Test name
Test status
Simulation time 2222467669 ps
CPU time 5.45 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:03:41 PM PDT 24
Peak memory 226508 kb
Host smart-81f7179d-6454-4f2b-ac4e-71e3cc40460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722540017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.722540017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.3456019950
Short name T511
Test name
Test status
Simulation time 36682636 ps
CPU time 1.29 seconds
Started Aug 18 05:03:29 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 226640 kb
Host smart-c0079da3-c9b8-4114-9efc-7fb670d45b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456019950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3456019950 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.3506882945
Short name T318
Test name
Test status
Simulation time 225461251005 ps
CPU time 4536.61 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 06:19:07 PM PDT 24
Peak memory 3338808 kb
Host smart-cbe64eab-3819-48f6-b23f-7224cee9454c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506882945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.3506882945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.1305200019
Short name T18
Test name
Test status
Simulation time 84369400915 ps
CPU time 403.81 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 348528 kb
Host smart-22bde183-6dbb-413d-98dd-fa5402f9592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305200019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1305200019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2076273850
Short name T27
Test name
Test status
Simulation time 5227558414 ps
CPU time 41.5 seconds
Started Aug 18 05:03:38 PM PDT 24
Finished Aug 18 05:04:20 PM PDT 24
Peak memory 256576 kb
Host smart-2788cb54-adf3-4f95-99ac-1b5d262e73ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076273850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2076273850 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.966618818
Short name T424
Test name
Test status
Simulation time 1670989024 ps
CPU time 41.11 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:04:18 PM PDT 24
Peak memory 257444 kb
Host smart-18e9df54-f0fc-4247-901a-49a4888b0ab0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966618818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.966618818 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.1994932632
Short name T254
Test name
Test status
Simulation time 556983037 ps
CPU time 9.41 seconds
Started Aug 18 05:03:30 PM PDT 24
Finished Aug 18 05:03:40 PM PDT 24
Peak memory 221752 kb
Host smart-70571340-3343-447a-b93e-d9434ee625c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994932632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1994932632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3217301491
Short name T44
Test name
Test status
Simulation time 198069851518 ps
CPU time 1832.96 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:34:10 PM PDT 24
Peak memory 1261484 kb
Host smart-b0139670-9a6b-459f-8de9-b553be6eee5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3217301491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3217301491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.148932297
Short name T456
Test name
Test status
Simulation time 144896608 ps
CPU time 3.2 seconds
Started Aug 18 05:03:28 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 219492 kb
Host smart-05c9894f-5695-4a56-8844-1cb4db56090b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148932297 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.kmac_test_vectors_kmac.148932297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1161483187
Short name T647
Test name
Test status
Simulation time 321458199 ps
CPU time 3.37 seconds
Started Aug 18 05:03:32 PM PDT 24
Finished Aug 18 05:03:35 PM PDT 24
Peak memory 219692 kb
Host smart-cfd032cd-e923-43ef-8ea3-659f0ed3f3cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161483187 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1161483187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.4256254362
Short name T528
Test name
Test status
Simulation time 363874518662 ps
CPU time 3430.97 seconds
Started Aug 18 05:03:33 PM PDT 24
Finished Aug 18 06:00:44 PM PDT 24
Peak memory 3171728 kb
Host smart-440f1a0b-0bab-437e-8e00-760f2e3dc925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4256254362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.4256254362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1595723004
Short name T181
Test name
Test status
Simulation time 1922819028 ps
CPU time 41.47 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:04:17 PM PDT 24
Peak memory 248116 kb
Host smart-9a7f211c-900f-4f0f-a0fc-cd478cf4d6e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1595723004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1595723004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.2293780210
Short name T404
Test name
Test status
Simulation time 1648777214 ps
CPU time 29.96 seconds
Started Aug 18 05:03:31 PM PDT 24
Finished Aug 18 05:04:01 PM PDT 24
Peak memory 233048 kb
Host smart-f71238b4-f50a-4a12-ae7f-cf98f96b04cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2293780210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2293780210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.294693561
Short name T390
Test name
Test status
Simulation time 35797619950 ps
CPU time 1581.25 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:29:59 PM PDT 24
Peak memory 1684248 kb
Host smart-0410f53a-a4fe-4ba4-bf87-9acfd6e0c2b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=294693561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.294693561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.2508226341
Short name T605
Test name
Test status
Simulation time 111809376189 ps
CPU time 4691.58 seconds
Started Aug 18 05:03:32 PM PDT 24
Finished Aug 18 06:21:45 PM PDT 24
Peak memory 3715364 kb
Host smart-e950d17c-ce55-4acc-b7e7-a3513c3944d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2508226341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2508226341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.877654533
Short name T428
Test name
Test status
Simulation time 2698570531 ps
CPU time 129.71 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:05:46 PM PDT 24
Peak memory 257768 kb
Host smart-18960f5a-05cb-420b-8aeb-6747a555022a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=877654533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.877654533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_app.1518845531
Short name T556
Test name
Test status
Simulation time 17804574211 ps
CPU time 115.36 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:05:32 PM PDT 24
Peak memory 306800 kb
Host smart-62d056c6-469b-4d46-ad71-822278d75517
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518845531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1518845531 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1808710538
Short name T533
Test name
Test status
Simulation time 8853063867 ps
CPU time 208.39 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:07:05 PM PDT 24
Peak memory 360340 kb
Host smart-75361cfa-be94-4af8-b39a-3fd263c6ee2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808710538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_par
tial_data.1808710538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.61979818
Short name T587
Test name
Test status
Simulation time 14858268395 ps
CPU time 670.6 seconds
Started Aug 18 05:03:36 PM PDT 24
Finished Aug 18 05:14:47 PM PDT 24
Peak memory 244996 kb
Host smart-77c55d68-4b7d-4992-9f21-e16aff8bff9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61979818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.61979818 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3225586584
Short name T431
Test name
Test status
Simulation time 3531373295 ps
CPU time 25.95 seconds
Started Aug 18 05:03:47 PM PDT 24
Finished Aug 18 05:04:13 PM PDT 24
Peak memory 226072 kb
Host smart-a6aa767d-3184-423b-ac4f-07003153381f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3225586584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3225586584 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2510207720
Short name T458
Test name
Test status
Simulation time 35025477 ps
CPU time 1.27 seconds
Started Aug 18 05:03:55 PM PDT 24
Finished Aug 18 05:03:57 PM PDT 24
Peak memory 221860 kb
Host smart-afd81421-7266-447f-8045-322b797f556d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2510207720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2510207720 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.323187863
Short name T463
Test name
Test status
Simulation time 6862093352 ps
CPU time 73.72 seconds
Started Aug 18 05:03:54 PM PDT 24
Finished Aug 18 05:05:08 PM PDT 24
Peak memory 224496 kb
Host smart-8768e488-daa3-4e2b-acc3-36001d4b1307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323187863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.323187863 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.241896770
Short name T705
Test name
Test status
Simulation time 3142550940 ps
CPU time 7.87 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:03:45 PM PDT 24
Peak memory 226772 kb
Host smart-6c99e1fb-5bdc-47a8-a4a9-238796af306d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241896770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.241
896770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.3216537390
Short name T643
Test name
Test status
Simulation time 11427167001 ps
CPU time 272.07 seconds
Started Aug 18 05:03:50 PM PDT 24
Finished Aug 18 05:08:23 PM PDT 24
Peak memory 314808 kb
Host smart-e3d55244-b054-49f7-8c20-cf29e68df475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216537390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3216537390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.920507860
Short name T216
Test name
Test status
Simulation time 59833658 ps
CPU time 1.3 seconds
Started Aug 18 05:03:56 PM PDT 24
Finished Aug 18 05:03:57 PM PDT 24
Peak memory 224940 kb
Host smart-ee6f7d02-e297-4c66-bc94-b0dbbb842166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920507860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.920507860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_mubi.3370011468
Short name T493
Test name
Test status
Simulation time 2405773692 ps
CPU time 53.57 seconds
Started Aug 18 05:03:51 PM PDT 24
Finished Aug 18 05:04:45 PM PDT 24
Peak memory 265636 kb
Host smart-4cd955b9-7ed0-48d1-bcb4-78a171135916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370011468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3370011468 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.3324601915
Short name T683
Test name
Test status
Simulation time 3180649205 ps
CPU time 129.3 seconds
Started Aug 18 05:03:39 PM PDT 24
Finished Aug 18 05:05:49 PM PDT 24
Peak memory 272884 kb
Host smart-34b291ce-3f0c-45ba-8b68-7dbfdd7fc732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324601915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3324601915 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.4268564244
Short name T478
Test name
Test status
Simulation time 1296944402 ps
CPU time 24.64 seconds
Started Aug 18 05:03:37 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 226612 kb
Host smart-0305b01b-483a-4923-a7d3-0b584af50731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268564244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.4268564244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.1868686651
Short name T495
Test name
Test status
Simulation time 26788467928 ps
CPU time 737.33 seconds
Started Aug 18 05:03:56 PM PDT 24
Finished Aug 18 05:16:14 PM PDT 24
Peak memory 637872 kb
Host smart-54e717f6-59c0-4b5c-946b-dd5c3489c7f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1868686651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1868686651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3835710189
Short name T325
Test name
Test status
Simulation time 179663807 ps
CPU time 2.18 seconds
Started Aug 18 05:03:38 PM PDT 24
Finished Aug 18 05:03:41 PM PDT 24
Peak memory 219656 kb
Host smart-62a5ab8c-d25a-403f-8530-524c21ca3125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835710189 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3835710189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.1419247196
Short name T633
Test name
Test status
Simulation time 236775117 ps
CPU time 2.27 seconds
Started Aug 18 05:03:40 PM PDT 24
Finished Aug 18 05:03:43 PM PDT 24
Peak memory 218732 kb
Host smart-f71d7ca4-2425-44b9-a88d-8656e135c63f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419247196 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1419247196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.4042116550
Short name T696
Test name
Test status
Simulation time 2362869922 ps
CPU time 41.92 seconds
Started Aug 18 05:03:40 PM PDT 24
Finished Aug 18 05:04:22 PM PDT 24
Peak memory 226424 kb
Host smart-69c32d7f-fe0c-4e7e-8290-ef8bb2b119ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4042116550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4042116550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.742632755
Short name T32
Test name
Test status
Simulation time 62908789827 ps
CPU time 2108.38 seconds
Started Aug 18 05:03:41 PM PDT 24
Finished Aug 18 05:38:49 PM PDT 24
Peak memory 1119700 kb
Host smart-6a55113a-c78a-4304-81cb-0ce5e8ef1804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=742632755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.742632755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.618245109
Short name T355
Test name
Test status
Simulation time 13478227667 ps
CPU time 1637.2 seconds
Started Aug 18 05:03:40 PM PDT 24
Finished Aug 18 05:30:57 PM PDT 24
Peak memory 882964 kb
Host smart-8ce39a24-7c3e-42fa-9136-0b0ec5edd760
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=618245109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.618245109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.3755145233
Short name T383
Test name
Test status
Simulation time 127092765645 ps
CPU time 1542.86 seconds
Started Aug 18 05:03:38 PM PDT 24
Finished Aug 18 05:29:21 PM PDT 24
Peak memory 1658892 kb
Host smart-8855a6db-5e86-4c58-b054-010d81778a2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3755145233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3755145233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1611983514
Short name T437
Test name
Test status
Simulation time 19395327498 ps
CPU time 237.99 seconds
Started Aug 18 05:03:39 PM PDT 24
Finished Aug 18 05:07:37 PM PDT 24
Peak memory 436056 kb
Host smart-1c11f7e0-7c9f-44ec-87d0-0c885e01060d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1611983514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1611983514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2183821659
Short name T421
Test name
Test status
Simulation time 20763602 ps
CPU time 0.8 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:04:32 PM PDT 24
Peak memory 218172 kb
Host smart-a4e59243-c3bc-45a0-9869-08eb47e1b6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183821659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2183821659 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.1411784134
Short name T34
Test name
Test status
Simulation time 88834685001 ps
CPU time 357.9 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:10:27 PM PDT 24
Peak memory 468756 kb
Host smart-5130b54c-76ce-4bc3-b239-158117338c87
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411784134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1411784134 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.645317198
Short name T614
Test name
Test status
Simulation time 113348238046 ps
CPU time 1487.71 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:29:13 PM PDT 24
Peak memory 262652 kb
Host smart-75d03419-c642-4ef2-9e6e-d7af5b86c291
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645317198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.645317198
+enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.3305080638
Short name T370
Test name
Test status
Simulation time 923234925 ps
CPU time 31.02 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:05:01 PM PDT 24
Peak memory 226124 kb
Host smart-18d35ebe-96ce-42f1-b2a1-74cd48c59433
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305080638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3305080638 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.706581445
Short name T74
Test name
Test status
Simulation time 18408569 ps
CPU time 0.87 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:04:29 PM PDT 24
Peak memory 220224 kb
Host smart-ed3885a7-d431-4485-a74d-9c1f1ad498a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=706581445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.706581445 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3764771207
Short name T472
Test name
Test status
Simulation time 16298467310 ps
CPU time 392.95 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:11:04 PM PDT 24
Peak memory 346488 kb
Host smart-b06ba756-f39c-4eb4-b9fc-dfdb2956a4a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764771207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3
764771207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_key_error.3325659317
Short name T602
Test name
Test status
Simulation time 376286954 ps
CPU time 2.35 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:27 PM PDT 24
Peak memory 226548 kb
Host smart-8753f7bc-dfe0-47b6-8bd8-5a675b5d7bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325659317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3325659317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.844797371
Short name T28
Test name
Test status
Simulation time 41199596 ps
CPU time 1.35 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:04:30 PM PDT 24
Peak memory 226580 kb
Host smart-93d4e4af-4f9e-4953-a866-c75f979fd5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844797371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.844797371 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.122735205
Short name T676
Test name
Test status
Simulation time 3157521577 ps
CPU time 324.68 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:09:53 PM PDT 24
Peak memory 400372 kb
Host smart-dcfee8d2-5f29-443a-bcd4-3642dcfd91e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122735205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an
d_output.122735205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2703438127
Short name T243
Test name
Test status
Simulation time 971735610 ps
CPU time 78.03 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:05:47 PM PDT 24
Peak memory 249992 kb
Host smart-990a04a8-b90c-4202-b83d-ca352962cbe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703438127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2703438127 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.4041571107
Short name T494
Test name
Test status
Simulation time 3931457786 ps
CPU time 80.04 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:05:50 PM PDT 24
Peak memory 229376 kb
Host smart-100b5767-2fac-4035-aed8-56e5f282ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041571107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4041571107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.2376737857
Short name T629
Test name
Test status
Simulation time 223749914795 ps
CPU time 3740.47 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 06:06:50 PM PDT 24
Peak memory 1579712 kb
Host smart-1c6363d6-c7bb-4f82-be8b-e2f6f000e2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2376737857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2376737857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_alert_test.3062220329
Short name T558
Test name
Test status
Simulation time 19018850 ps
CPU time 0.83 seconds
Started Aug 18 05:04:32 PM PDT 24
Finished Aug 18 05:04:33 PM PDT 24
Peak memory 218236 kb
Host smart-05d53652-a96f-4488-9e35-212dc38e768b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062220329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3062220329 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3996344552
Short name T281
Test name
Test status
Simulation time 75577175317 ps
CPU time 1021.86 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:21:33 PM PDT 24
Peak memory 254304 kb
Host smart-e94b8416-8f74-433f-ae94-739444347564
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996344552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.399634455
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.1381437663
Short name T379
Test name
Test status
Simulation time 585310031 ps
CPU time 36.07 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:05:07 PM PDT 24
Peak memory 234436 kb
Host smart-27fb9396-b83b-4290-badf-9d214ea0f215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1381437663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1381437663 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2501515711
Short name T554
Test name
Test status
Simulation time 80035805 ps
CPU time 1.03 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:04:31 PM PDT 24
Peak memory 221788 kb
Host smart-951c790a-8253-4e5e-bd5b-53f181413ae8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2501515711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2501515711 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.718889857
Short name T71
Test name
Test status
Simulation time 8030835243 ps
CPU time 199.69 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:07:51 PM PDT 24
Peak memory 356432 kb
Host smart-a0c431a3-0648-4e06-803f-e7fdb66d7f21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718889857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.71
8889857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.2296328273
Short name T162
Test name
Test status
Simulation time 7601754774 ps
CPU time 321.96 seconds
Started Aug 18 05:04:33 PM PDT 24
Finished Aug 18 05:09:55 PM PDT 24
Peak memory 347344 kb
Host smart-fb04bf95-8178-4dfe-aa0a-b3d03c9207e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296328273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2296328273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3080407204
Short name T568
Test name
Test status
Simulation time 837823097 ps
CPU time 5.96 seconds
Started Aug 18 05:04:32 PM PDT 24
Finished Aug 18 05:04:38 PM PDT 24
Peak memory 226436 kb
Host smart-9ea7a0a9-bf2b-4be5-b598-b5335b72c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080407204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3080407204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.4123511179
Short name T695
Test name
Test status
Simulation time 188100796 ps
CPU time 1.42 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:04:31 PM PDT 24
Peak memory 226664 kb
Host smart-622c0aa4-c365-4c41-a612-46b13b12f9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123511179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.4123511179 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.2118495630
Short name T33
Test name
Test status
Simulation time 4984678775 ps
CPU time 257.27 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:08:47 PM PDT 24
Peak memory 351904 kb
Host smart-ba4ffc98-398c-4c00-88da-e560ef3d1113
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118495630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.2118495630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.4147943435
Short name T197
Test name
Test status
Simulation time 332420579 ps
CPU time 5.38 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:04:35 PM PDT 24
Peak memory 226712 kb
Host smart-c703dd0f-5a7b-4771-adce-4a4086f6dff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147943435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.4147943435 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.31919014
Short name T656
Test name
Test status
Simulation time 2203603059 ps
CPU time 21.27 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:04:52 PM PDT 24
Peak memory 226804 kb
Host smart-ac4fc59d-f30b-4e1a-b503-533ef70ceeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31919014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.31919014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.928019911
Short name T388
Test name
Test status
Simulation time 18408573545 ps
CPU time 130.81 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:06:40 PM PDT 24
Peak memory 288592 kb
Host smart-8b9e2725-c5ee-4ae1-b515-f8275dc3486d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=928019911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.928019911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1970204494
Short name T506
Test name
Test status
Simulation time 21958010 ps
CPU time 0.81 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:41 PM PDT 24
Peak memory 218172 kb
Host smart-b1f426dd-930f-4669-ab91-602322dde7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970204494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1970204494 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.878911473
Short name T259
Test name
Test status
Simulation time 6063431105 ps
CPU time 234.91 seconds
Started Aug 18 05:04:36 PM PDT 24
Finished Aug 18 05:08:31 PM PDT 24
Peak memory 381532 kb
Host smart-7ca18b6f-530c-4d46-a542-588efeda2c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878911473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.878911473 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3672714039
Short name T140
Test name
Test status
Simulation time 152652666829 ps
CPU time 1678.28 seconds
Started Aug 18 05:04:32 PM PDT 24
Finished Aug 18 05:32:31 PM PDT 24
Peak memory 266952 kb
Host smart-3d6d1cca-04c8-41ee-9fc7-b20d5e3624ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672714039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.367271403
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.2711837155
Short name T225
Test name
Test status
Simulation time 456655998 ps
CPU time 9.08 seconds
Started Aug 18 05:04:42 PM PDT 24
Finished Aug 18 05:04:51 PM PDT 24
Peak memory 223916 kb
Host smart-3cf49aff-550b-4c28-ad89-48a2b676f93b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711837155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2711837155 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1456674181
Short name T73
Test name
Test status
Simulation time 12649744 ps
CPU time 0.86 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:41 PM PDT 24
Peak memory 220148 kb
Host smart-0197592d-cd47-468f-a4f2-83d19d42cac8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1456674181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1456674181 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_error.2504952792
Short name T644
Test name
Test status
Simulation time 18337432034 ps
CPU time 239.97 seconds
Started Aug 18 05:04:36 PM PDT 24
Finished Aug 18 05:08:36 PM PDT 24
Peak memory 312148 kb
Host smart-3242fe6d-abc8-48b4-8215-cbd577d2e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504952792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2504952792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.3645852568
Short name T678
Test name
Test status
Simulation time 1390252512 ps
CPU time 9.51 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:04:41 PM PDT 24
Peak memory 226432 kb
Host smart-db1ffb95-864a-40bf-8532-a8cffb7011d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645852568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3645852568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.2752433376
Short name T628
Test name
Test status
Simulation time 88514643 ps
CPU time 1.45 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:41 PM PDT 24
Peak memory 226584 kb
Host smart-5f6451bc-8cc0-4dec-9d8c-ef92b6831977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752433376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2752433376 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.3232111870
Short name T293
Test name
Test status
Simulation time 47039165239 ps
CPU time 850.48 seconds
Started Aug 18 05:04:36 PM PDT 24
Finished Aug 18 05:18:47 PM PDT 24
Peak memory 1161920 kb
Host smart-652ac239-7b8d-4639-b374-029bcb5dffd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232111870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.3232111870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.3286279528
Short name T537
Test name
Test status
Simulation time 6084022746 ps
CPU time 151.39 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:07:03 PM PDT 24
Peak memory 334140 kb
Host smart-2b89191e-385a-4f8f-88bb-d45c48ac25c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286279528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3286279528 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2525194575
Short name T279
Test name
Test status
Simulation time 3876279124 ps
CPU time 81.69 seconds
Started Aug 18 05:04:31 PM PDT 24
Finished Aug 18 05:05:53 PM PDT 24
Peak memory 227784 kb
Host smart-8221e11e-9160-4f6d-a558-71b4335a2146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525194575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2525194575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3415997542
Short name T169
Test name
Test status
Simulation time 58862916168 ps
CPU time 699.96 seconds
Started Aug 18 05:04:42 PM PDT 24
Finished Aug 18 05:16:22 PM PDT 24
Peak memory 322944 kb
Host smart-dcf0a3e2-71d0-4520-9dbf-0dfece4b90c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3415997542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3415997542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_alert_test.2353870953
Short name T500
Test name
Test status
Simulation time 13096673 ps
CPU time 0.83 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:04:53 PM PDT 24
Peak memory 218192 kb
Host smart-b48e93ca-1646-4afa-a4d6-1abb4a7b928d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353870953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2353870953 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.1378896027
Short name T655
Test name
Test status
Simulation time 356493893 ps
CPU time 2.71 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:43 PM PDT 24
Peak memory 226692 kb
Host smart-eb883b42-107d-49ae-a475-57108dc9e619
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378896027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1378896027 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.60258701
Short name T523
Test name
Test status
Simulation time 30446525280 ps
CPU time 767.19 seconds
Started Aug 18 05:04:39 PM PDT 24
Finished Aug 18 05:17:27 PM PDT 24
Peak memory 243192 kb
Host smart-a00f8f20-8236-4152-ac62-6b142fa7d413
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60258701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.60258701 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.3868051541
Short name T662
Test name
Test status
Simulation time 553643507 ps
CPU time 40.52 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:05:20 PM PDT 24
Peak memory 227112 kb
Host smart-d07f9573-cb66-4848-8d2f-f822114d9a0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3868051541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3868051541 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.3825724693
Short name T465
Test name
Test status
Simulation time 1619939382 ps
CPU time 27.48 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:05:07 PM PDT 24
Peak memory 226544 kb
Host smart-25c18bd8-7a75-4567-b6ca-6842b9e3d533
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825724693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.3825724693 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.3541656833
Short name T667
Test name
Test status
Simulation time 3546984457 ps
CPU time 162.6 seconds
Started Aug 18 05:04:39 PM PDT 24
Finished Aug 18 05:07:22 PM PDT 24
Peak memory 274748 kb
Host smart-6214216b-9b97-46ce-b0bf-d257e57cdb52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541656833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3
541656833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2788061153
Short name T677
Test name
Test status
Simulation time 10894714412 ps
CPU time 304.34 seconds
Started Aug 18 05:04:39 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 474996 kb
Host smart-7000df1f-eed8-481a-94e2-9173aac6a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788061153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2788061153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.3597993851
Short name T207
Test name
Test status
Simulation time 2288613863 ps
CPU time 4.93 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:45 PM PDT 24
Peak memory 226480 kb
Host smart-bbbc1001-db03-4fef-af96-741d694d806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597993851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3597993851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.3762861937
Short name T51
Test name
Test status
Simulation time 222172408 ps
CPU time 10.42 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:04:51 PM PDT 24
Peak memory 235008 kb
Host smart-b2361834-4335-495e-a9f9-648b416830e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762861937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3762861937 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.936738887
Short name T541
Test name
Test status
Simulation time 87250232633 ps
CPU time 4333.16 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 06:16:54 PM PDT 24
Peak memory 3303816 kb
Host smart-88f9108c-58c2-4e87-a4d1-75ff8bfe2ca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936738887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.936738887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.3717006675
Short name T606
Test name
Test status
Simulation time 11064865876 ps
CPU time 473.46 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:12:34 PM PDT 24
Peak memory 379432 kb
Host smart-c3899177-bdc9-484b-ba5c-e8dbb8f538d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717006675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3717006675 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.4126842022
Short name T565
Test name
Test status
Simulation time 4691262249 ps
CPU time 41.54 seconds
Started Aug 18 05:04:40 PM PDT 24
Finished Aug 18 05:05:21 PM PDT 24
Peak memory 226832 kb
Host smart-af033620-8e28-4428-b5ae-ad6d4db3a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126842022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.4126842022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.60334671
Short name T366
Test name
Test status
Simulation time 70933492340 ps
CPU time 2205.87 seconds
Started Aug 18 05:04:39 PM PDT 24
Finished Aug 18 05:41:26 PM PDT 24
Peak memory 1343628 kb
Host smart-ad8409d9-23db-4bf1-b78a-a6d11503504c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=60334671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.60334671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1609942548
Short name T648
Test name
Test status
Simulation time 64620217 ps
CPU time 0.83 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:04:53 PM PDT 24
Peak memory 218268 kb
Host smart-181f3583-1dbc-4125-a478-138fca400a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609942548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1609942548 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.273640891
Short name T673
Test name
Test status
Simulation time 15722666184 ps
CPU time 370.42 seconds
Started Aug 18 05:04:53 PM PDT 24
Finished Aug 18 05:11:03 PM PDT 24
Peak memory 499708 kb
Host smart-aa8f627b-98f6-4688-9868-f37a7d9cfbe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273640891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.273640891 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3053054648
Short name T536
Test name
Test status
Simulation time 8136293580 ps
CPU time 814.48 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:18:26 PM PDT 24
Peak memory 238680 kb
Host smart-3988e1f9-1645-41d6-9d9e-6aca644b9296
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053054648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.305305464
8 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1565073771
Short name T658
Test name
Test status
Simulation time 2087669587 ps
CPU time 40.21 seconds
Started Aug 18 05:04:51 PM PDT 24
Finished Aug 18 05:05:32 PM PDT 24
Peak memory 227036 kb
Host smart-e4721d93-6f1c-411c-af39-432ab3f63159
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565073771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1565073771 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.1710770352
Short name T199
Test name
Test status
Simulation time 6588314893 ps
CPU time 19.27 seconds
Started Aug 18 05:04:56 PM PDT 24
Finished Aug 18 05:05:15 PM PDT 24
Peak memory 226608 kb
Host smart-f3afa388-c627-488e-8b72-fdd83a4680be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1710770352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1710770352 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3386489690
Short name T514
Test name
Test status
Simulation time 51603974806 ps
CPU time 334.13 seconds
Started Aug 18 05:04:51 PM PDT 24
Finished Aug 18 05:10:25 PM PDT 24
Peak memory 444488 kb
Host smart-08319dcc-ee7b-4574-ab1d-6fc5b7406a53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386489690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3
386489690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.454428577
Short name T601
Test name
Test status
Simulation time 91823846380 ps
CPU time 177.98 seconds
Started Aug 18 05:04:54 PM PDT 24
Finished Aug 18 05:07:52 PM PDT 24
Peak memory 328144 kb
Host smart-64fd3b94-c91a-4039-ae96-2e1e1547a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454428577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.454428577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.3772949802
Short name T426
Test name
Test status
Simulation time 710114495 ps
CPU time 3.24 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:04:55 PM PDT 24
Peak memory 226520 kb
Host smart-54d26475-9b09-4d97-bd3e-3c9a64214aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772949802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3772949802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3563942428
Short name T584
Test name
Test status
Simulation time 117701489 ps
CPU time 1.27 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:04:53 PM PDT 24
Peak memory 226604 kb
Host smart-d1bf1e06-c3dd-46d0-8258-c30faf68b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563942428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3563942428 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.2021022207
Short name T645
Test name
Test status
Simulation time 1556802499 ps
CPU time 82.1 seconds
Started Aug 18 05:04:51 PM PDT 24
Finished Aug 18 05:06:14 PM PDT 24
Peak memory 267056 kb
Host smart-ffa21292-1731-4f23-90f3-7868971afb78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021022207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.2021022207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1348842903
Short name T278
Test name
Test status
Simulation time 15900885040 ps
CPU time 114.65 seconds
Started Aug 18 05:04:51 PM PDT 24
Finished Aug 18 05:06:46 PM PDT 24
Peak memory 308680 kb
Host smart-47c97d66-029b-4dac-8490-5091b9be0cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348842903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1348842903 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.327657447
Short name T290
Test name
Test status
Simulation time 578586344 ps
CPU time 21.6 seconds
Started Aug 18 05:04:50 PM PDT 24
Finished Aug 18 05:05:11 PM PDT 24
Peak memory 226768 kb
Host smart-b2414192-d8c6-4ee3-88e5-3aebbd0b2b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327657447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.327657447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.972761413
Short name T525
Test name
Test status
Simulation time 25397050603 ps
CPU time 204.14 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:08:16 PM PDT 24
Peak memory 381632 kb
Host smart-9248e3aa-7d4d-4aa2-a5a7-264a38ca99f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=972761413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.972761413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_alert_test.1424880151
Short name T548
Test name
Test status
Simulation time 58102956 ps
CPU time 0.92 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:05:04 PM PDT 24
Peak memory 218124 kb
Host smart-bc4ca74b-78ff-46fa-a2aa-d2c1f5a3e983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424880151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1424880151 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3336762482
Short name T510
Test name
Test status
Simulation time 85174326481 ps
CPU time 364.36 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 05:11:10 PM PDT 24
Peak memory 479620 kb
Host smart-96192dfc-dc03-46fc-829e-0bc1a88560fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336762482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3336762482 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1846713165
Short name T693
Test name
Test status
Simulation time 17068937708 ps
CPU time 864.11 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:19:16 PM PDT 24
Peak memory 240072 kb
Host smart-ed8e96de-6373-497c-92d6-fa672454dccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846713165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.184671316
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2459244006
Short name T65
Test name
Test status
Simulation time 67321876 ps
CPU time 1.17 seconds
Started Aug 18 05:05:06 PM PDT 24
Finished Aug 18 05:05:07 PM PDT 24
Peak memory 218348 kb
Host smart-e7ee3c48-7ded-4b91-8a56-eabc354031f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2459244006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2459244006 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.3482582298
Short name T332
Test name
Test status
Simulation time 23357073 ps
CPU time 0.97 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 05:05:06 PM PDT 24
Peak memory 220372 kb
Host smart-40f80b06-0d66-4de9-8229-b351f7f40451
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482582298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3482582298 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.2696080510
Short name T349
Test name
Test status
Simulation time 22954188362 ps
CPU time 115.73 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:06:58 PM PDT 24
Peak memory 295012 kb
Host smart-564bfdef-c4dd-4f9c-9ae9-992d8c702476
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696080510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.2
696080510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.4159525109
Short name T542
Test name
Test status
Simulation time 5680324622 ps
CPU time 184.99 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:08:08 PM PDT 24
Peak memory 378288 kb
Host smart-b23eeafe-9d34-408c-8932-a4b406c611fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159525109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.4159525109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.1132663358
Short name T359
Test name
Test status
Simulation time 1565217077 ps
CPU time 6.88 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:05:11 PM PDT 24
Peak memory 226460 kb
Host smart-9f8e6a13-9e68-43b7-8922-3f7b68ea590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132663358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1132663358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.54538413
Short name T25
Test name
Test status
Simulation time 55137897 ps
CPU time 1.39 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:04 PM PDT 24
Peak memory 226584 kb
Host smart-6bf4e1ba-3aa4-4327-9b08-ddeb9178a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54538413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.54538413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2739315547
Short name T294
Test name
Test status
Simulation time 14840915646 ps
CPU time 1782.1 seconds
Started Aug 18 05:04:52 PM PDT 24
Finished Aug 18 05:34:34 PM PDT 24
Peak memory 1068084 kb
Host smart-e64e2a8c-af05-4e1c-89a4-53d35462d875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739315547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2739315547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.3027090143
Short name T532
Test name
Test status
Simulation time 1536883370 ps
CPU time 32.42 seconds
Started Aug 18 05:04:50 PM PDT 24
Finished Aug 18 05:05:23 PM PDT 24
Peak memory 233572 kb
Host smart-5c12bdc6-67de-43bd-8f7e-a626a26c03af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027090143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3027090143 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1000439939
Short name T266
Test name
Test status
Simulation time 1530012569 ps
CPU time 57.24 seconds
Started Aug 18 05:04:51 PM PDT 24
Finished Aug 18 05:05:48 PM PDT 24
Peak memory 226728 kb
Host smart-fb013b9b-f360-4b11-b3c5-5db14c89e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000439939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1000439939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.3823702088
Short name T345
Test name
Test status
Simulation time 47403906350 ps
CPU time 1790.56 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:34:55 PM PDT 24
Peak memory 782792 kb
Host smart-f133bf3d-7144-4abb-86f1-2c075b895824
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3823702088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3823702088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_alert_test.1532442153
Short name T539
Test name
Test status
Simulation time 58250258 ps
CPU time 0.83 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:05:04 PM PDT 24
Peak memory 218276 kb
Host smart-2f81ec01-d581-4730-8c7e-5575a95f0b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532442153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1532442153 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.313295613
Short name T238
Test name
Test status
Simulation time 17327814796 ps
CPU time 213.19 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:08:36 PM PDT 24
Peak memory 385764 kb
Host smart-27129a9b-5067-4882-9332-8ae13459c3fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313295613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.313295613 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.791112302
Short name T405
Test name
Test status
Simulation time 228343447952 ps
CPU time 1686.02 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 05:33:12 PM PDT 24
Peak memory 271912 kb
Host smart-31e9a5e8-8e2f-4b33-94be-bfaa20b6873c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791112302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.791112302
+enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3777238249
Short name T665
Test name
Test status
Simulation time 22540716 ps
CPU time 0.89 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:05:05 PM PDT 24
Peak memory 218108 kb
Host smart-faed5338-0a2c-4036-b7a3-cd5e73acf51e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3777238249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3777238249 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.1134626169
Short name T305
Test name
Test status
Simulation time 22320478 ps
CPU time 1.01 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:05:04 PM PDT 24
Peak memory 220688 kb
Host smart-60b6c29b-e56f-412e-9d39-ee728ef6c90c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1134626169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1134626169 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2482429574
Short name T191
Test name
Test status
Simulation time 3265267305 ps
CPU time 95.61 seconds
Started Aug 18 05:05:01 PM PDT 24
Finished Aug 18 05:06:37 PM PDT 24
Peak memory 249124 kb
Host smart-7e69e50c-b3da-4cb2-8fdf-7d860e818b8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482429574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2
482429574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.421472898
Short name T566
Test name
Test status
Simulation time 64222414576 ps
CPU time 442.42 seconds
Started Aug 18 05:05:01 PM PDT 24
Finished Aug 18 05:12:24 PM PDT 24
Peak memory 531464 kb
Host smart-2f126b4b-4730-4365-8057-c7d4c16737f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421472898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.421472898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.1037408918
Short name T714
Test name
Test status
Simulation time 2122550828 ps
CPU time 9.98 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:12 PM PDT 24
Peak memory 226556 kb
Host smart-1fb1a385-f401-4eec-83b5-1c8540729fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037408918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1037408918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3476375517
Short name T221
Test name
Test status
Simulation time 178369155731 ps
CPU time 4928.88 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 06:27:14 PM PDT 24
Peak memory 3694204 kb
Host smart-4a5cf189-f76e-4c71-b120-0e36d6a5f8dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476375517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3476375517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.2019952032
Short name T331
Test name
Test status
Simulation time 3418449863 ps
CPU time 87.94 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 05:06:33 PM PDT 24
Peak memory 289348 kb
Host smart-883959ff-872e-4d3d-b941-eaf890787d9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019952032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2019952032 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1265943450
Short name T659
Test name
Test status
Simulation time 393462587 ps
CPU time 17.74 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:20 PM PDT 24
Peak memory 226720 kb
Host smart-247c8df1-823e-42c8-be67-d85a2b799010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265943450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1265943450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.288230498
Short name T538
Test name
Test status
Simulation time 77047763149 ps
CPU time 870.56 seconds
Started Aug 18 05:05:01 PM PDT 24
Finished Aug 18 05:19:32 PM PDT 24
Peak memory 912796 kb
Host smart-704eb1e2-f7cb-4938-aec8-76c8d98f6cca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=288230498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.288230498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_alert_test.2417401026
Short name T255
Test name
Test status
Simulation time 19259242 ps
CPU time 0.81 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:05:05 PM PDT 24
Peak memory 218280 kb
Host smart-73ed367b-59cf-406a-9f33-20466dd31855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417401026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2417401026 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.3031445022
Short name T621
Test name
Test status
Simulation time 14109170872 ps
CPU time 222.42 seconds
Started Aug 18 05:05:05 PM PDT 24
Finished Aug 18 05:08:47 PM PDT 24
Peak memory 305136 kb
Host smart-26b5f689-eb2f-4c24-9822-c1c630a9cf6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031445022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.3031445022 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.427198225
Short name T277
Test name
Test status
Simulation time 14853370630 ps
CPU time 670.01 seconds
Started Aug 18 05:05:01 PM PDT 24
Finished Aug 18 05:16:11 PM PDT 24
Peak memory 244100 kb
Host smart-530e4067-7b13-43fa-91f8-97750dd65387
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427198225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.427198225
+enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.3727405800
Short name T446
Test name
Test status
Simulation time 4083141785 ps
CPU time 53.13 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:55 PM PDT 24
Peak memory 228948 kb
Host smart-5c88bc48-8d11-4fe1-8119-40ba06d92c2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727405800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3727405800 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1943607364
Short name T252
Test name
Test status
Simulation time 43520729 ps
CPU time 1.26 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:05:05 PM PDT 24
Peak memory 222112 kb
Host smart-e48776f6-8c76-4631-afe2-e44d54af03d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1943607364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1943607364 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.393108429
Short name T265
Test name
Test status
Simulation time 51156344219 ps
CPU time 349.61 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 468124 kb
Host smart-a693bd31-e632-4625-a4a8-93130d15959c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393108429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.39
3108429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1220205158
Short name T487
Test name
Test status
Simulation time 4182072026 ps
CPU time 196.42 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:08:20 PM PDT 24
Peak memory 290084 kb
Host smart-43353d49-7321-4c30-b55b-1ad5b3654159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220205158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1220205158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.1998585447
Short name T585
Test name
Test status
Simulation time 3265410758 ps
CPU time 6.58 seconds
Started Aug 18 05:05:01 PM PDT 24
Finished Aug 18 05:05:08 PM PDT 24
Peak memory 226552 kb
Host smart-7ebf6a4a-4d94-42f6-b812-eb8688112b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998585447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1998585447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1050375468
Short name T256
Test name
Test status
Simulation time 50581624 ps
CPU time 1.35 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 05:05:04 PM PDT 24
Peak memory 226540 kb
Host smart-77e2d6e4-2974-4f32-8a8a-d805c162b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050375468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1050375468 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3626650142
Short name T141
Test name
Test status
Simulation time 87001607521 ps
CPU time 3837.42 seconds
Started Aug 18 05:05:02 PM PDT 24
Finished Aug 18 06:09:00 PM PDT 24
Peak memory 3325436 kb
Host smart-364b4da1-2652-4acd-95d8-df2a50c45b3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626650142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3626650142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.1292499374
Short name T586
Test name
Test status
Simulation time 20229661441 ps
CPU time 589.46 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:14:53 PM PDT 24
Peak memory 668868 kb
Host smart-13e023b1-fb25-441a-9121-b395bfe3a111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292499374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1292499374 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2922640825
Short name T360
Test name
Test status
Simulation time 1539950086 ps
CPU time 32.2 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:05:36 PM PDT 24
Peak memory 226592 kb
Host smart-34e1c52c-ae9b-49ad-b861-03e7a1022bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922640825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2922640825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2770782523
Short name T2
Test name
Test status
Simulation time 37306503732 ps
CPU time 1530.99 seconds
Started Aug 18 05:05:04 PM PDT 24
Finished Aug 18 05:30:35 PM PDT 24
Peak memory 983924 kb
Host smart-68ac5da4-2bb8-4378-a40e-140b70dee7e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2770782523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2770782523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_alert_test.4208764093
Short name T314
Test name
Test status
Simulation time 74007528 ps
CPU time 0.82 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:12 PM PDT 24
Peak memory 218184 kb
Host smart-2b947402-1939-4221-ad07-f46f2bf9d31f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208764093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.4208764093 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.847463238
Short name T553
Test name
Test status
Simulation time 11184796596 ps
CPU time 402.52 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:11:54 PM PDT 24
Peak memory 501628 kb
Host smart-8570c670-0c06-4fd9-b5df-7fb5cc613830
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847463238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.847463238 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.4040580512
Short name T600
Test name
Test status
Simulation time 298986223 ps
CPU time 26.27 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:38 PM PDT 24
Peak memory 226900 kb
Host smart-608d8912-4f74-4c27-97eb-746f178385e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040580512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.404058051
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1054460360
Short name T186
Test name
Test status
Simulation time 1948552280 ps
CPU time 25.14 seconds
Started Aug 18 05:05:12 PM PDT 24
Finished Aug 18 05:05:38 PM PDT 24
Peak memory 226868 kb
Host smart-7701a2d3-87a0-416f-8a08-677cdd8d29cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054460360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1054460360 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.3285030507
Short name T571
Test name
Test status
Simulation time 62779676 ps
CPU time 0.98 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:12 PM PDT 24
Peak memory 218200 kb
Host smart-cdd031d7-715b-4449-82b5-e7d340b34f2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3285030507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3285030507 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.2138029424
Short name T591
Test name
Test status
Simulation time 19709012630 ps
CPU time 245.23 seconds
Started Aug 18 05:05:13 PM PDT 24
Finished Aug 18 05:09:18 PM PDT 24
Peak memory 290108 kb
Host smart-b66b6909-53cb-41b1-b886-588dca10999a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138029424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2
138029424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.1932714237
Short name T297
Test name
Test status
Simulation time 47193516688 ps
CPU time 306.94 seconds
Started Aug 18 05:05:12 PM PDT 24
Finished Aug 18 05:10:19 PM PDT 24
Peak memory 478528 kb
Host smart-bffca9d3-1aea-4b44-9a7d-f06d863e974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932714237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.1932714237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.3275949663
Short name T534
Test name
Test status
Simulation time 4778499229 ps
CPU time 3.97 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:15 PM PDT 24
Peak memory 226616 kb
Host smart-4fad2ba9-126f-4428-a960-99dafa1b6f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275949663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3275949663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2082211968
Short name T687
Test name
Test status
Simulation time 89155836487 ps
CPU time 3992.76 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 3144484 kb
Host smart-0ea90534-5d25-472a-b396-1b9ea979836b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082211968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2082211968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3880398421
Short name T504
Test name
Test status
Simulation time 52987172730 ps
CPU time 422.65 seconds
Started Aug 18 05:05:13 PM PDT 24
Finished Aug 18 05:12:16 PM PDT 24
Peak memory 519976 kb
Host smart-2800229e-1adb-4329-90ec-6985cf09d63c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880398421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3880398421 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.614548309
Short name T262
Test name
Test status
Simulation time 1556568531 ps
CPU time 31.72 seconds
Started Aug 18 05:05:03 PM PDT 24
Finished Aug 18 05:05:35 PM PDT 24
Peak memory 226712 kb
Host smart-909f3ff1-37a0-4e77-8df7-179bcf4d1091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614548309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.614548309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2177955785
Short name T17
Test name
Test status
Simulation time 18296293999 ps
CPU time 1446.63 seconds
Started Aug 18 05:05:10 PM PDT 24
Finished Aug 18 05:29:17 PM PDT 24
Peak memory 726668 kb
Host smart-edf33d54-072b-4902-97c6-c721a6c63125
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2177955785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2177955785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_alert_test.2976747381
Short name T527
Test name
Test status
Simulation time 30987437 ps
CPU time 0.82 seconds
Started Aug 18 05:05:12 PM PDT 24
Finished Aug 18 05:05:13 PM PDT 24
Peak memory 218256 kb
Host smart-b32b32e1-2ef0-4485-91f3-6590771157f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976747381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2976747381 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2139299634
Short name T711
Test name
Test status
Simulation time 14787067181 ps
CPU time 228.63 seconds
Started Aug 18 05:05:13 PM PDT 24
Finished Aug 18 05:09:02 PM PDT 24
Peak memory 296660 kb
Host smart-bb0c506f-08c8-4966-bcf0-73125fe93715
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139299634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2139299634 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2553825073
Short name T672
Test name
Test status
Simulation time 13851805644 ps
CPU time 1493.03 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:30:04 PM PDT 24
Peak memory 247204 kb
Host smart-ab0e8bf2-d414-44ab-a426-6903991165a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553825073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.255382507
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.3778090022
Short name T708
Test name
Test status
Simulation time 1207966667 ps
CPU time 14.6 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:25 PM PDT 24
Peak memory 225800 kb
Host smart-5cbefe3b-70fd-4041-8853-3d22bb1ac1f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3778090022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3778090022 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.789210424
Short name T646
Test name
Test status
Simulation time 18556733 ps
CPU time 0.97 seconds
Started Aug 18 05:05:12 PM PDT 24
Finished Aug 18 05:05:13 PM PDT 24
Peak memory 220248 kb
Host smart-26b87ab8-9753-4cbc-9eb5-32f41113dc63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=789210424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.789210424 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3786903208
Short name T346
Test name
Test status
Simulation time 22502901361 ps
CPU time 428.46 seconds
Started Aug 18 05:05:12 PM PDT 24
Finished Aug 18 05:12:20 PM PDT 24
Peak memory 501064 kb
Host smart-f8f0c321-db84-4635-99aa-91cf83a2bf56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786903208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3
786903208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.4069406105
Short name T23
Test name
Test status
Simulation time 21321970389 ps
CPU time 290.57 seconds
Started Aug 18 05:05:10 PM PDT 24
Finished Aug 18 05:10:01 PM PDT 24
Peak memory 454364 kb
Host smart-a21ce2ff-cff5-4a74-a169-8998a1f02a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069406105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.4069406105 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.4150047789
Short name T626
Test name
Test status
Simulation time 5359308889 ps
CPU time 11.69 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:23 PM PDT 24
Peak memory 226576 kb
Host smart-191593c6-89e6-4704-9222-74dd98aaf3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150047789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.4150047789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.2273652731
Short name T78
Test name
Test status
Simulation time 49364028 ps
CPU time 1.16 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:12 PM PDT 24
Peak memory 226588 kb
Host smart-1ea09b80-2cd9-4d61-a677-9fb5e79d899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273652731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2273652731 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3836268007
Short name T635
Test name
Test status
Simulation time 74380042756 ps
CPU time 3087.65 seconds
Started Aug 18 05:05:10 PM PDT 24
Finished Aug 18 05:56:38 PM PDT 24
Peak memory 2820944 kb
Host smart-8a7546f4-9b07-43f1-8455-5c26ae1aa42b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836268007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3836268007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2467624386
Short name T688
Test name
Test status
Simulation time 170761641 ps
CPU time 3.21 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:05:15 PM PDT 24
Peak memory 226684 kb
Host smart-4143c569-187c-47d2-bbdc-c340e9f7ce6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467624386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2467624386 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.3475167760
Short name T551
Test name
Test status
Simulation time 404326810 ps
CPU time 2.59 seconds
Started Aug 18 05:05:13 PM PDT 24
Finished Aug 18 05:05:16 PM PDT 24
Peak memory 222404 kb
Host smart-e35bf16c-7006-4b57-aac3-04962454e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475167760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3475167760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.632263401
Short name T333
Test name
Test status
Simulation time 6147602449 ps
CPU time 154.72 seconds
Started Aug 18 05:05:09 PM PDT 24
Finished Aug 18 05:07:44 PM PDT 24
Peak memory 319976 kb
Host smart-efbd57a7-dbf8-4ce7-904f-1cff9a127ab0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=632263401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.632263401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_alert_test.218401665
Short name T371
Test name
Test status
Simulation time 36455590 ps
CPU time 0.78 seconds
Started Aug 18 05:03:55 PM PDT 24
Finished Aug 18 05:03:56 PM PDT 24
Peak memory 218224 kb
Host smart-413a111c-b1d2-4cb2-a991-e19e74e28f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218401665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.218401665 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2061265601
Short name T326
Test name
Test status
Simulation time 78691940935 ps
CPU time 392.42 seconds
Started Aug 18 05:03:51 PM PDT 24
Finished Aug 18 05:10:23 PM PDT 24
Peak memory 509092 kb
Host smart-a3467385-07bf-4d54-a141-48d1013903a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061265601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_par
tial_data.2061265601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.175193363
Short name T258
Test name
Test status
Simulation time 10595102723 ps
CPU time 980.8 seconds
Started Aug 18 05:03:52 PM PDT 24
Finished Aug 18 05:20:13 PM PDT 24
Peak memory 242180 kb
Host smart-a762d893-c3ad-4e79-a943-b83704e23c30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175193363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.175193363 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1185833078
Short name T466
Test name
Test status
Simulation time 448617273 ps
CPU time 1.23 seconds
Started Aug 18 05:03:53 PM PDT 24
Finished Aug 18 05:03:54 PM PDT 24
Peak memory 218492 kb
Host smart-816d6c6a-5e66-4fd2-83bf-6c7a17eb39cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1185833078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1185833078 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.1975235096
Short name T459
Test name
Test status
Simulation time 20078025 ps
CPU time 0.9 seconds
Started Aug 18 05:03:49 PM PDT 24
Finished Aug 18 05:03:50 PM PDT 24
Peak memory 220300 kb
Host smart-3e0f3dc5-ad71-4f0e-82d9-7621c6e4b986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975235096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1975235096 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.638263166
Short name T620
Test name
Test status
Simulation time 5180770086 ps
CPU time 12.21 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:11 PM PDT 24
Peak memory 226696 kb
Host smart-e336cfc1-1ef5-42a4-b334-ca1366a2f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638263166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.638263166 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3606757917
Short name T222
Test name
Test status
Simulation time 7438581419 ps
CPU time 173.03 seconds
Started Aug 18 05:03:55 PM PDT 24
Finished Aug 18 05:06:48 PM PDT 24
Peak memory 337840 kb
Host smart-5268c8d4-8426-4915-841f-70065931bf3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606757917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.36
06757917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.2287757915
Short name T632
Test name
Test status
Simulation time 20640641220 ps
CPU time 540.78 seconds
Started Aug 18 05:03:49 PM PDT 24
Finished Aug 18 05:12:50 PM PDT 24
Peak memory 638924 kb
Host smart-4366ef25-4e68-4ccf-b389-6a4844a2bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287757915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2287757915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.1892335956
Short name T6
Test name
Test status
Simulation time 224488532 ps
CPU time 2.54 seconds
Started Aug 18 05:03:55 PM PDT 24
Finished Aug 18 05:03:58 PM PDT 24
Peak memory 226528 kb
Host smart-e587ab98-ad92-4006-9e93-c0d7f50192a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892335956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1892335956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_mubi.480805426
Short name T280
Test name
Test status
Simulation time 19584857499 ps
CPU time 224.41 seconds
Started Aug 18 05:03:56 PM PDT 24
Finished Aug 18 05:07:40 PM PDT 24
Peak memory 401576 kb
Host smart-eef5c244-3229-43be-970a-085bf64d2b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480805426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.480805426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4051245814
Short name T31
Test name
Test status
Simulation time 11267235885 ps
CPU time 96.79 seconds
Started Aug 18 05:03:48 PM PDT 24
Finished Aug 18 05:05:25 PM PDT 24
Peak memory 281328 kb
Host smart-f3f8b9d5-1606-4090-9cbf-d7537a94a0fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051245814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4051245814 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.2476223817
Short name T365
Test name
Test status
Simulation time 6791870668 ps
CPU time 140.25 seconds
Started Aug 18 05:03:56 PM PDT 24
Finished Aug 18 05:06:16 PM PDT 24
Peak memory 271820 kb
Host smart-e032f39c-d5fc-4f26-89fc-eea6a032913f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476223817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2476223817 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2815237615
Short name T315
Test name
Test status
Simulation time 34313554560 ps
CPU time 44.76 seconds
Started Aug 18 05:03:49 PM PDT 24
Finished Aug 18 05:04:34 PM PDT 24
Peak memory 226696 kb
Host smart-d7d6c8a2-0ac6-480c-89da-fa386193a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815237615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2815237615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.1570585930
Short name T72
Test name
Test status
Simulation time 24456535450 ps
CPU time 830.62 seconds
Started Aug 18 05:03:49 PM PDT 24
Finished Aug 18 05:17:39 PM PDT 24
Peak memory 398884 kb
Host smart-83478d0a-9795-4677-b211-911f21acf9f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1570585930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1570585930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_stress_all_with_rand_reset.3269764656
Short name T43
Test name
Test status
Simulation time 3474498591 ps
CPU time 100.79 seconds
Started Aug 18 05:03:54 PM PDT 24
Finished Aug 18 05:05:35 PM PDT 24
Peak memory 243296 kb
Host smart-c860aa69-0fd0-4934-996e-791bf68fad1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269764656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.3269764656 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.2616096707
Short name T618
Test name
Test status
Simulation time 105393415 ps
CPU time 2.44 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 219444 kb
Host smart-74298a19-a2cf-454d-aeb4-48fcd881aa37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616096707 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.2616096707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.687854242
Short name T353
Test name
Test status
Simulation time 253311873 ps
CPU time 3.95 seconds
Started Aug 18 05:03:48 PM PDT 24
Finished Aug 18 05:03:52 PM PDT 24
Peak memory 219512 kb
Host smart-b92827a7-53f1-4998-91ff-7ebb001621c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687854242 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.kmac_test_vectors_kmac_xof.687854242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.3662998297
Short name T110
Test name
Test status
Simulation time 314960280083 ps
CPU time 3012.35 seconds
Started Aug 18 05:03:50 PM PDT 24
Finished Aug 18 05:54:03 PM PDT 24
Peak memory 3071396 kb
Host smart-b0d9d36d-75a8-4cc4-a87c-0cbc0ed40545
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3662998297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3662998297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3900254632
Short name T324
Test name
Test status
Simulation time 934053419651 ps
CPU time 3474.03 seconds
Started Aug 18 05:03:54 PM PDT 24
Finished Aug 18 06:01:49 PM PDT 24
Peak memory 2897068 kb
Host smart-e3d378e8-a399-4566-b154-1150d898d01a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3900254632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3900254632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.3001332666
Short name T291
Test name
Test status
Simulation time 8377143572 ps
CPU time 35.8 seconds
Started Aug 18 05:03:54 PM PDT 24
Finished Aug 18 05:04:30 PM PDT 24
Peak memory 235060 kb
Host smart-716bde6f-c40c-4c9f-a28a-ef8cf3d60584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3001332666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3001332666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.4067929045
Short name T232
Test name
Test status
Simulation time 111382084596 ps
CPU time 1531.84 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:29:32 PM PDT 24
Peak memory 1695496 kb
Host smart-45134678-558a-4272-a875-bf47d7f9b20a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4067929045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.4067929045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.2638489163
Short name T461
Test name
Test status
Simulation time 108730961111 ps
CPU time 4365.1 seconds
Started Aug 18 05:03:56 PM PDT 24
Finished Aug 18 06:16:41 PM PDT 24
Peak memory 3546984 kb
Host smart-871e4e7d-94cf-4e2c-bfef-7524d335a70c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2638489163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2638489163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.4081275653
Short name T401
Test name
Test status
Simulation time 19977877496 ps
CPU time 118.01 seconds
Started Aug 18 05:03:55 PM PDT 24
Finished Aug 18 05:05:53 PM PDT 24
Peak memory 259288 kb
Host smart-d451126a-177c-466e-a6dc-c2511fd6bbba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4081275653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.4081275653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.2580684204
Short name T502
Test name
Test status
Simulation time 49345332 ps
CPU time 0.82 seconds
Started Aug 18 05:05:25 PM PDT 24
Finished Aug 18 05:05:26 PM PDT 24
Peak memory 218192 kb
Host smart-96455113-fa03-48da-9d60-720e3844eb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580684204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2580684204 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.1174664682
Short name T319
Test name
Test status
Simulation time 20582001654 ps
CPU time 73.45 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:06:36 PM PDT 24
Peak memory 270640 kb
Host smart-ec7d71a6-acc5-46ca-87c3-9049946ac250
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174664682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1174664682 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.1604128126
Short name T244
Test name
Test status
Simulation time 36583834159 ps
CPU time 1560.91 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:31:23 PM PDT 24
Peak memory 264616 kb
Host smart-30b88bdc-740b-44c9-a0fc-0c38c19163bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604128126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.160412812
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.155509643
Short name T625
Test name
Test status
Simulation time 5628755218 ps
CPU time 62.28 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:06:24 PM PDT 24
Peak memory 265848 kb
Host smart-0226955b-337e-4113-9484-ba461e4e9fe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155509643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.15
5509643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1821317786
Short name T137
Test name
Test status
Simulation time 32730310247 ps
CPU time 208.11 seconds
Started Aug 18 05:05:23 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 375676 kb
Host smart-07985147-6163-465c-8fbe-bd77c98b722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821317786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1821317786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.1581540909
Short name T598
Test name
Test status
Simulation time 3765844735 ps
CPU time 9.01 seconds
Started Aug 18 05:05:25 PM PDT 24
Finished Aug 18 05:05:34 PM PDT 24
Peak memory 226556 kb
Host smart-277fa8b6-eff8-420d-ad7e-af36351b9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581540909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1581540909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.3683925267
Short name T590
Test name
Test status
Simulation time 164557233 ps
CPU time 1.33 seconds
Started Aug 18 05:05:21 PM PDT 24
Finished Aug 18 05:05:23 PM PDT 24
Peak memory 226588 kb
Host smart-c56a48e8-7858-4eaf-bf55-7f95bde6d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683925267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3683925267 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.3787060063
Short name T195
Test name
Test status
Simulation time 244530656418 ps
CPU time 2560.56 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:47:52 PM PDT 24
Peak memory 2401356 kb
Host smart-27218ce6-72da-489c-82f2-15819fa39cdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787060063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.3787060063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.4041977416
Short name T654
Test name
Test status
Simulation time 3758780117 ps
CPU time 93.59 seconds
Started Aug 18 05:05:10 PM PDT 24
Finished Aug 18 05:06:44 PM PDT 24
Peak memory 301548 kb
Host smart-9777bb72-4243-4c89-abdb-80aee6c17a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041977416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.4041977416 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3491615207
Short name T526
Test name
Test status
Simulation time 37960581187 ps
CPU time 66.95 seconds
Started Aug 18 05:05:11 PM PDT 24
Finished Aug 18 05:06:18 PM PDT 24
Peak memory 225416 kb
Host smart-0d96f95d-afd1-484f-a08b-099b60305d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491615207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3491615207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.1181510430
Short name T97
Test name
Test status
Simulation time 403774779 ps
CPU time 46.45 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:06:08 PM PDT 24
Peak memory 226744 kb
Host smart-1f17b0a4-afc0-4b1e-abdb-46ab0aebcc2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1181510430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1181510430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1101319184
Short name T471
Test name
Test status
Simulation time 60886084 ps
CPU time 0.84 seconds
Started Aug 18 05:05:24 PM PDT 24
Finished Aug 18 05:05:25 PM PDT 24
Peak memory 218256 kb
Host smart-3e097982-49a3-4834-bbce-3b2d62787786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101319184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1101319184 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.3079053956
Short name T480
Test name
Test status
Simulation time 4758334294 ps
CPU time 331.66 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 325108 kb
Host smart-cc1864cf-5eac-4cde-a0b0-d0c57c12b599
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079053956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3079053956 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.883834494
Short name T611
Test name
Test status
Simulation time 25779528201 ps
CPU time 1310.43 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:27:13 PM PDT 24
Peak memory 264168 kb
Host smart-01d028e7-7db6-4bdc-b8de-3c256e36ef9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883834494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.883834494
+enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1638127235
Short name T549
Test name
Test status
Simulation time 873901043 ps
CPU time 15.78 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:05:38 PM PDT 24
Peak memory 224756 kb
Host smart-adcc04ee-435b-4f5e-8b15-bfbdb410b24d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638127235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1
638127235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.3867228205
Short name T530
Test name
Test status
Simulation time 27513062547 ps
CPU time 464.88 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:13:07 PM PDT 24
Peak memory 376540 kb
Host smart-279b5414-7cfb-4ff4-9c1d-2fa7bc01968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867228205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.3867228205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.4147505148
Short name T104
Test name
Test status
Simulation time 5645722311 ps
CPU time 5.75 seconds
Started Aug 18 05:05:21 PM PDT 24
Finished Aug 18 05:05:27 PM PDT 24
Peak memory 226628 kb
Host smart-89bdcd0b-1796-485b-a5e2-06a1773bee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147505148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.4147505148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.2564089624
Short name T653
Test name
Test status
Simulation time 5725235540 ps
CPU time 86.77 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:06:48 PM PDT 24
Peak memory 336476 kb
Host smart-d5db54a0-b790-4f7b-a293-a61e977b19e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564089624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.2564089624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.3056296535
Short name T352
Test name
Test status
Simulation time 49721623250 ps
CPU time 449.15 seconds
Started Aug 18 05:05:23 PM PDT 24
Finished Aug 18 05:12:52 PM PDT 24
Peak memory 541984 kb
Host smart-656152b4-de49-48a9-b03c-eb0c59620ac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056296535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3056296535 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.1352036294
Short name T210
Test name
Test status
Simulation time 1766670254 ps
CPU time 42.79 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:06:05 PM PDT 24
Peak memory 222064 kb
Host smart-144fa140-9f50-4580-94cc-b6dc88b03088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352036294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1352036294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3419151846
Short name T700
Test name
Test status
Simulation time 82956579675 ps
CPU time 491.12 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 05:13:33 PM PDT 24
Peak memory 486056 kb
Host smart-36c8cfa0-0460-4eb4-a0e6-43f19f08e8da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3419151846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3419151846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_alert_test.1327944898
Short name T564
Test name
Test status
Simulation time 12202560 ps
CPU time 0.81 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:05:35 PM PDT 24
Peak memory 218236 kb
Host smart-6aafe7e1-002a-4a08-9dda-59eac504bdc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327944898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1327944898 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3690483402
Short name T441
Test name
Test status
Simulation time 2799367676 ps
CPU time 164.08 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:08:19 PM PDT 24
Peak memory 274324 kb
Host smart-1c2bc60c-51f6-4705-914d-2ed92651f896
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690483402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3690483402 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1540469221
Short name T555
Test name
Test status
Simulation time 22433639568 ps
CPU time 607.85 seconds
Started Aug 18 05:05:35 PM PDT 24
Finished Aug 18 05:15:43 PM PDT 24
Peak memory 236880 kb
Host smart-1378f960-960d-46a7-ab7e-a61968cf8d01
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540469221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.154046922
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.779869751
Short name T98
Test name
Test status
Simulation time 3906236874 ps
CPU time 17.69 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:05:53 PM PDT 24
Peak memory 226660 kb
Host smart-b1ff2e63-88ca-44f2-b73a-f75bf756685c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779869751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.77
9869751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.2154353398
Short name T599
Test name
Test status
Simulation time 1440015215 ps
CPU time 101.05 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:07:15 PM PDT 24
Peak memory 273888 kb
Host smart-8f2dd08d-172a-46a3-9079-e8368e2a1a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154353398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2154353398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.2829340031
Short name T322
Test name
Test status
Simulation time 2542502947 ps
CPU time 5.73 seconds
Started Aug 18 05:05:37 PM PDT 24
Finished Aug 18 05:05:42 PM PDT 24
Peak memory 226616 kb
Host smart-f614d1e3-ad09-4c3f-8b6f-6c07275ccc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829340031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2829340031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3480851917
Short name T344
Test name
Test status
Simulation time 113446048601 ps
CPU time 3774.81 seconds
Started Aug 18 05:05:22 PM PDT 24
Finished Aug 18 06:08:17 PM PDT 24
Peak memory 1853596 kb
Host smart-702c87c8-032d-4fa2-a2a2-e572213e3023
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480851917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3480851917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.3239636751
Short name T96
Test name
Test status
Simulation time 4394335183 ps
CPU time 359.23 seconds
Started Aug 18 05:05:23 PM PDT 24
Finished Aug 18 05:11:22 PM PDT 24
Peak memory 341864 kb
Host smart-f108e4c0-0a32-41de-be69-77e6e04522ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239636751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3239636751 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1028929013
Short name T139
Test name
Test status
Simulation time 4468366900 ps
CPU time 48.83 seconds
Started Aug 18 05:05:25 PM PDT 24
Finished Aug 18 05:06:13 PM PDT 24
Peak memory 223468 kb
Host smart-d5711b65-7f4a-451e-ac52-16f60baa4fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028929013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1028929013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3193402224
Short name T449
Test name
Test status
Simulation time 77435568600 ps
CPU time 2664.18 seconds
Started Aug 18 05:05:35 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 1109012 kb
Host smart-11a0f8df-40ff-4815-b2ff-f76ffef1e1e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3193402224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3193402224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_alert_test.4159794885
Short name T275
Test name
Test status
Simulation time 63044511 ps
CPU time 0.85 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:05:37 PM PDT 24
Peak memory 218196 kb
Host smart-9d2aad39-5e66-4fdd-8fb1-29cd036972fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159794885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.4159794885 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.3848704830
Short name T573
Test name
Test status
Simulation time 19957137943 ps
CPU time 246.38 seconds
Started Aug 18 05:05:37 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 416256 kb
Host smart-286fb2db-680d-44f2-a082-e9711cb21193
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848704830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3848704830 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.3095341167
Short name T690
Test name
Test status
Simulation time 9625716767 ps
CPU time 424 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:12:40 PM PDT 24
Peak memory 240592 kb
Host smart-36891daf-96bf-4486-8565-237062f59936
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095341167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.309534116
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.236887018
Short name T304
Test name
Test status
Simulation time 6599983281 ps
CPU time 408.24 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:12:22 PM PDT 24
Peak memory 357064 kb
Host smart-381b923f-e34d-43fb-b757-1a16d6b4b05e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236887018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.23
6887018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.766155849
Short name T513
Test name
Test status
Simulation time 27555679617 ps
CPU time 452.16 seconds
Started Aug 18 05:05:37 PM PDT 24
Finished Aug 18 05:13:10 PM PDT 24
Peak memory 560716 kb
Host smart-e716e4d9-2bca-4103-8c15-9157233c3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766155849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.766155849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.684805102
Short name T219
Test name
Test status
Simulation time 1180937052 ps
CPU time 2.09 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:05:38 PM PDT 24
Peak memory 226592 kb
Host smart-3c2f66be-5acf-472a-ac5a-48f6e42f42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684805102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.684805102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1579765462
Short name T321
Test name
Test status
Simulation time 146668414890 ps
CPU time 3000.72 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:55:35 PM PDT 24
Peak memory 1559368 kb
Host smart-f120e2b9-bad2-4bf8-8fa2-6aadd4177f83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579765462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1579765462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2588850518
Short name T498
Test name
Test status
Simulation time 49964674436 ps
CPU time 339.33 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:11:16 PM PDT 24
Peak memory 478560 kb
Host smart-b8f4286b-4782-47ed-92b6-7e15b74b8cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588850518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2588850518 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1700019891
Short name T227
Test name
Test status
Simulation time 435479959 ps
CPU time 16.14 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:05:52 PM PDT 24
Peak memory 226728 kb
Host smart-f4eec814-698c-4aef-896f-3661312ba987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700019891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1700019891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1999691932
Short name T560
Test name
Test status
Simulation time 37039124153 ps
CPU time 321.71 seconds
Started Aug 18 05:05:35 PM PDT 24
Finished Aug 18 05:10:57 PM PDT 24
Peak memory 334372 kb
Host smart-66f8e1bd-e6c8-4559-a092-a7cb20d77c66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1999691932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1999691932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_alert_test.3364398309
Short name T369
Test name
Test status
Simulation time 16415928 ps
CPU time 0.85 seconds
Started Aug 18 05:05:44 PM PDT 24
Finished Aug 18 05:05:45 PM PDT 24
Peak memory 218188 kb
Host smart-af62ddaa-ca81-4046-b7e6-a4be92b2ca9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364398309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.3364398309 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3870373131
Short name T260
Test name
Test status
Simulation time 1121289310 ps
CPU time 70.82 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:06:47 PM PDT 24
Peak memory 244560 kb
Host smart-d20fa223-62d2-44a5-a5d1-4c887126a63a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870373131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3870373131 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.1466479781
Short name T400
Test name
Test status
Simulation time 79280003303 ps
CPU time 844.6 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:19:39 PM PDT 24
Peak memory 252880 kb
Host smart-587ff0b5-59ff-4cf2-a76b-abf9f6efb3c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466479781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.146647978
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3845397644
Short name T477
Test name
Test status
Simulation time 60672904806 ps
CPU time 453.27 seconds
Started Aug 18 05:05:37 PM PDT 24
Finished Aug 18 05:13:11 PM PDT 24
Peak memory 507412 kb
Host smart-493658a7-cd1b-4152-9b71-9216079156cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845397644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3
845397644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.520010068
Short name T394
Test name
Test status
Simulation time 48932045358 ps
CPU time 338.71 seconds
Started Aug 18 05:05:35 PM PDT 24
Finished Aug 18 05:11:14 PM PDT 24
Peak memory 491296 kb
Host smart-b5aef1cf-5684-44ae-8ea3-0ef34c2f5723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520010068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.520010068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1500170455
Short name T108
Test name
Test status
Simulation time 953543825 ps
CPU time 2.71 seconds
Started Aug 18 05:05:44 PM PDT 24
Finished Aug 18 05:05:46 PM PDT 24
Peak memory 226344 kb
Host smart-2b1e76b8-638b-4c8d-a65c-f08f335cfd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500170455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1500170455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2413971272
Short name T439
Test name
Test status
Simulation time 296057218 ps
CPU time 1.41 seconds
Started Aug 18 05:05:46 PM PDT 24
Finished Aug 18 05:05:47 PM PDT 24
Peak memory 226576 kb
Host smart-1a9a6746-3356-4b4e-b600-412929a88e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413971272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2413971272 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.418832902
Short name T467
Test name
Test status
Simulation time 261239676112 ps
CPU time 2927.74 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:54:22 PM PDT 24
Peak memory 1483568 kb
Host smart-e3b0aa16-1008-4666-b311-86fddc7e2d82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418832902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.418832902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.3023140970
Short name T356
Test name
Test status
Simulation time 11554727055 ps
CPU time 333.62 seconds
Started Aug 18 05:05:36 PM PDT 24
Finished Aug 18 05:11:09 PM PDT 24
Peak memory 488104 kb
Host smart-83d4412b-0e52-4ee7-be91-d3a0e7920a4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023140970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3023140970 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2130758645
Short name T132
Test name
Test status
Simulation time 9276531763 ps
CPU time 71.77 seconds
Started Aug 18 05:05:34 PM PDT 24
Finished Aug 18 05:06:46 PM PDT 24
Peak memory 225092 kb
Host smart-abb1aa22-6ee9-498e-8d3b-8b04999b6814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130758645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2130758645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2970760384
Short name T411
Test name
Test status
Simulation time 368928957963 ps
CPU time 1385.71 seconds
Started Aug 18 05:05:45 PM PDT 24
Finished Aug 18 05:28:51 PM PDT 24
Peak memory 984496 kb
Host smart-00812b35-2a6a-41be-89b7-4920c87c7cf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2970760384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2970760384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_alert_test.3263356714
Short name T102
Test name
Test status
Simulation time 15899229 ps
CPU time 0.83 seconds
Started Aug 18 05:05:45 PM PDT 24
Finished Aug 18 05:05:46 PM PDT 24
Peak memory 218264 kb
Host smart-0380ac44-d1d9-448b-b9a5-2c13c00a5e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263356714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3263356714 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.70857060
Short name T170
Test name
Test status
Simulation time 16879814455 ps
CPU time 253.46 seconds
Started Aug 18 05:05:45 PM PDT 24
Finished Aug 18 05:09:58 PM PDT 24
Peak memory 391232 kb
Host smart-568b9cd3-5c53-4b6c-b639-97e10a0164df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70857060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.70857060 +enable_masking=1
+sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2570012371
Short name T420
Test name
Test status
Simulation time 207650125757 ps
CPU time 1273.54 seconds
Started Aug 18 05:05:45 PM PDT 24
Finished Aug 18 05:26:59 PM PDT 24
Peak memory 249016 kb
Host smart-80d3ef7e-1beb-4ae1-a4d4-0033a11e1e98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570012371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.257001237
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.45566830
Short name T9
Test name
Test status
Simulation time 15510893048 ps
CPU time 196.22 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:08:59 PM PDT 24
Peak memory 350464 kb
Host smart-81106376-a893-48b1-bb5d-8d1ed01bb205
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45566830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.455
66830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.70918644
Short name T296
Test name
Test status
Simulation time 8175429425 ps
CPU time 311.03 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:10:54 PM PDT 24
Peak memory 343616 kb
Host smart-555bf5b6-741d-47f9-b141-32eea7528ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70918644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.70918644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.840843407
Short name T399
Test name
Test status
Simulation time 5166097086 ps
CPU time 11.08 seconds
Started Aug 18 05:05:44 PM PDT 24
Finished Aug 18 05:05:55 PM PDT 24
Peak memory 226552 kb
Host smart-ab24a573-8014-44dd-a2dd-f4f8519243ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840843407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.840843407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.1888468314
Short name T45
Test name
Test status
Simulation time 44316276 ps
CPU time 1.34 seconds
Started Aug 18 05:05:46 PM PDT 24
Finished Aug 18 05:05:47 PM PDT 24
Peak memory 226632 kb
Host smart-13f4c19c-73f9-4de7-b87c-1ce87201b8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888468314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1888468314 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.3959948934
Short name T190
Test name
Test status
Simulation time 35363946616 ps
CPU time 746.12 seconds
Started Aug 18 05:05:45 PM PDT 24
Finished Aug 18 05:18:11 PM PDT 24
Peak memory 976356 kb
Host smart-330000e1-fc6c-4bc7-a72b-74fcad464f41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959948934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.3959948934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.713245484
Short name T202
Test name
Test status
Simulation time 1489857779 ps
CPU time 116.09 seconds
Started Aug 18 05:05:47 PM PDT 24
Finished Aug 18 05:07:44 PM PDT 24
Peak memory 262112 kb
Host smart-d79706b0-9064-46e5-b9a5-10608ad5cbd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713245484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.713245484 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3457870681
Short name T517
Test name
Test status
Simulation time 1064310453 ps
CPU time 26.2 seconds
Started Aug 18 05:05:44 PM PDT 24
Finished Aug 18 05:06:10 PM PDT 24
Peak memory 226576 kb
Host smart-4da5d429-cc93-4719-82f8-ad5f87290692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457870681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3457870681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.88812211
Short name T375
Test name
Test status
Simulation time 122377451679 ps
CPU time 2658.19 seconds
Started Aug 18 05:05:46 PM PDT 24
Finished Aug 18 05:50:04 PM PDT 24
Peak memory 831516 kb
Host smart-67a8cad5-c7bf-4b25-8e06-39d009e5a409
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=88812211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.88812211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_alert_test.485102160
Short name T484
Test name
Test status
Simulation time 28728896 ps
CPU time 0.9 seconds
Started Aug 18 05:05:57 PM PDT 24
Finished Aug 18 05:05:58 PM PDT 24
Peak memory 218252 kb
Host smart-e190cc38-b5a5-457e-b671-715b80495e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485102160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.485102160 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.994812588
Short name T373
Test name
Test status
Simulation time 21728770889 ps
CPU time 406.66 seconds
Started Aug 18 05:05:46 PM PDT 24
Finished Aug 18 05:12:33 PM PDT 24
Peak memory 334936 kb
Host smart-98963eed-15fc-4540-bc4e-4aee9a5c307e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994812588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.994812588 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.3945321839
Short name T447
Test name
Test status
Simulation time 16970205988 ps
CPU time 959.72 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:21:43 PM PDT 24
Peak memory 253832 kb
Host smart-9fd7377d-580c-4db4-a884-15f29c6dab27
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945321839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.394532183
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_error.3527409644
Short name T684
Test name
Test status
Simulation time 32765880900 ps
CPU time 265.31 seconds
Started Aug 18 05:05:55 PM PDT 24
Finished Aug 18 05:10:21 PM PDT 24
Peak memory 442080 kb
Host smart-5100793a-fb47-4180-9676-decf1373ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527409644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3527409644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2513156063
Short name T330
Test name
Test status
Simulation time 1527022787 ps
CPU time 11.27 seconds
Started Aug 18 05:05:56 PM PDT 24
Finished Aug 18 05:06:07 PM PDT 24
Peak memory 226480 kb
Host smart-cdf5caba-e4eb-40fa-83ec-b0074a67e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513156063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2513156063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.640932308
Short name T47
Test name
Test status
Simulation time 92159399 ps
CPU time 1.42 seconds
Started Aug 18 05:05:57 PM PDT 24
Finished Aug 18 05:05:59 PM PDT 24
Peak memory 226660 kb
Host smart-c7babc52-2b4a-41c8-9c9c-799c07f6b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640932308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.640932308 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.1780907338
Short name T111
Test name
Test status
Simulation time 176637679354 ps
CPU time 771.47 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:18:35 PM PDT 24
Peak memory 1025280 kb
Host smart-f9524cfc-b178-4369-82d4-0b94e95d2077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780907338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.1780907338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.3111680147
Short name T237
Test name
Test status
Simulation time 4454070261 ps
CPU time 365.6 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:11:49 PM PDT 24
Peak memory 340520 kb
Host smart-fa01bf44-9954-4346-b7ba-10bace5291d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111680147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3111680147 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.3161602409
Short name T622
Test name
Test status
Simulation time 5564744233 ps
CPU time 109.87 seconds
Started Aug 18 05:05:43 PM PDT 24
Finished Aug 18 05:07:33 PM PDT 24
Peak memory 230380 kb
Host smart-48e4bbad-5f8c-4acc-9666-8a678e3f7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161602409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.3161602409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.103432089
Short name T546
Test name
Test status
Simulation time 81329910904 ps
CPU time 3487.63 seconds
Started Aug 18 05:05:56 PM PDT 24
Finished Aug 18 06:04:04 PM PDT 24
Peak memory 1270828 kb
Host smart-18220741-3c0a-4c2a-92cf-fbb6466273cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=103432089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.103432089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2482192069
Short name T603
Test name
Test status
Simulation time 18787934 ps
CPU time 0.87 seconds
Started Aug 18 05:05:55 PM PDT 24
Finished Aug 18 05:05:56 PM PDT 24
Peak memory 218260 kb
Host smart-97a8b0ab-9eb8-4fd0-9431-78067e016604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482192069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2482192069 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.3518719017
Short name T543
Test name
Test status
Simulation time 2578736737 ps
CPU time 126.54 seconds
Started Aug 18 05:05:58 PM PDT 24
Finished Aug 18 05:08:04 PM PDT 24
Peak memory 265648 kb
Host smart-5dab0741-8c26-4ada-abe9-7ef0e44de704
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518719017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3518719017 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3055820735
Short name T144
Test name
Test status
Simulation time 34610097650 ps
CPU time 219.33 seconds
Started Aug 18 05:05:52 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 233496 kb
Host smart-eef03b5f-ea55-44b5-8758-8e7ac9ad5183
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055820735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.305582073
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.2038466079
Short name T236
Test name
Test status
Simulation time 11786777507 ps
CPU time 213.51 seconds
Started Aug 18 05:05:53 PM PDT 24
Finished Aug 18 05:09:27 PM PDT 24
Peak memory 357012 kb
Host smart-73527634-65bb-4644-9bbe-dc7e1d7d7aed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038466079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2
038466079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2023890615
Short name T515
Test name
Test status
Simulation time 5825808662 ps
CPU time 238.7 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:09:53 PM PDT 24
Peak memory 310524 kb
Host smart-f5df0dea-cb72-4fed-97fd-3a7425a919cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023890615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2023890615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.1731236174
Short name T651
Test name
Test status
Simulation time 1159309111 ps
CPU time 8.17 seconds
Started Aug 18 05:05:57 PM PDT 24
Finished Aug 18 05:06:05 PM PDT 24
Peak memory 226492 kb
Host smart-982c5aae-80bc-4408-9c44-b32a44a00733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731236174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1731236174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1831916021
Short name T241
Test name
Test status
Simulation time 41673787 ps
CPU time 1.37 seconds
Started Aug 18 05:05:57 PM PDT 24
Finished Aug 18 05:05:58 PM PDT 24
Peak memory 226664 kb
Host smart-2dad0cce-6ea9-40e6-bcc3-b3427d1ac670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831916021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1831916021 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.738570765
Short name T335
Test name
Test status
Simulation time 20866262313 ps
CPU time 2567.57 seconds
Started Aug 18 05:05:53 PM PDT 24
Finished Aug 18 05:48:41 PM PDT 24
Peak memory 1486552 kb
Host smart-dd8afd06-61e1-41e9-9db2-3d5294c65399
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738570765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_an
d_output.738570765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.3319276040
Short name T572
Test name
Test status
Simulation time 5194624475 ps
CPU time 106.1 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:07:41 PM PDT 24
Peak memory 260396 kb
Host smart-c402ca3d-c8fe-4589-aa95-8d1df4ea3f16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319276040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3319276040 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3704763140
Short name T639
Test name
Test status
Simulation time 12195965182 ps
CPU time 88.1 seconds
Started Aug 18 05:05:52 PM PDT 24
Finished Aug 18 05:07:20 PM PDT 24
Peak memory 228540 kb
Host smart-8028f2ba-0b05-4d81-9953-1eff359af8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704763140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3704763140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_alert_test.1221710088
Short name T377
Test name
Test status
Simulation time 27744189 ps
CPU time 0.9 seconds
Started Aug 18 05:05:53 PM PDT 24
Finished Aug 18 05:05:54 PM PDT 24
Peak memory 218272 kb
Host smart-92c37a3a-80a8-4096-902a-86aeb3d6f202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221710088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1221710088 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.2375569636
Short name T519
Test name
Test status
Simulation time 17905767681 ps
CPU time 280.81 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 423220 kb
Host smart-016609b7-4e48-412a-bfee-782156efe463
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375569636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2375569636 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.1579061014
Short name T316
Test name
Test status
Simulation time 1702968625 ps
CPU time 208.6 seconds
Started Aug 18 05:05:53 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 228308 kb
Host smart-da11f6ca-d1ce-4021-8f9f-553fbcfad5c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579061014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.157906101
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.3734543170
Short name T67
Test name
Test status
Simulation time 19290149598 ps
CPU time 371.98 seconds
Started Aug 18 05:05:55 PM PDT 24
Finished Aug 18 05:12:07 PM PDT 24
Peak memory 465064 kb
Host smart-8af64cef-42aa-40bd-9b0c-bf6273982a60
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734543170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3
734543170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_key_error.55357226
Short name T271
Test name
Test status
Simulation time 1658984688 ps
CPU time 12.26 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:06:07 PM PDT 24
Peak memory 218368 kb
Host smart-b1ccf58f-d7d2-4d13-b878-7c72e022cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55357226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.55357226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.4193005850
Short name T403
Test name
Test status
Simulation time 98708400 ps
CPU time 1.74 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:05:56 PM PDT 24
Peak memory 226588 kb
Host smart-4761b940-9b14-4312-9a16-4e7e6940885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193005850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4193005850 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.1247131318
Short name T627
Test name
Test status
Simulation time 46132558202 ps
CPU time 2570.93 seconds
Started Aug 18 05:05:55 PM PDT 24
Finished Aug 18 05:48:46 PM PDT 24
Peak memory 2320072 kb
Host smart-ff99dea0-c7c1-4d02-a935-99d66c5249c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247131318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.1247131318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.4178022274
Short name T464
Test name
Test status
Simulation time 10202796847 ps
CPU time 185.04 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 293328 kb
Host smart-19935496-71ac-4bf1-8430-7ea33ca0516e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178022274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.4178022274 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.2351870654
Short name T263
Test name
Test status
Simulation time 464912780 ps
CPU time 8.65 seconds
Started Aug 18 05:05:56 PM PDT 24
Finished Aug 18 05:06:04 PM PDT 24
Peak memory 226320 kb
Host smart-eec29604-cdbd-451e-9d94-273e1cc98db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351870654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2351870654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.2228772261
Short name T664
Test name
Test status
Simulation time 1770740280 ps
CPU time 103.81 seconds
Started Aug 18 05:05:53 PM PDT 24
Finished Aug 18 05:07:37 PM PDT 24
Peak memory 257096 kb
Host smart-10042c19-0cb9-4750-9375-c255bdfc41f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2228772261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2228772261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3880835715
Short name T138
Test name
Test status
Simulation time 45295431 ps
CPU time 0.86 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:06:05 PM PDT 24
Peak memory 218196 kb
Host smart-9b896f6a-cfd1-42b5-9209-b08cac4a9f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880835715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3880835715 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.225994832
Short name T109
Test name
Test status
Simulation time 10113584595 ps
CPU time 373.74 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:12:18 PM PDT 24
Peak memory 462812 kb
Host smart-77a37a61-edc5-40da-b5c2-4248e166a8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225994832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.225994832 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.1489854757
Short name T634
Test name
Test status
Simulation time 188343922561 ps
CPU time 1027.85 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:23:13 PM PDT 24
Peak memory 250816 kb
Host smart-150feba1-bc4d-4042-b583-762312e0677b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489854757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.148985475
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_error.522430742
Short name T250
Test name
Test status
Simulation time 6444973112 ps
CPU time 209.29 seconds
Started Aug 18 05:06:06 PM PDT 24
Finished Aug 18 05:09:36 PM PDT 24
Peak memory 395064 kb
Host smart-11b4ad41-d4ad-4315-b9e5-6b9019594a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522430742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.522430742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.2814174056
Short name T612
Test name
Test status
Simulation time 696662733 ps
CPU time 5.71 seconds
Started Aug 18 05:06:06 PM PDT 24
Finished Aug 18 05:06:12 PM PDT 24
Peak memory 226448 kb
Host smart-f0c5fadc-a8dd-4685-a66b-406a303bca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814174056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2814174056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.1152622500
Short name T707
Test name
Test status
Simulation time 660018074 ps
CPU time 1.48 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:06:07 PM PDT 24
Peak memory 226568 kb
Host smart-6c73e397-3c3c-452c-a4b0-c84295a62b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152622500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1152622500 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2034832926
Short name T189
Test name
Test status
Simulation time 27785678916 ps
CPU time 272.87 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:10:37 PM PDT 24
Peak memory 542872 kb
Host smart-a5e3f49e-b4a3-4c1a-832b-9b5028a0eb49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034832926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2034832926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3714743150
Short name T582
Test name
Test status
Simulation time 38576604470 ps
CPU time 252.17 seconds
Started Aug 18 05:06:08 PM PDT 24
Finished Aug 18 05:10:20 PM PDT 24
Peak memory 433536 kb
Host smart-a7ba4459-3ccd-4339-8222-d0a72704c0ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714743150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3714743150 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.3147517375
Short name T339
Test name
Test status
Simulation time 6468937311 ps
CPU time 57.49 seconds
Started Aug 18 05:05:54 PM PDT 24
Finished Aug 18 05:06:51 PM PDT 24
Peak memory 226732 kb
Host smart-ceaaf562-79b4-4129-8184-d910a6255799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147517375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3147517375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.2568101550
Short name T52
Test name
Test status
Simulation time 114774526742 ps
CPU time 916.72 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:21:21 PM PDT 24
Peak memory 685764 kb
Host smart-56a94b45-fc90-4a02-b2e8-1ffe14817aad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2568101550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2568101550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_alert_test.3875426962
Short name T257
Test name
Test status
Simulation time 14392907 ps
CPU time 0.83 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:04:01 PM PDT 24
Peak memory 218160 kb
Host smart-5e6429da-d13a-4d0d-8d8a-38838ec348a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875426962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3875426962 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.3106052897
Short name T689
Test name
Test status
Simulation time 6745033963 ps
CPU time 82.83 seconds
Started Aug 18 05:03:57 PM PDT 24
Finished Aug 18 05:05:20 PM PDT 24
Peak memory 284704 kb
Host smart-cb9e06d3-7e2e-4c56-bfe4-3af3f9f99268
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106052897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3106052897 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.1690416996
Short name T675
Test name
Test status
Simulation time 5406563103 ps
CPU time 233.77 seconds
Started Aug 18 05:03:57 PM PDT 24
Finished Aug 18 05:07:51 PM PDT 24
Peak memory 300800 kb
Host smart-accd6612-2fb7-4d56-be4c-601559cdc0e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690416996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_par
tial_data.1690416996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.1988811630
Short name T295
Test name
Test status
Simulation time 13348096438 ps
CPU time 769.96 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:16:50 PM PDT 24
Peak memory 238372 kb
Host smart-5bc7878c-1f38-4eb4-bb44-d6071ceb59ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988811630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1988811630
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.2485667283
Short name T501
Test name
Test status
Simulation time 2675639316 ps
CPU time 42.69 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:42 PM PDT 24
Peak memory 236172 kb
Host smart-38a64c16-9a3f-403d-a971-58b6a53da0d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2485667283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2485667283 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.15493549
Short name T640
Test name
Test status
Simulation time 41809815 ps
CPU time 1.08 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:03:59 PM PDT 24
Peak memory 218372 kb
Host smart-4f7fc4dd-1bef-4c94-a9be-705c569b15c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15493549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.15493549 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.4161542624
Short name T245
Test name
Test status
Simulation time 221995326395 ps
CPU time 463.26 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:11:43 PM PDT 24
Peak memory 525488 kb
Host smart-303ebffb-fcb5-4733-bbc9-0512af1838aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161542624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.41
61542624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.347146316
Short name T21
Test name
Test status
Simulation time 33502575656 ps
CPU time 461.23 seconds
Started Aug 18 05:03:57 PM PDT 24
Finished Aug 18 05:11:38 PM PDT 24
Peak memory 584640 kb
Host smart-40fdea9d-389e-4d6c-8ca4-d9829b1cc7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347146316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.347146316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.434743441
Short name T292
Test name
Test status
Simulation time 3897471644 ps
CPU time 8.28 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:08 PM PDT 24
Peak memory 218508 kb
Host smart-ceb0bfa2-8f63-4e48-9c51-fa26bfcd4dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434743441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.434743441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.2447121382
Short name T239
Test name
Test status
Simulation time 1251461511 ps
CPU time 9.77 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:04:08 PM PDT 24
Peak memory 242296 kb
Host smart-0ce100ae-6600-45e6-9904-b797eb041149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447121382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2447121382 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.3605866025
Short name T230
Test name
Test status
Simulation time 7684836543 ps
CPU time 848.7 seconds
Started Aug 18 05:03:47 PM PDT 24
Finished Aug 18 05:17:55 PM PDT 24
Peak memory 674416 kb
Host smart-8c11b1c1-43de-43ca-badd-29b9a5d8c22d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605866025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.3605866025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1310592593
Short name T340
Test name
Test status
Simulation time 4919431697 ps
CPU time 364.92 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 334904 kb
Host smart-2c7d2b94-eb23-4150-8a88-f5f5cc1cc912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310592593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1310592593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.1484085441
Short name T374
Test name
Test status
Simulation time 82744019738 ps
CPU time 362.55 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 346992 kb
Host smart-05dac165-8aa7-4d78-8ee9-f2b5e8e61c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484085441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1484085441 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3395859794
Short name T240
Test name
Test status
Simulation time 5302808024 ps
CPU time 46.75 seconds
Started Aug 18 05:03:57 PM PDT 24
Finished Aug 18 05:04:43 PM PDT 24
Peak memory 222876 kb
Host smart-1f38f985-f4dc-49bc-be32-bab4180e1695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395859794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3395859794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.3386147162
Short name T55
Test name
Test status
Simulation time 9372184308 ps
CPU time 265.26 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:08:25 PM PDT 24
Peak memory 310596 kb
Host smart-e3ea8e82-c7df-45aa-bad8-ac61a5e0d316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3386147162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3386147162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.1234339818
Short name T272
Test name
Test status
Simulation time 56149510 ps
CPU time 2.5 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 218552 kb
Host smart-e7778099-8c0a-4ca0-ab58-cfd22fdbd0a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234339818 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.1234339818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.1832475709
Short name T479
Test name
Test status
Simulation time 171293783 ps
CPU time 3.61 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:04:04 PM PDT 24
Peak memory 219516 kb
Host smart-bf8f57b9-4bb8-4de9-9030-d8130bfbe49c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832475709 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1832475709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1476219922
Short name T328
Test name
Test status
Simulation time 1165569094 ps
CPU time 41.15 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:04:39 PM PDT 24
Peak memory 225836 kb
Host smart-6231038a-0543-4bd5-8858-752d220da8a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1476219922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1476219922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.4034799303
Short name T285
Test name
Test status
Simulation time 1181898284 ps
CPU time 34.52 seconds
Started Aug 18 05:04:01 PM PDT 24
Finished Aug 18 05:04:35 PM PDT 24
Peak memory 224192 kb
Host smart-96bb851f-36b1-40e5-bb31-d0904ebd522d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4034799303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4034799303 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1178443373
Short name T430
Test name
Test status
Simulation time 47951386711 ps
CPU time 2240.14 seconds
Started Aug 18 05:04:01 PM PDT 24
Finished Aug 18 05:41:21 PM PDT 24
Peak memory 2412136 kb
Host smart-c43ba405-fd86-4cc7-b2e3-4ea0733c7198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1178443373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1178443373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.4285982087
Short name T682
Test name
Test status
Simulation time 1906338505 ps
CPU time 20.38 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:20 PM PDT 24
Peak memory 218576 kb
Host smart-df5419c2-db4f-4411-b62a-bb505ea945f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4285982087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.4285982087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.74259188
Short name T470
Test name
Test status
Simulation time 22531653167 ps
CPU time 209.93 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:07:30 PM PDT 24
Peak memory 437652 kb
Host smart-63d6eda7-9bcd-4249-a186-c702f198c107
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=74259188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.74259188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.3961137541
Short name T638
Test name
Test status
Simulation time 38454078118 ps
CPU time 488.52 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:12:08 PM PDT 24
Peak memory 360008 kb
Host smart-7f0e8542-1010-4f3e-93c2-5716ba2f28c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3961137541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3961137541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.4239207862
Short name T193
Test name
Test status
Simulation time 166795103 ps
CPU time 0.94 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:06:05 PM PDT 24
Peak memory 218280 kb
Host smart-2794ba08-a9a6-487c-a65c-405f458ca9b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239207862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.4239207862 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2787264193
Short name T288
Test name
Test status
Simulation time 27594335270 ps
CPU time 355.86 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:12:01 PM PDT 24
Peak memory 349764 kb
Host smart-a6018cd2-69be-4190-b1c3-4166182a3bdf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787264193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2787264193 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.4006776056
Short name T699
Test name
Test status
Simulation time 12907531780 ps
CPU time 297.79 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:11:03 PM PDT 24
Peak memory 235392 kb
Host smart-67677fe5-eb39-4977-9af6-72fdee4f8ccd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006776056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.400677605
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.3189010452
Short name T61
Test name
Test status
Simulation time 7816541748 ps
CPU time 282.45 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:10:48 PM PDT 24
Peak memory 315256 kb
Host smart-cde4ee9b-973a-446d-8b04-761fd8d0bc4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189010452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3
189010452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.1451521200
Short name T636
Test name
Test status
Simulation time 1177252020 ps
CPU time 31.34 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:06:37 PM PDT 24
Peak memory 255552 kb
Host smart-383960a3-47b7-4b35-86ff-ce306f4315a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451521200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1451521200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.502626804
Short name T692
Test name
Test status
Simulation time 590498555 ps
CPU time 6.56 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:06:11 PM PDT 24
Peak memory 226640 kb
Host smart-ff813b54-8fec-4666-a538-1f81a280e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502626804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.502626804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.1490328172
Short name T445
Test name
Test status
Simulation time 36957341 ps
CPU time 1.84 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:06:05 PM PDT 24
Peak memory 226652 kb
Host smart-4ca862d9-5f5d-45a1-b11e-53d990680815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490328172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1490328172 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.1841119366
Short name T354
Test name
Test status
Simulation time 75775406216 ps
CPU time 3891 seconds
Started Aug 18 05:06:06 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 3007832 kb
Host smart-7f9925c0-4a03-47e5-851f-3351b3661b67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841119366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.1841119366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3360774840
Short name T248
Test name
Test status
Simulation time 32717312320 ps
CPU time 297.64 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:11:02 PM PDT 24
Peak memory 458972 kb
Host smart-794d8d92-0042-4675-9db9-753b48c1a468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360774840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3360774840 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2385363526
Short name T357
Test name
Test status
Simulation time 4138644636 ps
CPU time 53.2 seconds
Started Aug 18 05:06:04 PM PDT 24
Finished Aug 18 05:06:58 PM PDT 24
Peak memory 223564 kb
Host smart-b7448ac6-8b5b-406e-be72-b8a3a60891aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385363526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2385363526 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.1483410231
Short name T657
Test name
Test status
Simulation time 41475770246 ps
CPU time 1867.79 seconds
Started Aug 18 05:06:05 PM PDT 24
Finished Aug 18 05:37:13 PM PDT 24
Peak memory 1160112 kb
Host smart-b01826f2-c1ec-48ee-b3f7-578d9feea2be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1483410231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1483410231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_alert_test.604256051
Short name T188
Test name
Test status
Simulation time 66963888 ps
CPU time 0.82 seconds
Started Aug 18 05:06:13 PM PDT 24
Finished Aug 18 05:06:14 PM PDT 24
Peak memory 218212 kb
Host smart-01028551-bdff-4738-bb3e-eba703e38737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604256051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.604256051 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.1996180541
Short name T402
Test name
Test status
Simulation time 62835899721 ps
CPU time 376.61 seconds
Started Aug 18 05:06:13 PM PDT 24
Finished Aug 18 05:12:29 PM PDT 24
Peak memory 511656 kb
Host smart-b6dc5219-2b3d-46c1-8659-ba34b4ea5722
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996180541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1996180541 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.3776008216
Short name T311
Test name
Test status
Simulation time 4183527388 ps
CPU time 63.82 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:07:18 PM PDT 24
Peak memory 227080 kb
Host smart-5f163096-43be-464d-b25a-a8a62a099e23
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776008216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.377600821
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2816558300
Short name T524
Test name
Test status
Simulation time 9114222550 ps
CPU time 49.59 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:07:04 PM PDT 24
Peak memory 251532 kb
Host smart-ceba6caa-c83e-4c6c-adff-b49062ab4551
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816558300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2
816558300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.130761423
Short name T567
Test name
Test status
Simulation time 175991636289 ps
CPU time 303.75 seconds
Started Aug 18 05:06:12 PM PDT 24
Finished Aug 18 05:11:16 PM PDT 24
Peak memory 462336 kb
Host smart-16b0ef7c-588e-46c2-8daa-13ce277cff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130761423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.130761423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1532854176
Short name T698
Test name
Test status
Simulation time 1492650724 ps
CPU time 10.83 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:06:25 PM PDT 24
Peak memory 226496 kb
Host smart-39af9b73-9192-4c63-848c-7c801205c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532854176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1532854176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.1602009178
Short name T350
Test name
Test status
Simulation time 81961537 ps
CPU time 1.42 seconds
Started Aug 18 05:06:16 PM PDT 24
Finished Aug 18 05:06:18 PM PDT 24
Peak memory 226624 kb
Host smart-b3d49ed9-180e-4c25-8476-7dca0e2888a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602009178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1602009178 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.1070759973
Short name T681
Test name
Test status
Simulation time 4093424199 ps
CPU time 39.95 seconds
Started Aug 18 05:06:12 PM PDT 24
Finished Aug 18 05:06:52 PM PDT 24
Peak memory 260360 kb
Host smart-e7ffbf6a-2f0b-41f1-b8d3-74a7dfa07daf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070759973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.1070759973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1654730024
Short name T429
Test name
Test status
Simulation time 222947514869 ps
CPU time 490.08 seconds
Started Aug 18 05:06:17 PM PDT 24
Finished Aug 18 05:14:27 PM PDT 24
Peak memory 590224 kb
Host smart-8a63e8f8-324d-46e8-b8cd-f91492023cb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654730024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1654730024 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3467881993
Short name T251
Test name
Test status
Simulation time 3426027233 ps
CPU time 18.98 seconds
Started Aug 18 05:06:07 PM PDT 24
Finished Aug 18 05:06:26 PM PDT 24
Peak memory 226880 kb
Host smart-3e0a5ef6-ec1c-4325-a24f-e4caa21051ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467881993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3467881993 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.938862780
Short name T53
Test name
Test status
Simulation time 45776248771 ps
CPU time 1813.44 seconds
Started Aug 18 05:06:13 PM PDT 24
Finished Aug 18 05:36:27 PM PDT 24
Peak memory 955044 kb
Host smart-d4945cae-f284-4d1e-8e0b-fda237c06503
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=938862780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.938862780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2268552588
Short name T362
Test name
Test status
Simulation time 43628023 ps
CPU time 0.82 seconds
Started Aug 18 05:06:15 PM PDT 24
Finished Aug 18 05:06:16 PM PDT 24
Peak memory 218228 kb
Host smart-d2e6ac77-bfc8-423a-8d47-582595a9abba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268552588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2268552588 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.3121462400
Short name T547
Test name
Test status
Simulation time 3652047291 ps
CPU time 97.03 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:07:51 PM PDT 24
Peak memory 253340 kb
Host smart-78b78c1d-2980-4141-a120-5b228a113104
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121462400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3121462400 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.2160576743
Short name T302
Test name
Test status
Simulation time 20108589537 ps
CPU time 537.49 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:15:12 PM PDT 24
Peak memory 243160 kb
Host smart-660d992c-d942-47b0-80a0-b65b6b4d5f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160576743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.216057674
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.1653418369
Short name T619
Test name
Test status
Simulation time 7841395930 ps
CPU time 164.96 seconds
Started Aug 18 05:06:12 PM PDT 24
Finished Aug 18 05:08:57 PM PDT 24
Peak memory 345520 kb
Host smart-7db9a9c7-733d-4070-9c41-152486a83ded
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653418369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1
653418369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.2120759355
Short name T253
Test name
Test status
Simulation time 83240424855 ps
CPU time 147.71 seconds
Started Aug 18 05:06:16 PM PDT 24
Finished Aug 18 05:08:44 PM PDT 24
Peak memory 324932 kb
Host smart-5a7658e0-58fa-4ff3-a303-9ceb0de61b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120759355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2120759355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.3531082459
Short name T234
Test name
Test status
Simulation time 929222146 ps
CPU time 6.59 seconds
Started Aug 18 05:06:12 PM PDT 24
Finished Aug 18 05:06:19 PM PDT 24
Peak memory 226468 kb
Host smart-592feeeb-8102-48b8-ab9f-70d022988f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531082459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.3531082459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.3886792988
Short name T444
Test name
Test status
Simulation time 69822495 ps
CPU time 1.36 seconds
Started Aug 18 05:06:17 PM PDT 24
Finished Aug 18 05:06:18 PM PDT 24
Peak memory 226680 kb
Host smart-88fe968a-ed9a-42a8-895c-5303fa6c9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886792988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3886792988 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.1794580658
Short name T508
Test name
Test status
Simulation time 25621586890 ps
CPU time 805.31 seconds
Started Aug 18 05:06:15 PM PDT 24
Finished Aug 18 05:19:40 PM PDT 24
Peak memory 618052 kb
Host smart-c22e356d-f9f7-4c1d-8564-5c272315f3d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794580658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.1794580658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.2033218023
Short name T588
Test name
Test status
Simulation time 863613433 ps
CPU time 8.27 seconds
Started Aug 18 05:06:14 PM PDT 24
Finished Aug 18 05:06:22 PM PDT 24
Peak memory 226604 kb
Host smart-45c5d8fc-3334-49e8-9a4f-01949de43341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033218023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2033218023 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.155945131
Short name T211
Test name
Test status
Simulation time 9544440238 ps
CPU time 72.06 seconds
Started Aug 18 05:06:12 PM PDT 24
Finished Aug 18 05:07:24 PM PDT 24
Peak memory 226800 kb
Host smart-7eae4c3b-15ce-441b-b12f-1d975515b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155945131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.155945131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3416602482
Short name T69
Test name
Test status
Simulation time 83016484430 ps
CPU time 1407.69 seconds
Started Aug 18 05:06:15 PM PDT 24
Finished Aug 18 05:29:43 PM PDT 24
Peak memory 842184 kb
Host smart-aad40ea0-017a-49e6-bf86-fd6e5bf50ea0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3416602482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3416602482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3561091454
Short name T419
Test name
Test status
Simulation time 243019190 ps
CPU time 0.86 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:06:24 PM PDT 24
Peak memory 218264 kb
Host smart-86fd83d5-472a-49e3-bc38-e26392bdc304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561091454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3561091454 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.604764014
Short name T660
Test name
Test status
Simulation time 72696391458 ps
CPU time 158.42 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 334856 kb
Host smart-b6540701-5c94-4647-8e7f-3021e8a03dd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604764014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.604764014 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.4007645719
Short name T298
Test name
Test status
Simulation time 22358454606 ps
CPU time 502.16 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:14:45 PM PDT 24
Peak memory 241856 kb
Host smart-1e136e98-db34-48bd-960a-b42ecb643a65
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007645719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.400764571
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.2273309710
Short name T380
Test name
Test status
Simulation time 1096904389 ps
CPU time 30.02 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:06:53 PM PDT 24
Peak memory 229844 kb
Host smart-b3563e1e-d245-49df-b4c4-84b17b1b2376
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273309710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2
273309710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.773759581
Short name T460
Test name
Test status
Simulation time 16563868360 ps
CPU time 265.3 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:10:47 PM PDT 24
Peak memory 316840 kb
Host smart-f48a5789-b6b8-4db4-ba45-8d2f6a8ac536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773759581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.773759581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.2218042654
Short name T531
Test name
Test status
Simulation time 5646118779 ps
CPU time 10.36 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:06:33 PM PDT 24
Peak memory 226696 kb
Host smart-7f060a8f-6474-4221-96c1-002a22bf05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218042654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2218042654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.2616151793
Short name T58
Test name
Test status
Simulation time 115549554 ps
CPU time 1.22 seconds
Started Aug 18 05:06:29 PM PDT 24
Finished Aug 18 05:06:31 PM PDT 24
Peak memory 226680 kb
Host smart-6fe976c3-c8ea-47fc-9816-89e9366eb3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616151793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2616151793 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2444433777
Short name T226
Test name
Test status
Simulation time 61094744547 ps
CPU time 2680.05 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 2333460 kb
Host smart-3e28a9ab-0e7e-4f50-a75b-c085fbb7afb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444433777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2444433777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1861048602
Short name T198
Test name
Test status
Simulation time 59163007898 ps
CPU time 553.34 seconds
Started Aug 18 05:06:28 PM PDT 24
Finished Aug 18 05:15:42 PM PDT 24
Peak memory 632640 kb
Host smart-7593b8aa-328d-4f3f-adc9-6588a6016865
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861048602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1861048602 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.2504218778
Short name T490
Test name
Test status
Simulation time 33096193732 ps
CPU time 78.04 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:07:41 PM PDT 24
Peak memory 226800 kb
Host smart-54d1c131-bff6-48c1-961b-2b68b631d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504218778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2504218778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.1095578554
Short name T54
Test name
Test status
Simulation time 16161602003 ps
CPU time 1372.99 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:29:15 PM PDT 24
Peak memory 336632 kb
Host smart-338e336c-70e3-4670-b876-faef48aa94e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1095578554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1095578554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_alert_test.2656806162
Short name T417
Test name
Test status
Simulation time 42702209 ps
CPU time 0.82 seconds
Started Aug 18 05:06:29 PM PDT 24
Finished Aug 18 05:06:30 PM PDT 24
Peak memory 218208 kb
Host smart-039840c4-791b-4a61-9f6c-1a6e5994ff48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656806162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2656806162 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.638404022
Short name T358
Test name
Test status
Simulation time 14229768787 ps
CPU time 404.76 seconds
Started Aug 18 05:06:28 PM PDT 24
Finished Aug 18 05:13:13 PM PDT 24
Peak memory 502124 kb
Host smart-8bf3ecfc-4ecf-4e99-be13-f7490a2c5d80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638404022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.638404022 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.712478700
Short name T701
Test name
Test status
Simulation time 14682729205 ps
CPU time 632.37 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:16:55 PM PDT 24
Peak memory 244772 kb
Host smart-6255405f-d087-4066-b0aa-d9d68c311f2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712478700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.712478700
+enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2918242649
Short name T231
Test name
Test status
Simulation time 26527841598 ps
CPU time 179.62 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 350788 kb
Host smart-3eb99b10-c905-46dd-a719-2b2225174612
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918242649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2
918242649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.3704459728
Short name T20
Test name
Test status
Simulation time 2778574173 ps
CPU time 68.4 seconds
Started Aug 18 05:06:24 PM PDT 24
Finished Aug 18 05:07:33 PM PDT 24
Peak memory 299196 kb
Host smart-93f2f580-78fa-4939-b573-18868aff34aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704459728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3704459728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2845274091
Short name T235
Test name
Test status
Simulation time 3686760875 ps
CPU time 7.61 seconds
Started Aug 18 05:06:22 PM PDT 24
Finished Aug 18 05:06:30 PM PDT 24
Peak memory 226628 kb
Host smart-4a845d88-2aec-41f0-ab26-1d4f6b8da3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845274091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2845274091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.1660979863
Short name T46
Test name
Test status
Simulation time 33517709 ps
CPU time 1.43 seconds
Started Aug 18 05:06:27 PM PDT 24
Finished Aug 18 05:06:29 PM PDT 24
Peak memory 226544 kb
Host smart-ea71b41f-5fba-4ff1-af30-d64759466ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660979863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1660979863 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.4104832595
Short name T204
Test name
Test status
Simulation time 170669044995 ps
CPU time 2272.97 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:44:17 PM PDT 24
Peak memory 2198616 kb
Host smart-32f26024-50d5-4c23-99eb-d6c076803972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104832595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.4104832595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.3337380553
Short name T712
Test name
Test status
Simulation time 81680144759 ps
CPU time 375.92 seconds
Started Aug 18 05:06:21 PM PDT 24
Finished Aug 18 05:12:37 PM PDT 24
Peak memory 505776 kb
Host smart-fdcbdb65-3042-4e37-8a8b-584901080e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337380553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3337380553 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2469544814
Short name T389
Test name
Test status
Simulation time 1409518606 ps
CPU time 44.73 seconds
Started Aug 18 05:06:23 PM PDT 24
Finished Aug 18 05:07:08 PM PDT 24
Peak memory 226608 kb
Host smart-e92ebd3e-9bcd-4c9f-b34b-400ba60824b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469544814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2469544814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.416492700
Short name T563
Test name
Test status
Simulation time 358511790029 ps
CPU time 3160.14 seconds
Started Aug 18 05:06:21 PM PDT 24
Finished Aug 18 05:59:01 PM PDT 24
Peak memory 1954716 kb
Host smart-abb53a6c-0c1a-4e86-b4d9-2135a66a10cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=416492700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.416492700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_alert_test.3865329116
Short name T580
Test name
Test status
Simulation time 13938378 ps
CPU time 0.83 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:06:34 PM PDT 24
Peak memory 218264 kb
Host smart-2d80f446-6e33-4481-9bf4-670c7078dd46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865329116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3865329116 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.2858955739
Short name T670
Test name
Test status
Simulation time 80139350921 ps
CPU time 504.16 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:14:59 PM PDT 24
Peak memory 590700 kb
Host smart-41f83dba-e970-4465-b707-c4fdfc44d254
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858955739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2858955739 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.2116418394
Short name T521
Test name
Test status
Simulation time 9504908009 ps
CPU time 951.56 seconds
Started Aug 18 05:06:32 PM PDT 24
Finished Aug 18 05:22:24 PM PDT 24
Peak memory 242412 kb
Host smart-4714f19b-ba24-40d3-9a9d-0ab40a858ee3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116418394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.211641839
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.615924291
Short name T113
Test name
Test status
Simulation time 204648630190 ps
CPU time 485.9 seconds
Started Aug 18 05:06:32 PM PDT 24
Finished Aug 18 05:14:38 PM PDT 24
Peak memory 535308 kb
Host smart-8cba3bef-e0cb-478f-bcbf-5ab96c2bbd39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615924291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.61
5924291 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.385982287
Short name T581
Test name
Test status
Simulation time 3966142344 ps
CPU time 328.71 seconds
Started Aug 18 05:06:34 PM PDT 24
Finished Aug 18 05:12:03 PM PDT 24
Peak memory 339380 kb
Host smart-a87de544-3137-4724-9d3d-3988742f2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385982287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.385982287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.3012674656
Short name T398
Test name
Test status
Simulation time 1990663805 ps
CPU time 4.96 seconds
Started Aug 18 05:06:34 PM PDT 24
Finished Aug 18 05:06:39 PM PDT 24
Peak memory 226524 kb
Host smart-cfbda0ed-c438-442a-b9e3-936bd0b05063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012674656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3012674656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2144142135
Short name T617
Test name
Test status
Simulation time 43711705 ps
CPU time 1.64 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:06:35 PM PDT 24
Peak memory 226620 kb
Host smart-56c57ea0-2466-4e55-8f68-9e55aa6ce77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144142135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2144142135 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.41227174
Short name T540
Test name
Test status
Simulation time 25964806253 ps
CPU time 3456.58 seconds
Started Aug 18 05:06:24 PM PDT 24
Finished Aug 18 06:04:01 PM PDT 24
Peak memory 1759816 kb
Host smart-8c3da544-4537-4714-a17e-7c37f30406b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41227174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and
_output.41227174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.3425577595
Short name T182
Test name
Test status
Simulation time 64583651543 ps
CPU time 581.93 seconds
Started Aug 18 05:06:32 PM PDT 24
Finished Aug 18 05:16:14 PM PDT 24
Peak memory 625104 kb
Host smart-421ef992-9e69-425b-9196-b322aeb919fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425577595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.3425577595 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.772594216
Short name T637
Test name
Test status
Simulation time 3062499899 ps
CPU time 20.66 seconds
Started Aug 18 05:06:28 PM PDT 24
Finished Aug 18 05:06:49 PM PDT 24
Peak memory 226700 kb
Host smart-ffe5ec31-5b22-4298-9bf2-95b04c92ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772594216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.772594216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.3215082379
Short name T310
Test name
Test status
Simulation time 80730481250 ps
CPU time 490.86 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:14:46 PM PDT 24
Peak memory 459460 kb
Host smart-d710ac61-8d17-4cbe-82d8-f41814a9c716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3215082379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3215082379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3424790879
Short name T372
Test name
Test status
Simulation time 42814017 ps
CPU time 0.78 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:06:34 PM PDT 24
Peak memory 218068 kb
Host smart-892ba66e-8756-408b-9509-ff5493b9b746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424790879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3424790879 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.1194842885
Short name T246
Test name
Test status
Simulation time 3599518701 ps
CPU time 74.45 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:07:48 PM PDT 24
Peak memory 270452 kb
Host smart-03cb6779-d840-431c-bcb2-c7d87d6a3863
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194842885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1194842885 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.172246802
Short name T641
Test name
Test status
Simulation time 6306844386 ps
CPU time 766.23 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:19:20 PM PDT 24
Peak memory 237936 kb
Host smart-b6a90c84-9b84-45f9-8d7f-e8da7183b07e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172246802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.172246802
+enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.3472242231
Short name T440
Test name
Test status
Simulation time 12116559411 ps
CPU time 217.19 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:10:12 PM PDT 24
Peak memory 390948 kb
Host smart-c9a43aac-3688-4bfd-9720-948ca44008fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472242231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3
472242231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.2880316500
Short name T432
Test name
Test status
Simulation time 48986485586 ps
CPU time 467.99 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:14:21 PM PDT 24
Peak memory 572864 kb
Host smart-cab31446-9f26-45a9-ae38-6d0b9783ea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880316500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2880316500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.2200119948
Short name T476
Test name
Test status
Simulation time 179528817 ps
CPU time 1.93 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:06:37 PM PDT 24
Peak memory 226400 kb
Host smart-1178d27c-ee66-48ba-92ed-6e91a835ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200119948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2200119948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.1856612150
Short name T41
Test name
Test status
Simulation time 53385942 ps
CPU time 1.53 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:06:36 PM PDT 24
Peak memory 226652 kb
Host smart-d7430506-9435-4fd5-9ab9-2a01d77c7907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856612150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1856612150 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.422247795
Short name T583
Test name
Test status
Simulation time 16962507086 ps
CPU time 2124.67 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:41:58 PM PDT 24
Peak memory 1184728 kb
Host smart-e5750e1e-b6d1-479b-bb86-f0a1e8e22061
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422247795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an
d_output.422247795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.968075984
Short name T406
Test name
Test status
Simulation time 8314055902 ps
CPU time 262.86 seconds
Started Aug 18 05:06:35 PM PDT 24
Finished Aug 18 05:10:58 PM PDT 24
Peak memory 433588 kb
Host smart-62830674-2e81-44cb-9c14-75a7636b683f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968075984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.968075984 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.518114678
Short name T452
Test name
Test status
Simulation time 4295363638 ps
CPU time 46.51 seconds
Started Aug 18 05:06:32 PM PDT 24
Finished Aug 18 05:07:19 PM PDT 24
Peak memory 226716 kb
Host smart-88f9345e-cd8e-4f3b-9202-5846e273079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518114678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.518114678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.2262684043
Short name T313
Test name
Test status
Simulation time 101026898258 ps
CPU time 3328.07 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 06:02:01 PM PDT 24
Peak memory 1552408 kb
Host smart-5cc91513-fc2f-4372-8add-dc4995a865bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2262684043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2262684043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2800341796
Short name T320
Test name
Test status
Simulation time 105096734 ps
CPU time 0.79 seconds
Started Aug 18 05:06:44 PM PDT 24
Finished Aug 18 05:06:45 PM PDT 24
Peak memory 218196 kb
Host smart-27fbb2ec-8f17-486a-957d-0cfe18566118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800341796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2800341796 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.3169877905
Short name T307
Test name
Test status
Simulation time 48354833066 ps
CPU time 360.67 seconds
Started Aug 18 05:06:48 PM PDT 24
Finished Aug 18 05:12:48 PM PDT 24
Peak memory 334696 kb
Host smart-e089acf2-6e72-4024-ae13-59da7d82a409
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169877905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.3169877905 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.104197707
Short name T261
Test name
Test status
Simulation time 4135291094 ps
CPU time 168.72 seconds
Started Aug 18 05:06:45 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 238748 kb
Host smart-143b53d4-5d31-4387-bea3-0d2eab6440d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104197707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.104197707
+enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2730955085
Short name T462
Test name
Test status
Simulation time 1304237516 ps
CPU time 61.19 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:07:44 PM PDT 24
Peak memory 242404 kb
Host smart-979c9998-7fb8-4eb7-bbc7-cd5492751ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730955085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2
730955085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.1707787880
Short name T422
Test name
Test status
Simulation time 12426571726 ps
CPU time 442.04 seconds
Started Aug 18 05:06:47 PM PDT 24
Finished Aug 18 05:14:09 PM PDT 24
Peak memory 564980 kb
Host smart-e44ff7c7-2ddc-4e18-82e0-4130c0e39b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707787880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1707787880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1268625942
Short name T223
Test name
Test status
Simulation time 7533596452 ps
CPU time 10.47 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:06:54 PM PDT 24
Peak memory 226552 kb
Host smart-004ad271-5ab3-453a-8ad0-7946ab27856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268625942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1268625942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.2874801695
Short name T666
Test name
Test status
Simulation time 647880633 ps
CPU time 1.64 seconds
Started Aug 18 05:06:44 PM PDT 24
Finished Aug 18 05:06:46 PM PDT 24
Peak memory 226528 kb
Host smart-ad0c9d52-45b9-4bec-97c7-dd208085c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874801695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2874801695 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.4080564053
Short name T578
Test name
Test status
Simulation time 157438530066 ps
CPU time 1285.41 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:28:09 PM PDT 24
Peak memory 1491020 kb
Host smart-de90f57c-d6dc-49b8-b061-9ddfc6591850
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080564053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.4080564053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.1528521685
Short name T671
Test name
Test status
Simulation time 1484670546 ps
CPU time 23.82 seconds
Started Aug 18 05:06:42 PM PDT 24
Finished Aug 18 05:07:06 PM PDT 24
Peak memory 229568 kb
Host smart-43ae3483-38be-446c-9517-dd0256d260f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528521685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1528521685 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.2201797387
Short name T579
Test name
Test status
Simulation time 12445523606 ps
CPU time 39.4 seconds
Started Aug 18 05:06:33 PM PDT 24
Finished Aug 18 05:07:13 PM PDT 24
Peak memory 226844 kb
Host smart-037a541b-bf45-4d1d-b58e-9b1bb127cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201797387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.2201797387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.3042463446
Short name T68
Test name
Test status
Simulation time 112831946445 ps
CPU time 905.25 seconds
Started Aug 18 05:06:45 PM PDT 24
Finished Aug 18 05:21:51 PM PDT 24
Peak memory 470968 kb
Host smart-1dc5d4a1-6c46-4c05-8872-07c43bbf182f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3042463446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3042463446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_alert_test.4034706505
Short name T201
Test name
Test status
Simulation time 107726368 ps
CPU time 0.75 seconds
Started Aug 18 05:06:42 PM PDT 24
Finished Aug 18 05:06:43 PM PDT 24
Peak memory 218204 kb
Host smart-3450dd50-7690-4d9c-a6c2-f33a44a4a868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034706505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.4034706505 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.3244924426
Short name T594
Test name
Test status
Simulation time 14591436107 ps
CPU time 353.19 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:12:36 PM PDT 24
Peak memory 450656 kb
Host smart-77ede98c-813f-4002-b6c6-49f9187d8d06
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244924426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3244924426 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2204468755
Short name T575
Test name
Test status
Simulation time 275366897 ps
CPU time 15.34 seconds
Started Aug 18 05:06:45 PM PDT 24
Finished Aug 18 05:07:01 PM PDT 24
Peak memory 224184 kb
Host smart-7ff0534e-cbe2-4012-bfd2-7ebb0d20cc76
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204468755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.220446875
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3962946136
Short name T706
Test name
Test status
Simulation time 10818794043 ps
CPU time 85.86 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:08:09 PM PDT 24
Peak memory 291808 kb
Host smart-b642d510-344b-4d94-9850-e5a43654ea11
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962946136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3
962946136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.3839406499
Short name T415
Test name
Test status
Simulation time 18325663195 ps
CPU time 160.92 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:09:24 PM PDT 24
Peak memory 345704 kb
Host smart-2c5ed04f-ec49-4c24-ad44-39b4db1b764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839406499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3839406499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.3760208979
Short name T229
Test name
Test status
Simulation time 1149141811 ps
CPU time 8.47 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:06:52 PM PDT 24
Peak memory 226616 kb
Host smart-6c487e18-9bc7-4014-9802-3d8c45536bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760208979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3760208979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.711696250
Short name T57
Test name
Test status
Simulation time 98463909 ps
CPU time 1.32 seconds
Started Aug 18 05:06:44 PM PDT 24
Finished Aug 18 05:06:46 PM PDT 24
Peak memory 226724 kb
Host smart-5c1c0c3f-0d94-406b-ab4b-d3b1ef572739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711696250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.711696250 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3223092157
Short name T552
Test name
Test status
Simulation time 72399546742 ps
CPU time 2174.66 seconds
Started Aug 18 05:06:48 PM PDT 24
Finished Aug 18 05:43:03 PM PDT 24
Peak memory 1235036 kb
Host smart-0cd983fa-7465-415d-a8f0-109c1773ec2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223092157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3223092157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.2754090152
Short name T577
Test name
Test status
Simulation time 23403979773 ps
CPU time 254.94 seconds
Started Aug 18 05:06:43 PM PDT 24
Finished Aug 18 05:10:58 PM PDT 24
Peak memory 423952 kb
Host smart-523a53cd-872c-42b9-a6c5-778c457cdbf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754090152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2754090152 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.2096375310
Short name T615
Test name
Test status
Simulation time 6290695018 ps
CPU time 38.42 seconds
Started Aug 18 05:06:46 PM PDT 24
Finished Aug 18 05:07:24 PM PDT 24
Peak memory 226808 kb
Host smart-d0b1a77b-6bb2-4ebb-88eb-4f4a305dcb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096375310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2096375310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.3775802733
Short name T215
Test name
Test status
Simulation time 30071955570 ps
CPU time 849.75 seconds
Started Aug 18 05:06:41 PM PDT 24
Finished Aug 18 05:20:51 PM PDT 24
Peak memory 654956 kb
Host smart-c3fb5dab-a195-4652-ab3a-31771f0e74b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3775802733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3775802733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_alert_test.512829686
Short name T562
Test name
Test status
Simulation time 28163276 ps
CPU time 0.89 seconds
Started Aug 18 05:06:54 PM PDT 24
Finished Aug 18 05:06:55 PM PDT 24
Peak memory 218196 kb
Host smart-8b461258-68fb-439e-8341-359bd0f37f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512829686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.512829686 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3757756886
Short name T299
Test name
Test status
Simulation time 9259318303 ps
CPU time 142.32 seconds
Started Aug 18 05:06:53 PM PDT 24
Finished Aug 18 05:09:15 PM PDT 24
Peak memory 320088 kb
Host smart-a7a178f5-9039-42be-b190-5eb71296a252
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757756886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3757756886 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.716830909
Short name T453
Test name
Test status
Simulation time 68304888044 ps
CPU time 864.32 seconds
Started Aug 18 05:06:54 PM PDT 24
Finished Aug 18 05:21:18 PM PDT 24
Peak memory 251144 kb
Host smart-5c3f3c7b-43d0-48be-9080-f894299ae870
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716830909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.716830909
+enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.3041840580
Short name T183
Test name
Test status
Simulation time 21946969365 ps
CPU time 169.15 seconds
Started Aug 18 05:06:58 PM PDT 24
Finished Aug 18 05:09:47 PM PDT 24
Peak memory 345720 kb
Host smart-bb14de7c-cc7f-4ea2-b959-888fb9508944
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041840580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.3
041840580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.3063305519
Short name T317
Test name
Test status
Simulation time 11172167098 ps
CPU time 225.22 seconds
Started Aug 18 05:06:58 PM PDT 24
Finished Aug 18 05:10:43 PM PDT 24
Peak memory 404436 kb
Host smart-f07004be-2288-4660-8853-af82c14ed4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063305519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3063305519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3942600411
Short name T300
Test name
Test status
Simulation time 512358376 ps
CPU time 4.27 seconds
Started Aug 18 05:06:52 PM PDT 24
Finished Aug 18 05:06:56 PM PDT 24
Peak memory 226472 kb
Host smart-a82b262d-ef44-425c-8743-0292b3ebf141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942600411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3942600411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1077787700
Short name T49
Test name
Test status
Simulation time 142159880 ps
CPU time 1.6 seconds
Started Aug 18 05:06:52 PM PDT 24
Finished Aug 18 05:06:54 PM PDT 24
Peak memory 226644 kb
Host smart-da255f29-1e13-4278-a329-444f85e4be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077787700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1077787700 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.3776485625
Short name T185
Test name
Test status
Simulation time 36947848211 ps
CPU time 2201.34 seconds
Started Aug 18 05:06:48 PM PDT 24
Finished Aug 18 05:43:30 PM PDT 24
Peak memory 1289204 kb
Host smart-79f73159-9ea7-41d9-95f1-8284f6ab9366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776485625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.3776485625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1072844250
Short name T499
Test name
Test status
Simulation time 12825723061 ps
CPU time 232.31 seconds
Started Aug 18 05:06:54 PM PDT 24
Finished Aug 18 05:10:46 PM PDT 24
Peak memory 388496 kb
Host smart-c91f6e9d-e52a-4494-b5a2-92cb5f24d9b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072844250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1072844250 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.2622092001
Short name T213
Test name
Test status
Simulation time 4079413983 ps
CPU time 27.88 seconds
Started Aug 18 05:06:45 PM PDT 24
Finished Aug 18 05:07:13 PM PDT 24
Peak memory 226900 kb
Host smart-88887321-a2c4-4647-9c65-e34624aa6766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622092001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2622092001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.536849587
Short name T410
Test name
Test status
Simulation time 216349275351 ps
CPU time 1574.9 seconds
Started Aug 18 05:06:54 PM PDT 24
Finished Aug 18 05:33:09 PM PDT 24
Peak memory 929456 kb
Host smart-88fa66b7-51cc-4b8f-9e68-23af8fc50b78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=536849587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.536849587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_alert_test.483656209
Short name T589
Test name
Test status
Simulation time 17323998 ps
CPU time 0.84 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:04:11 PM PDT 24
Peak memory 218260 kb
Host smart-77f41fff-9a62-44e1-89aa-afa456204ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483656209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.483656209 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.2078321507
Short name T208
Test name
Test status
Simulation time 10843474787 ps
CPU time 299.57 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:08:59 PM PDT 24
Peak memory 427388 kb
Host smart-2a7c2477-e182-4a4d-8b11-8a2e59b18666
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078321507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2078321507 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1424297174
Short name T436
Test name
Test status
Simulation time 93975679196 ps
CPU time 232.23 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:08:03 PM PDT 24
Peak memory 379916 kb
Host smart-eb803835-64b8-4bc1-8503-e8e79233c044
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424297174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_par
tial_data.1424297174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.480047902
Short name T391
Test name
Test status
Simulation time 23721517199 ps
CPU time 639.63 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:14:40 PM PDT 24
Peak memory 236616 kb
Host smart-205468c2-3df8-4e02-8639-f32a23035438
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480047902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.480047902 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.4119091495
Short name T686
Test name
Test status
Simulation time 124675774 ps
CPU time 1 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:04:11 PM PDT 24
Peak memory 221608 kb
Host smart-bcc7e250-6bda-4519-a842-59456a659eda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119091495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.4119091495 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.3229490827
Short name T12
Test name
Test status
Simulation time 5169268560 ps
CPU time 51.8 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:05:06 PM PDT 24
Peak memory 223820 kb
Host smart-121e852a-0189-4c31-9e91-6125db037dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229490827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3229490827 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.3840032422
Short name T608
Test name
Test status
Simulation time 2075428407 ps
CPU time 48.58 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:05:00 PM PDT 24
Peak memory 258820 kb
Host smart-89b59b06-28fc-4d92-94f6-fc097e4fc027
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840032422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.38
40032422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_key_error.3055216457
Short name T106
Test name
Test status
Simulation time 1572233219 ps
CPU time 8.24 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:04:18 PM PDT 24
Peak memory 226420 kb
Host smart-b8dcbdc0-a78c-45e1-96ba-8102ca3878f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055216457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3055216457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.2080157043
Short name T40
Test name
Test status
Simulation time 3245627349 ps
CPU time 26.68 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:04:39 PM PDT 24
Peak memory 242448 kb
Host smart-9b1e894e-6ded-41cf-85b2-a1b465a560cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080157043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2080157043 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.3042374940
Short name T363
Test name
Test status
Simulation time 198921151650 ps
CPU time 2811.03 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 2552484 kb
Host smart-398b02b2-c3d5-4e3d-a4d1-2a27329473b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042374940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.3042374940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.2077562732
Short name T650
Test name
Test status
Simulation time 11242179311 ps
CPU time 281.02 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 445816 kb
Host smart-f7b3ab34-5c0b-4cc9-a45b-8e9cf1c68b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077562732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2077562732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2002003487
Short name T79
Test name
Test status
Simulation time 3525541924 ps
CPU time 46.64 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:04:58 PM PDT 24
Peak memory 264428 kb
Host smart-c3b79ac4-726d-4ccb-ad53-4f92cebee466
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002003487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2002003487 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.763536798
Short name T323
Test name
Test status
Simulation time 7508238817 ps
CPU time 154.64 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:06:33 PM PDT 24
Peak memory 273212 kb
Host smart-2f54948e-8d01-4f5e-9819-e5be1ad74250
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763536798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.763536798 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.2162972596
Short name T334
Test name
Test status
Simulation time 12298798639 ps
CPU time 100.87 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:05:41 PM PDT 24
Peak memory 229744 kb
Host smart-516b2a9d-425d-41c7-840d-45750792df1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162972596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2162972596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1356790369
Short name T704
Test name
Test status
Simulation time 82932228704 ps
CPU time 2246.49 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:41:40 PM PDT 24
Peak memory 872396 kb
Host smart-15c67091-6666-4011-b514-014a7bf2e942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1356790369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1356790369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3889596081
Short name T450
Test name
Test status
Simulation time 275304295 ps
CPU time 3.01 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 219444 kb
Host smart-1252bd38-2284-4ef1-9b87-eb855141c9f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889596081 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3889596081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3488810388
Short name T196
Test name
Test status
Simulation time 110612323 ps
CPU time 2.54 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:04:01 PM PDT 24
Peak memory 219668 kb
Host smart-f1930ed4-7f96-4cb7-b2ad-9d1399645960
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488810388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3488810388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.3148445665
Short name T457
Test name
Test status
Simulation time 2061965286 ps
CPU time 45.17 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:04:43 PM PDT 24
Peak memory 252048 kb
Host smart-e6306cf9-a67e-41e8-8dae-b7e01a51fbd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3148445665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3148445665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.143548793
Short name T270
Test name
Test status
Simulation time 1090935433 ps
CPU time 35.22 seconds
Started Aug 18 05:03:58 PM PDT 24
Finished Aug 18 05:04:33 PM PDT 24
Peak memory 223908 kb
Host smart-27e14894-ab8b-430f-99da-87e9c0f41a0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=143548793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.143548793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2963612809
Short name T507
Test name
Test status
Simulation time 6972217115 ps
CPU time 29.26 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:04:28 PM PDT 24
Peak memory 234508 kb
Host smart-90aec389-2e64-49eb-b696-01367c8ff738
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2963612809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2963612809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3811732524
Short name T336
Test name
Test status
Simulation time 18498039905 ps
CPU time 1199.06 seconds
Started Aug 18 05:03:59 PM PDT 24
Finished Aug 18 05:23:58 PM PDT 24
Peak memory 678292 kb
Host smart-8b709cdd-30b5-47b7-81f2-2cd2ccd035ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3811732524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3811732524 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1553165856
Short name T187
Test name
Test status
Simulation time 209849940618 ps
CPU time 4409.7 seconds
Started Aug 18 05:03:57 PM PDT 24
Finished Aug 18 06:17:28 PM PDT 24
Peak memory 3561524 kb
Host smart-baaa5fa5-08a0-46d1-8cab-45c95da9c5e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1553165856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1553165856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.2052520300
Short name T443
Test name
Test status
Simulation time 12028456802 ps
CPU time 418.9 seconds
Started Aug 18 05:04:00 PM PDT 24
Finished Aug 18 05:10:59 PM PDT 24
Peak memory 263572 kb
Host smart-245eb1a9-8404-47fa-8d9e-75c178b313b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2052520300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2052520300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.4048448175
Short name T661
Test name
Test status
Simulation time 45615551 ps
CPU time 0.81 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:07:05 PM PDT 24
Peak memory 218148 kb
Host smart-1296fba9-903e-403b-b19c-979c194e2823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048448175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.4048448175 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3193328531
Short name T135
Test name
Test status
Simulation time 17189562855 ps
CPU time 421.44 seconds
Started Aug 18 05:07:00 PM PDT 24
Finished Aug 18 05:14:02 PM PDT 24
Peak memory 529228 kb
Host smart-ba04b797-ebf1-4d7b-b320-8e718a917927
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193328531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3193328531 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.4240941004
Short name T214
Test name
Test status
Simulation time 134819040794 ps
CPU time 1225.24 seconds
Started Aug 18 05:07:01 PM PDT 24
Finished Aug 18 05:27:26 PM PDT 24
Peak memory 258580 kb
Host smart-731823e8-a537-4895-8e5e-ff58f097a9c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240941004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.424094100
4 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.2550264168
Short name T301
Test name
Test status
Simulation time 4559570894 ps
CPU time 146.39 seconds
Started Aug 18 05:06:53 PM PDT 24
Finished Aug 18 05:09:20 PM PDT 24
Peak memory 273912 kb
Host smart-203fd0b8-8384-405b-99fa-9d22b7fdab64
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550264168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2
550264168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1581553485
Short name T631
Test name
Test status
Simulation time 17615318331 ps
CPU time 168.9 seconds
Started Aug 18 05:07:00 PM PDT 24
Finished Aug 18 05:09:48 PM PDT 24
Peak memory 373048 kb
Host smart-119c9d97-9eaf-412f-81f9-83996d4ddf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581553485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1581553485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.877802261
Short name T107
Test name
Test status
Simulation time 1077449651 ps
CPU time 8.52 seconds
Started Aug 18 05:07:00 PM PDT 24
Finished Aug 18 05:07:09 PM PDT 24
Peak memory 226424 kb
Host smart-18717cd3-0893-4914-a891-0d436d4f9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877802261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.877802261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.2910800003
Short name T284
Test name
Test status
Simulation time 34295638 ps
CPU time 1.19 seconds
Started Aug 18 05:07:01 PM PDT 24
Finished Aug 18 05:07:02 PM PDT 24
Peak memory 226568 kb
Host smart-ee751743-eb8d-4e68-8544-612c4b48ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910800003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2910800003 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.126659010
Short name T242
Test name
Test status
Simulation time 446332836028 ps
CPU time 5131.58 seconds
Started Aug 18 05:06:52 PM PDT 24
Finished Aug 18 06:32:25 PM PDT 24
Peak memory 3751884 kb
Host smart-4c694d0c-91d0-4500-b552-09dd92bde50a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126659010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.126659010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.3310025432
Short name T342
Test name
Test status
Simulation time 3712424937 ps
CPU time 188.61 seconds
Started Aug 18 05:06:57 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 282004 kb
Host smart-af77bc7a-e589-4e43-8360-7f7ca4995bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310025432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3310025432 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1107865348
Short name T713
Test name
Test status
Simulation time 997410711 ps
CPU time 20.37 seconds
Started Aug 18 05:06:53 PM PDT 24
Finished Aug 18 05:07:13 PM PDT 24
Peak memory 226600 kb
Host smart-f69a3f2a-7c8f-4d6b-aea1-70c30754f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107865348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1107865348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.290165307
Short name T518
Test name
Test status
Simulation time 45650800426 ps
CPU time 1206.04 seconds
Started Aug 18 05:06:53 PM PDT 24
Finished Aug 18 05:26:59 PM PDT 24
Peak memory 669304 kb
Host smart-298d001b-1005-4182-9c9f-7207a54c165a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=290165307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.290165307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_alert_test.2077771497
Short name T200
Test name
Test status
Simulation time 14777374 ps
CPU time 0.85 seconds
Started Aug 18 05:07:06 PM PDT 24
Finished Aug 18 05:07:07 PM PDT 24
Peak memory 218292 kb
Host smart-c0f08fb4-c8ad-40ac-bc04-b7706b80733a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077771497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2077771497 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.3267105713
Short name T308
Test name
Test status
Simulation time 13242966790 ps
CPU time 251.95 seconds
Started Aug 18 05:07:06 PM PDT 24
Finished Aug 18 05:11:18 PM PDT 24
Peak memory 416620 kb
Host smart-9ed46517-5e92-4b7c-857c-fc968d6e85b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267105713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.3267105713 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.2190473476
Short name T491
Test name
Test status
Simulation time 50203235229 ps
CPU time 1616.09 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:34:00 PM PDT 24
Peak memory 245852 kb
Host smart-1ae0fe0d-ffef-4de9-b390-f985e6b94182
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190473476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.219047347
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.373385802
Short name T283
Test name
Test status
Simulation time 914697169 ps
CPU time 64.08 seconds
Started Aug 18 05:07:03 PM PDT 24
Finished Aug 18 05:08:08 PM PDT 24
Peak memory 244752 kb
Host smart-2828a308-a5ee-42d4-9f4b-a7068298c875
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373385802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.37
3385802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3550953378
Short name T37
Test name
Test status
Simulation time 3845502300 ps
CPU time 111.25 seconds
Started Aug 18 05:07:05 PM PDT 24
Finished Aug 18 05:08:56 PM PDT 24
Peak memory 307924 kb
Host smart-67b4ed84-dadd-43cf-8827-51ed7248fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550953378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3550953378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.2924627647
Short name T385
Test name
Test status
Simulation time 1256153760 ps
CPU time 3.13 seconds
Started Aug 18 05:07:03 PM PDT 24
Finished Aug 18 05:07:07 PM PDT 24
Peak memory 226504 kb
Host smart-ecb3d8ad-f146-4388-8c6e-79ebf71f5aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924627647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2924627647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.1992796387
Short name T561
Test name
Test status
Simulation time 134193913 ps
CPU time 1.35 seconds
Started Aug 18 05:07:03 PM PDT 24
Finished Aug 18 05:07:05 PM PDT 24
Peak memory 226688 kb
Host smart-01997b31-7af0-4aca-86ec-12f70f2796d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992796387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1992796387 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.599439162
Short name T505
Test name
Test status
Simulation time 36515436228 ps
CPU time 385.68 seconds
Started Aug 18 05:07:05 PM PDT 24
Finished Aug 18 05:13:31 PM PDT 24
Peak memory 651428 kb
Host smart-a6c637b7-2fd7-4a8c-a8ac-0c99c6dc7d1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599439162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.599439162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2368189694
Short name T481
Test name
Test status
Simulation time 7937202041 ps
CPU time 173.75 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:09:58 PM PDT 24
Peak memory 283184 kb
Host smart-e1ce7bd1-0cca-4fc9-97dd-442d86a0c19b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368189694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2368189694 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.3484870485
Short name T697
Test name
Test status
Simulation time 3188392602 ps
CPU time 54.82 seconds
Started Aug 18 05:07:08 PM PDT 24
Finished Aug 18 05:08:03 PM PDT 24
Peak memory 226760 kb
Host smart-d8f0c9ac-f7a9-44b7-b1ae-ff9cf0ff6be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484870485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.3484870485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.643429094
Short name T503
Test name
Test status
Simulation time 5838393144 ps
CPU time 135.02 seconds
Started Aug 18 05:07:03 PM PDT 24
Finished Aug 18 05:09:18 PM PDT 24
Peak memory 285128 kb
Host smart-db46cb5c-45ae-4578-9ba1-9389fb289a25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=643429094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.643429094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_alert_test.3170790566
Short name T217
Test name
Test status
Simulation time 60451695 ps
CPU time 0.83 seconds
Started Aug 18 05:07:07 PM PDT 24
Finished Aug 18 05:07:08 PM PDT 24
Peak memory 218276 kb
Host smart-06c47ccd-c01b-4e6c-a0bb-2b4c237cf797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170790566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3170790566 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.3655192671
Short name T136
Test name
Test status
Simulation time 25085390567 ps
CPU time 331.96 seconds
Started Aug 18 05:07:05 PM PDT 24
Finished Aug 18 05:12:37 PM PDT 24
Peak memory 323232 kb
Host smart-7041ad6e-9e40-49c8-b4cc-fa9d7393df68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655192671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3655192671 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.4116846542
Short name T233
Test name
Test status
Simulation time 206648885032 ps
CPU time 1514.96 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:32:20 PM PDT 24
Peak memory 264352 kb
Host smart-7804088e-be24-4038-9765-f106455f6647
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116846542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.411684654
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2713448159
Short name T343
Test name
Test status
Simulation time 6438996377 ps
CPU time 149.51 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 317948 kb
Host smart-8f1c2a28-59de-4c70-bd05-80b0a58b574e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713448159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2
713448159 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.334610329
Short name T337
Test name
Test status
Simulation time 45212781667 ps
CPU time 319.09 seconds
Started Aug 18 05:07:08 PM PDT 24
Finished Aug 18 05:12:27 PM PDT 24
Peak memory 488600 kb
Host smart-7d9b5da3-c980-46ad-a636-ec63d747ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334610329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.334610329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.2592875903
Short name T434
Test name
Test status
Simulation time 2601067471 ps
CPU time 4.95 seconds
Started Aug 18 05:07:07 PM PDT 24
Finished Aug 18 05:07:12 PM PDT 24
Peak memory 226460 kb
Host smart-ad93961a-8125-40f8-83eb-dc31703d37a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592875903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2592875903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.64510390
Short name T570
Test name
Test status
Simulation time 69425275 ps
CPU time 2.28 seconds
Started Aug 18 05:07:07 PM PDT 24
Finished Aug 18 05:07:09 PM PDT 24
Peak memory 226636 kb
Host smart-469720a3-da83-4e4f-b992-097f6da8b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64510390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.64510390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.52928160
Short name T433
Test name
Test status
Simulation time 310939807676 ps
CPU time 4025.79 seconds
Started Aug 18 05:07:06 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 3229240 kb
Host smart-32357360-63ae-4f5a-baaf-ec165c503edb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52928160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and
_output.52928160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3876753658
Short name T376
Test name
Test status
Simulation time 4161949187 ps
CPU time 297.41 seconds
Started Aug 18 05:07:08 PM PDT 24
Finished Aug 18 05:12:05 PM PDT 24
Peak memory 318336 kb
Host smart-60ebf16f-9c36-4316-8119-37864669cfab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876753658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3876753658 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.350806946
Short name T206
Test name
Test status
Simulation time 5994475555 ps
CPU time 73.65 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:08:18 PM PDT 24
Peak memory 226808 kb
Host smart-1b355e92-3a0d-4a80-a6d1-dcd7dca56232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350806946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.350806946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.2741044777
Short name T685
Test name
Test status
Simulation time 5018531756 ps
CPU time 138.69 seconds
Started Aug 18 05:07:04 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 307384 kb
Host smart-ed325a85-7fc5-4e44-9b46-e269df6acf31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2741044777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2741044777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_alert_test.688733630
Short name T569
Test name
Test status
Simulation time 17567954 ps
CPU time 0.78 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:07:16 PM PDT 24
Peak memory 218208 kb
Host smart-82e921be-e8f9-4a9e-97c2-b8b7e54c0a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688733630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.688733630 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2097795463
Short name T387
Test name
Test status
Simulation time 12977187328 ps
CPU time 198.56 seconds
Started Aug 18 05:07:16 PM PDT 24
Finished Aug 18 05:10:34 PM PDT 24
Peak memory 354536 kb
Host smart-32cb0fa3-6726-48bb-90d8-12342695c115
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097795463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2097795463 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3710033973
Short name T674
Test name
Test status
Simulation time 61884331784 ps
CPU time 1692.73 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:35:28 PM PDT 24
Peak memory 249508 kb
Host smart-ebd228f6-2227-4415-ae21-ebca9c5fe29a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710033973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.371003397
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.8681072
Short name T64
Test name
Test status
Simulation time 1462261647 ps
CPU time 67.56 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:08:23 PM PDT 24
Peak memory 247808 kb
Host smart-7143e2df-20ac-46f9-a98d-5e801ad30a35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8681072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.8681
072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.1354492263
Short name T448
Test name
Test status
Simulation time 9302990369 ps
CPU time 442.16 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:14:38 PM PDT 24
Peak memory 395384 kb
Host smart-7bd54dbd-40d2-4c95-95d8-82df25fb544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354492263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1354492263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2853523462
Short name T397
Test name
Test status
Simulation time 253319293 ps
CPU time 2.47 seconds
Started Aug 18 05:07:16 PM PDT 24
Finished Aug 18 05:07:19 PM PDT 24
Peak memory 226380 kb
Host smart-cacdf732-70b7-49f2-a17d-7add49352fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853523462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2853523462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.309940576
Short name T48
Test name
Test status
Simulation time 78722178 ps
CPU time 1.37 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:07:17 PM PDT 24
Peak memory 226732 kb
Host smart-7da3e374-1380-4301-a4eb-6d29fd611c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309940576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.309940576 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_sideload.3335758729
Short name T145
Test name
Test status
Simulation time 2946956752 ps
CPU time 249.12 seconds
Started Aug 18 05:07:14 PM PDT 24
Finished Aug 18 05:11:24 PM PDT 24
Peak memory 305712 kb
Host smart-aada0916-f8fc-4fde-9fb1-c931d696363f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335758729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3335758729 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.3501417740
Short name T435
Test name
Test status
Simulation time 5664660258 ps
CPU time 61.69 seconds
Started Aug 18 05:07:15 PM PDT 24
Finished Aug 18 05:08:17 PM PDT 24
Peak memory 226644 kb
Host smart-162d6b06-bb26-49dd-a526-1c49361dbd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501417740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3501417740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2485056614
Short name T630
Test name
Test status
Simulation time 13698984070 ps
CPU time 90.77 seconds
Started Aug 18 05:07:18 PM PDT 24
Finished Aug 18 05:08:49 PM PDT 24
Peak memory 286240 kb
Host smart-e8ba0911-df2e-4895-9e6d-eb965db14cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2485056614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2485056614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_alert_test.2791952733
Short name T468
Test name
Test status
Simulation time 21973383 ps
CPU time 0.86 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:27 PM PDT 24
Peak memory 218284 kb
Host smart-d308ab73-a73c-47ae-8ce9-f6277c948f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791952733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2791952733 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.389976126
Short name T273
Test name
Test status
Simulation time 25162965681 ps
CPU time 194.95 seconds
Started Aug 18 05:07:16 PM PDT 24
Finished Aug 18 05:10:31 PM PDT 24
Peak memory 358244 kb
Host smart-35e2b48e-6b48-4b24-b44a-643d428975d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389976126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.389976126 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.689946203
Short name T408
Test name
Test status
Simulation time 210886140995 ps
CPU time 802.03 seconds
Started Aug 18 05:07:14 PM PDT 24
Finished Aug 18 05:20:36 PM PDT 24
Peak memory 246672 kb
Host smart-e26fd83f-207e-4026-b3e1-85d6a479d1de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689946203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.689946203
+enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2937451825
Short name T269
Test name
Test status
Simulation time 14974886267 ps
CPU time 367.86 seconds
Started Aug 18 05:07:16 PM PDT 24
Finished Aug 18 05:13:24 PM PDT 24
Peak memory 532820 kb
Host smart-db236e17-8c1d-4367-bfb3-2e49e699a43f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937451825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2
937451825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.872024846
Short name T347
Test name
Test status
Simulation time 7401730864 ps
CPU time 225.79 seconds
Started Aug 18 05:07:17 PM PDT 24
Finished Aug 18 05:11:03 PM PDT 24
Peak memory 405532 kb
Host smart-d601b451-1158-4607-847e-74c7218828e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872024846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.872024846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.1498054529
Short name T668
Test name
Test status
Simulation time 192018271 ps
CPU time 1.41 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:28 PM PDT 24
Peak memory 226456 kb
Host smart-35088ec7-1c3b-4bf8-afba-fa72ea44ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498054529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1498054529 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3148335323
Short name T473
Test name
Test status
Simulation time 351712052 ps
CPU time 4.87 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:31 PM PDT 24
Peak memory 235180 kb
Host smart-9457ec69-d5a0-4d31-8054-bacd43e8491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148335323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3148335323 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2119050395
Short name T218
Test name
Test status
Simulation time 205381808081 ps
CPU time 4551.33 seconds
Started Aug 18 05:07:16 PM PDT 24
Finished Aug 18 06:23:08 PM PDT 24
Peak memory 3723296 kb
Host smart-8a61bd32-1219-441a-b885-eb026a25d2a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119050395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2119050395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2105123308
Short name T576
Test name
Test status
Simulation time 19441924059 ps
CPU time 186.4 seconds
Started Aug 18 05:07:14 PM PDT 24
Finished Aug 18 05:10:21 PM PDT 24
Peak memory 378748 kb
Host smart-fb61c3b7-6fd0-4a2d-893f-8782d3944b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105123308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2105123308 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.1659162810
Short name T212
Test name
Test status
Simulation time 3621207388 ps
CPU time 22.32 seconds
Started Aug 18 05:07:17 PM PDT 24
Finished Aug 18 05:07:39 PM PDT 24
Peak memory 223748 kb
Host smart-cba5c532-f3bf-45fb-af72-b4ab21fd9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659162810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1659162810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1240434547
Short name T427
Test name
Test status
Simulation time 12033991023 ps
CPU time 595.01 seconds
Started Aug 18 05:07:24 PM PDT 24
Finished Aug 18 05:17:19 PM PDT 24
Peak memory 459784 kb
Host smart-9ec3d08a-4799-4028-8484-1f51a49bbc9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1240434547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1240434547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_alert_test.222568413
Short name T596
Test name
Test status
Simulation time 51731109 ps
CPU time 0.91 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:07:26 PM PDT 24
Peak memory 218244 kb
Host smart-b14f1a2b-1ea4-4af0-921b-6573d074c0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222568413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.222568413 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.2756657012
Short name T378
Test name
Test status
Simulation time 24378019693 ps
CPU time 169.35 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:10:14 PM PDT 24
Peak memory 344684 kb
Host smart-20a6e370-2b3e-46e8-9aad-6fd95ff4d8b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756657012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2756657012 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2180631776
Short name T149
Test name
Test status
Simulation time 13217892761 ps
CPU time 569.52 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:16:55 PM PDT 24
Peak memory 241268 kb
Host smart-da24468c-2760-4024-b114-2a5664a8c405
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180631776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.218063177
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_error.1059233316
Short name T327
Test name
Test status
Simulation time 5600149780 ps
CPU time 40.91 seconds
Started Aug 18 05:07:24 PM PDT 24
Finished Aug 18 05:08:05 PM PDT 24
Peak memory 266372 kb
Host smart-e20026fd-ab2a-4174-be09-8f3bc180df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059233316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1059233316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.260180234
Short name T475
Test name
Test status
Simulation time 1013824516 ps
CPU time 7.29 seconds
Started Aug 18 05:07:23 PM PDT 24
Finished Aug 18 05:07:31 PM PDT 24
Peak memory 226344 kb
Host smart-4c95a842-538a-47a8-99c6-acedb02d95fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260180234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.260180234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3400353076
Short name T276
Test name
Test status
Simulation time 35293773 ps
CPU time 1.47 seconds
Started Aug 18 05:07:27 PM PDT 24
Finished Aug 18 05:07:28 PM PDT 24
Peak memory 226656 kb
Host smart-4cf6f629-cd6d-4438-9f92-240377a7b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400353076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3400353076 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_sideload.2307658384
Short name T574
Test name
Test status
Simulation time 7901915402 ps
CPU time 122.56 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:09:29 PM PDT 24
Peak memory 264360 kb
Host smart-0d767237-3c2f-42ff-8567-1a0e5ad38967
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307658384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2307658384 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.3977685045
Short name T559
Test name
Test status
Simulation time 2757449393 ps
CPU time 5.95 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:32 PM PDT 24
Peak memory 226628 kb
Host smart-37e8d273-3ebd-4ed9-8e59-3ada94e79e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977685045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3977685045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3414448060
Short name T348
Test name
Test status
Simulation time 9412855545 ps
CPU time 234.34 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:11:20 PM PDT 24
Peak memory 357912 kb
Host smart-f38bcba2-6075-47ae-a54d-b91a539b781a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3414448060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3414448060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_alert_test.2666461980
Short name T3
Test name
Test status
Simulation time 16217834 ps
CPU time 0.79 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:27 PM PDT 24
Peak memory 218232 kb
Host smart-d783818d-684d-4e06-ac01-61a5ba662961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666461980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2666461980 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.1314469593
Short name T286
Test name
Test status
Simulation time 18633322691 ps
CPU time 363.54 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:13:29 PM PDT 24
Peak memory 479112 kb
Host smart-c657b1ca-30ab-4a13-9b35-05d25394ff8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314469593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1314469593 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.1321005306
Short name T16
Test name
Test status
Simulation time 71317931363 ps
CPU time 738.16 seconds
Started Aug 18 05:07:27 PM PDT 24
Finished Aug 18 05:19:45 PM PDT 24
Peak memory 246584 kb
Host smart-6a390a69-675a-42b6-9d25-b52eb7898b95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321005306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.132100530
6 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.2451710847
Short name T35
Test name
Test status
Simulation time 4639007657 ps
CPU time 53.93 seconds
Started Aug 18 05:07:23 PM PDT 24
Finished Aug 18 05:08:17 PM PDT 24
Peak memory 263560 kb
Host smart-4975f276-fc97-4bbd-9a01-d3c9e8098dc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451710847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2
451710847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.2233439517
Short name T224
Test name
Test status
Simulation time 155445843112 ps
CPU time 645.28 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:18:12 PM PDT 24
Peak memory 648272 kb
Host smart-1a6404b2-039e-4974-90ad-2ef69091451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233439517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2233439517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2042650822
Short name T39
Test name
Test status
Simulation time 554625705 ps
CPU time 5.32 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:07:32 PM PDT 24
Peak memory 234672 kb
Host smart-e2a74f36-ea92-4dc8-ac6a-bf96206fb8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042650822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2042650822 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3635571147
Short name T694
Test name
Test status
Simulation time 166991978008 ps
CPU time 409.7 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:14:15 PM PDT 24
Peak memory 685520 kb
Host smart-cab269e7-3684-44ab-a0fb-a73828034f07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635571147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3635571147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.1710686135
Short name T451
Test name
Test status
Simulation time 38696064328 ps
CPU time 387.45 seconds
Started Aug 18 05:07:24 PM PDT 24
Finished Aug 18 05:13:52 PM PDT 24
Peak memory 339492 kb
Host smart-5a3d787f-4086-4e51-8c5d-8e9d0444086d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710686135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1710686135 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.4108591384
Short name T184
Test name
Test status
Simulation time 2764914862 ps
CPU time 64.65 seconds
Started Aug 18 05:07:25 PM PDT 24
Finished Aug 18 05:08:29 PM PDT 24
Peak memory 225164 kb
Host smart-21bd951c-9235-4040-9769-af3ea9dc2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108591384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.4108591384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.1055967709
Short name T607
Test name
Test status
Simulation time 214532656004 ps
CPU time 2222.14 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:44:29 PM PDT 24
Peak memory 1937444 kb
Host smart-525e2dd3-d9a1-47af-9d19-9c39d828a80d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1055967709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1055967709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1324933824
Short name T474
Test name
Test status
Simulation time 18222213 ps
CPU time 0.83 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:07:38 PM PDT 24
Peak memory 218200 kb
Host smart-4796bef1-da6b-4314-8391-d07b64af5284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324933824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1324933824 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.1890768187
Short name T512
Test name
Test status
Simulation time 35815785321 ps
CPU time 470.29 seconds
Started Aug 18 05:07:38 PM PDT 24
Finished Aug 18 05:15:28 PM PDT 24
Peak memory 563744 kb
Host smart-9a795964-2e13-4f03-a4b4-ee1af81cf411
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890768187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1890768187 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2466581632
Short name T393
Test name
Test status
Simulation time 41286599101 ps
CPU time 1023.66 seconds
Started Aug 18 05:07:36 PM PDT 24
Finished Aug 18 05:24:40 PM PDT 24
Peak memory 253688 kb
Host smart-48f7a4e3-cc55-4383-933b-0ba3713d0042
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466581632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.246658163
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.1900716695
Short name T167
Test name
Test status
Simulation time 27691965916 ps
CPU time 407.57 seconds
Started Aug 18 05:07:36 PM PDT 24
Finished Aug 18 05:14:24 PM PDT 24
Peak memory 531344 kb
Host smart-4e8f59fc-6d55-4f6c-b412-8e43ecbd1601
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900716695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1
900716695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.1566210926
Short name T38
Test name
Test status
Simulation time 6877651586 ps
CPU time 122.34 seconds
Started Aug 18 05:07:36 PM PDT 24
Finished Aug 18 05:09:38 PM PDT 24
Peak memory 267728 kb
Host smart-e88d0247-57f3-4f4d-aaf5-a76c74b9b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566210926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1566210926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.2760272741
Short name T4
Test name
Test status
Simulation time 332354182 ps
CPU time 3.3 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:07:41 PM PDT 24
Peak memory 226372 kb
Host smart-28c0e9c4-a35b-4db6-bfa9-07cfd950cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760272741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2760272741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.483222469
Short name T592
Test name
Test status
Simulation time 642614386 ps
CPU time 10.44 seconds
Started Aug 18 05:07:36 PM PDT 24
Finished Aug 18 05:07:46 PM PDT 24
Peak memory 243164 kb
Host smart-32fe9bc8-9039-4dbe-9e4b-15eb45d17012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483222469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.483222469 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.3299084833
Short name T112
Test name
Test status
Simulation time 904606587 ps
CPU time 105.14 seconds
Started Aug 18 05:07:27 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 266264 kb
Host smart-4a46b46e-0466-4866-b09c-0143ff61e333
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299084833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.3299084833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.2164834569
Short name T412
Test name
Test status
Simulation time 13633168868 ps
CPU time 293.2 seconds
Started Aug 18 05:07:26 PM PDT 24
Finished Aug 18 05:12:20 PM PDT 24
Peak memory 316216 kb
Host smart-272d179a-9b1d-483e-b69f-952210f9df07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164834569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2164834569 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.1159677888
Short name T312
Test name
Test status
Simulation time 1205603102 ps
CPU time 42.6 seconds
Started Aug 18 05:07:27 PM PDT 24
Finished Aug 18 05:08:10 PM PDT 24
Peak memory 226540 kb
Host smart-b6d4bbc1-6836-4764-b1eb-bebcf0d594c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159677888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1159677888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.4148927464
Short name T338
Test name
Test status
Simulation time 9544914604 ps
CPU time 803.38 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:21:01 PM PDT 24
Peak memory 447352 kb
Host smart-08168022-8a5e-43de-acc0-e4674565d02f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4148927464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.4148927464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_alert_test.438504358
Short name T623
Test name
Test status
Simulation time 38388068 ps
CPU time 0.8 seconds
Started Aug 18 05:07:50 PM PDT 24
Finished Aug 18 05:07:51 PM PDT 24
Peak memory 218196 kb
Host smart-dd315fb0-7d2d-44d0-9e3b-fe2ad5c9463f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438504358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.438504358 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3077614713
Short name T329
Test name
Test status
Simulation time 8708703916 ps
CPU time 66.13 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 267228 kb
Host smart-4a4491cd-567f-473a-8c63-1f71caf23d89
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077614713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3077614713 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.3305018020
Short name T134
Test name
Test status
Simulation time 10731225772 ps
CPU time 144.52 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:10:01 PM PDT 24
Peak memory 229916 kb
Host smart-ba044cac-359d-4c9a-8ac2-97eee4254c70
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305018020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.330501802
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2004902515
Short name T691
Test name
Test status
Simulation time 1175599389 ps
CPU time 41.26 seconds
Started Aug 18 05:07:39 PM PDT 24
Finished Aug 18 05:08:20 PM PDT 24
Peak memory 241356 kb
Host smart-05a38b1b-ded0-402e-b74a-0d6f123f84e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004902515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2
004902515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.3316202208
Short name T268
Test name
Test status
Simulation time 3972824097 ps
CPU time 149.5 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:10:07 PM PDT 24
Peak memory 289384 kb
Host smart-f0a448e4-ae30-4189-a7ce-94a76cc27a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316202208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3316202208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.2397197931
Short name T486
Test name
Test status
Simulation time 5580266187 ps
CPU time 10.87 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:07:48 PM PDT 24
Peak memory 226704 kb
Host smart-6736343e-8bb0-49d0-9146-6dcdf60029f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397197931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2397197931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.1919953001
Short name T282
Test name
Test status
Simulation time 214242545 ps
CPU time 1.75 seconds
Started Aug 18 05:07:50 PM PDT 24
Finished Aug 18 05:07:52 PM PDT 24
Peak memory 226532 kb
Host smart-60941fe9-4223-4ce1-bf0f-4bbaa7dc406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919953001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1919953001 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.2206295591
Short name T287
Test name
Test status
Simulation time 21562799753 ps
CPU time 2854.49 seconds
Started Aug 18 05:07:37 PM PDT 24
Finished Aug 18 05:55:12 PM PDT 24
Peak memory 1495684 kb
Host smart-97f68277-8de2-4343-8029-1e424836b16d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206295591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.2206295591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.2082517231
Short name T203
Test name
Test status
Simulation time 14188076341 ps
CPU time 106.16 seconds
Started Aug 18 05:07:38 PM PDT 24
Finished Aug 18 05:09:24 PM PDT 24
Peak memory 304864 kb
Host smart-22883186-a283-40be-bf60-221a5a0af649
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082517231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.2082517231 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.2986758804
Short name T142
Test name
Test status
Simulation time 7807431111 ps
CPU time 66.03 seconds
Started Aug 18 05:07:36 PM PDT 24
Finished Aug 18 05:08:43 PM PDT 24
Peak memory 226728 kb
Host smart-5e533867-141a-49b5-bf41-3aa0188bfe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986758804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.2986758804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_alert_test.2647105249
Short name T264
Test name
Test status
Simulation time 13126862 ps
CPU time 0.82 seconds
Started Aug 18 05:07:48 PM PDT 24
Finished Aug 18 05:07:49 PM PDT 24
Peak memory 218280 kb
Host smart-8e9583b7-4456-496c-89e7-3ba70117681e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647105249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2647105249 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.4016448632
Short name T669
Test name
Test status
Simulation time 74607419465 ps
CPU time 458.94 seconds
Started Aug 18 05:07:51 PM PDT 24
Finished Aug 18 05:15:30 PM PDT 24
Peak memory 556500 kb
Host smart-16a1d73f-9b05-4c0c-a516-46aff150b2eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016448632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.4016448632 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.689248001
Short name T616
Test name
Test status
Simulation time 9976605383 ps
CPU time 359.22 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:13:49 PM PDT 24
Peak memory 238140 kb
Host smart-e7b1d0f8-f99b-4071-8b95-48964e8fa6e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689248001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.689248001
+enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.535595531
Short name T341
Test name
Test status
Simulation time 57687189556 ps
CPU time 384.61 seconds
Started Aug 18 05:07:52 PM PDT 24
Finished Aug 18 05:14:16 PM PDT 24
Peak memory 480248 kb
Host smart-4a04c22e-7252-42d5-8277-2715eb029eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535595531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.53
5595531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.3295355219
Short name T19
Test name
Test status
Simulation time 8689534161 ps
CPU time 234.39 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:11:44 PM PDT 24
Peak memory 434296 kb
Host smart-0938fef6-d3c7-45e9-9148-48e535f8e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295355219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3295355219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.3844000649
Short name T709
Test name
Test status
Simulation time 5064255279 ps
CPU time 4.52 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:07:53 PM PDT 24
Peak memory 226580 kb
Host smart-38053800-5722-4cf3-95dd-7746523f6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844000649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3844000649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.1310075979
Short name T442
Test name
Test status
Simulation time 106474688 ps
CPU time 1.42 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:07:50 PM PDT 24
Peak memory 226528 kb
Host smart-7309660c-700e-422f-bc34-f7d1cf9a914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310075979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1310075979 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.347170940
Short name T454
Test name
Test status
Simulation time 123131135496 ps
CPU time 2808.9 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:54:38 PM PDT 24
Peak memory 2596520 kb
Host smart-d273c33d-4f67-4489-a602-1173bf332ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347170940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an
d_output.347170940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.254095086
Short name T413
Test name
Test status
Simulation time 132203856229 ps
CPU time 561.84 seconds
Started Aug 18 05:07:50 PM PDT 24
Finished Aug 18 05:17:12 PM PDT 24
Peak memory 597432 kb
Host smart-367361c0-3b7b-4e6b-886e-ce6a0f85b508
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254095086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.254095086 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.777124620
Short name T220
Test name
Test status
Simulation time 1651669813 ps
CPU time 41.95 seconds
Started Aug 18 05:07:51 PM PDT 24
Finished Aug 18 05:08:33 PM PDT 24
Peak memory 226752 kb
Host smart-6fc33c4d-0ec6-4823-a867-4ea1c9789c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777124620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.777124620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.96314043
Short name T409
Test name
Test status
Simulation time 9398639004 ps
CPU time 112.6 seconds
Started Aug 18 05:07:49 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 285224 kb
Host smart-8d729e5f-dfe1-47c2-b950-7a954501e547
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=96314043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.96314043 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3540931046
Short name T516
Test name
Test status
Simulation time 44338685 ps
CPU time 0.84 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:04:14 PM PDT 24
Peak memory 218292 kb
Host smart-6b587888-25f9-490d-9d13-cacd587e725d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540931046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3540931046 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.1579428393
Short name T652
Test name
Test status
Simulation time 19371143989 ps
CPU time 382.78 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:10:35 PM PDT 24
Peak memory 355388 kb
Host smart-2e3ae720-e078-4fa7-bb7c-faad5d35f5cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579428393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1579428393 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.2684750891
Short name T624
Test name
Test status
Simulation time 65501135230 ps
CPU time 453.7 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:11:46 PM PDT 24
Peak memory 525860 kb
Host smart-a762b4b7-2091-43c2-99ca-b390b7582734
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684750891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_par
tial_data.2684750891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.2220607244
Short name T497
Test name
Test status
Simulation time 54393363059 ps
CPU time 1037.49 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:21:29 PM PDT 24
Peak memory 257364 kb
Host smart-943d57fb-3f0a-4f16-b857-29fd5485c147
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220607244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2220607244
+enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.2280291033
Short name T703
Test name
Test status
Simulation time 2048548673 ps
CPU time 36.18 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:04:50 PM PDT 24
Peak memory 227632 kb
Host smart-bc59f7de-364d-40d9-8f80-0c2f5f419207
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2280291033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2280291033 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.957672837
Short name T535
Test name
Test status
Simulation time 70920554 ps
CPU time 1.17 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:04:12 PM PDT 24
Peak memory 221608 kb
Host smart-1e033369-2a90-4836-8b7a-10dd08e62b43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=957672837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.957672837 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3543483877
Short name T11
Test name
Test status
Simulation time 22436607471 ps
CPU time 71.08 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:05:21 PM PDT 24
Peak memory 226852 kb
Host smart-a5780b87-1e90-4cbf-9ad1-70c71dc6cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543483877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3543483877 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.4034510281
Short name T70
Test name
Test status
Simulation time 6816095709 ps
CPU time 143.67 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:06:36 PM PDT 24
Peak memory 322948 kb
Host smart-fb425848-c440-4285-8273-b48380653830
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034510281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.40
34510281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_key_error.1434067131
Short name T522
Test name
Test status
Simulation time 14389328426 ps
CPU time 11.61 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:04:22 PM PDT 24
Peak memory 226640 kb
Host smart-fb54dc2e-5146-4188-a43c-3eb1a2eff5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434067131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1434067131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.209781006
Short name T303
Test name
Test status
Simulation time 23087905304 ps
CPU time 3023.72 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:54:37 PM PDT 24
Peak memory 1645444 kb
Host smart-e8cbec0e-459a-4439-9a37-4217b0d852dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209781006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and
_output.209781006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.83772975
Short name T267
Test name
Test status
Simulation time 9052516695 ps
CPU time 131.01 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:06:22 PM PDT 24
Peak memory 328316 kb
Host smart-19d45f25-7ec1-4647-9746-92ecef4fb81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83772975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.83772975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.3003015698
Short name T56
Test name
Test status
Simulation time 6147026271 ps
CPU time 480.79 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:12:13 PM PDT 24
Peak memory 364856 kb
Host smart-2097ad32-6c4e-4228-869e-32bee1c58bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003015698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3003015698 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.1355682003
Short name T274
Test name
Test status
Simulation time 12607420140 ps
CPU time 76.88 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:05:30 PM PDT 24
Peak memory 226668 kb
Host smart-2dbd3671-95c6-40aa-ba32-23a1b4cdc36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355682003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1355682003 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_alert_test.3401890088
Short name T101
Test name
Test status
Simulation time 18647920 ps
CPU time 0.84 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:04:15 PM PDT 24
Peak memory 218208 kb
Host smart-abe54e75-5f70-4d1d-a143-8be09d7deef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401890088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3401890088 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.488808142
Short name T205
Test name
Test status
Simulation time 11068451575 ps
CPU time 274.86 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:08:48 PM PDT 24
Peak memory 425580 kb
Host smart-e4e2f446-c734-4f6c-a6df-81323c428176
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488808142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.488808142 +enable_masking=1
+sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.2671137300
Short name T289
Test name
Test status
Simulation time 15345637086 ps
CPU time 379.45 seconds
Started Aug 18 05:04:10 PM PDT 24
Finished Aug 18 05:10:30 PM PDT 24
Peak memory 487908 kb
Host smart-aa77bf2c-3cf8-44d7-8d1c-3838c4dabeb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671137300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_par
tial_data.2671137300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.548147538
Short name T368
Test name
Test status
Simulation time 24113712404 ps
CPU time 605.08 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:14:16 PM PDT 24
Peak memory 238688 kb
Host smart-9be0bba1-1c42-4f1e-acce-fd652966850c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548147538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.548147538 +
enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3894716638
Short name T557
Test name
Test status
Simulation time 1051928861 ps
CPU time 23.54 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:04:36 PM PDT 24
Peak memory 232396 kb
Host smart-bee87a63-1667-4cce-a6ff-075b4444c2cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3894716638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3894716638 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.3058918139
Short name T384
Test name
Test status
Simulation time 55903186 ps
CPU time 0.94 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:04:12 PM PDT 24
Peak memory 220492 kb
Host smart-444daebf-4cab-416e-baee-bbd2993decf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058918139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3058918139 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.1424476806
Short name T604
Test name
Test status
Simulation time 488749837 ps
CPU time 6.72 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:04:19 PM PDT 24
Peak memory 221400 kb
Host smart-5315245f-bbff-4ad5-b5a9-796832baaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424476806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1424476806 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.702751315
Short name T509
Test name
Test status
Simulation time 11323786336 ps
CPU time 294.34 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:09:06 PM PDT 24
Peak memory 410388 kb
Host smart-0e8fa836-a1e0-42b4-9c7c-b3609c6d6ed0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702751315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refres
h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.702
751315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.2578286313
Short name T392
Test name
Test status
Simulation time 65004453635 ps
CPU time 346.87 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:10:01 PM PDT 24
Peak memory 467872 kb
Host smart-1ae41e40-0601-41c2-bb4a-4f36464c8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578286313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2578286313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.1763871961
Short name T105
Test name
Test status
Simulation time 3013574151 ps
CPU time 9.74 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:04:21 PM PDT 24
Peak memory 218560 kb
Host smart-ce591d67-8918-47af-b7e7-389cba27fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763871961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1763871961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2572090054
Short name T14
Test name
Test status
Simulation time 2327830744 ps
CPU time 15.58 seconds
Started Aug 18 05:04:15 PM PDT 24
Finished Aug 18 05:04:31 PM PDT 24
Peak memory 243248 kb
Host smart-5c348121-8632-4d62-b65d-662e719087a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572090054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2572090054 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.3004346465
Short name T482
Test name
Test status
Simulation time 28125724158 ps
CPU time 1167.86 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:23:41 PM PDT 24
Peak memory 1442608 kb
Host smart-2238b5ea-b845-42aa-9ed2-29a20cf1f13c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004346465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.3004346465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1385064582
Short name T520
Test name
Test status
Simulation time 13749533763 ps
CPU time 264.97 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:08:37 PM PDT 24
Peak memory 411172 kb
Host smart-12e77a04-160f-4739-8bed-852aec24ff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385064582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1385064582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3479214639
Short name T545
Test name
Test status
Simulation time 36750654502 ps
CPU time 277.83 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 413784 kb
Host smart-7d03a2b9-8fb2-4051-833a-87309f3efd63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479214639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3479214639 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.2542879530
Short name T489
Test name
Test status
Simulation time 472910571 ps
CPU time 5.88 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:04:19 PM PDT 24
Peak memory 226424 kb
Host smart-7c38e0d3-cc0e-44ab-a126-463eb2ee4e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542879530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2542879530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.319518580
Short name T306
Test name
Test status
Simulation time 18822500271 ps
CPU time 1491.3 seconds
Started Aug 18 05:04:13 PM PDT 24
Finished Aug 18 05:29:04 PM PDT 24
Peak memory 669640 kb
Host smart-23c07564-20a0-4d37-9a0e-0172ee18b7cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=319518580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.319518580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3382289348
Short name T469
Test name
Test status
Simulation time 80308391 ps
CPU time 0.85 seconds
Started Aug 18 05:04:17 PM PDT 24
Finished Aug 18 05:04:18 PM PDT 24
Peak memory 218236 kb
Host smart-c4e58e3e-6bf0-4cf4-ace3-f7b3636e0817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382289348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3382289348 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.2394516610
Short name T416
Test name
Test status
Simulation time 7499069086 ps
CPU time 231.88 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:08:06 PM PDT 24
Peak memory 295460 kb
Host smart-57953c4b-c959-4697-a52f-0d7e663d704e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394516610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_par
tial_data.2394516610 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3787651340
Short name T438
Test name
Test status
Simulation time 13632068753 ps
CPU time 734.74 seconds
Started Aug 18 05:04:15 PM PDT 24
Finished Aug 18 05:16:30 PM PDT 24
Peak memory 243076 kb
Host smart-5580a8a2-5968-4a0c-a782-849be2152ed4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787651340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3787651340
+enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.2406481064
Short name T62
Test name
Test status
Simulation time 163543614 ps
CPU time 0.96 seconds
Started Aug 18 05:04:15 PM PDT 24
Finished Aug 18 05:04:16 PM PDT 24
Peak memory 218100 kb
Host smart-9850b421-fa5f-4573-9cc3-e7ab3b36330e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2406481064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2406481064 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.2904613423
Short name T194
Test name
Test status
Simulation time 218336646 ps
CPU time 7.64 seconds
Started Aug 18 05:04:17 PM PDT 24
Finished Aug 18 05:04:25 PM PDT 24
Peak memory 226384 kb
Host smart-57ff23cd-c8f5-429c-9ad4-788280b5b050
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2904613423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2904613423 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3291943142
Short name T483
Test name
Test status
Simulation time 5573487700 ps
CPU time 54.8 seconds
Started Aug 18 05:04:16 PM PDT 24
Finished Aug 18 05:05:11 PM PDT 24
Peak memory 226872 kb
Host smart-112e8977-ad1d-46d4-b83a-8098ec05fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291943142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3291943142 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.3013966100
Short name T613
Test name
Test status
Simulation time 4911425940 ps
CPU time 92.49 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:05:47 PM PDT 24
Peak memory 293812 kb
Host smart-ce56b0be-adc8-46fa-8521-86f628bd028f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013966100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.30
13966100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.3863157403
Short name T544
Test name
Test status
Simulation time 9331466805 ps
CPU time 272.25 seconds
Started Aug 18 05:04:18 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 437532 kb
Host smart-e401fc81-f17c-4ef4-b1f9-423f6f5c8498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863157403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3863157403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.4038583764
Short name T247
Test name
Test status
Simulation time 4867288528 ps
CPU time 10.63 seconds
Started Aug 18 05:04:17 PM PDT 24
Finished Aug 18 05:04:27 PM PDT 24
Peak memory 226620 kb
Host smart-4c2005ca-1828-48fb-b4a8-1f740f73edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038583764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4038583764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.2483868133
Short name T496
Test name
Test status
Simulation time 48148600 ps
CPU time 2.01 seconds
Started Aug 18 05:04:15 PM PDT 24
Finished Aug 18 05:04:17 PM PDT 24
Peak memory 226612 kb
Host smart-88d2f3a6-d20c-40a8-a6be-3daed848263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483868133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2483868133 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1211553236
Short name T209
Test name
Test status
Simulation time 181058590103 ps
CPU time 1734.45 seconds
Started Aug 18 05:04:12 PM PDT 24
Finished Aug 18 05:33:06 PM PDT 24
Peak memory 1907364 kb
Host smart-1cd6d33a-4cc8-4ed3-adbd-3009c27bb3e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211553236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1211553236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2511990924
Short name T593
Test name
Test status
Simulation time 9842634272 ps
CPU time 140.97 seconds
Started Aug 18 05:04:11 PM PDT 24
Finished Aug 18 05:06:32 PM PDT 24
Peak memory 275640 kb
Host smart-cfcf62c0-3614-4006-a35f-a6025e0d82ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511990924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2511990924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.870102277
Short name T488
Test name
Test status
Simulation time 1101930862 ps
CPU time 93.06 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:05:47 PM PDT 24
Peak memory 253836 kb
Host smart-17e43a16-33ae-4729-8892-406e6a4c4bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870102277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.870102277 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.3292566934
Short name T364
Test name
Test status
Simulation time 34011234275 ps
CPU time 69.69 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:05:24 PM PDT 24
Peak memory 226800 kb
Host smart-1ee9d469-7919-4962-bdfa-be768bc1dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292566934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3292566934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.3742635153
Short name T550
Test name
Test status
Simulation time 41436970459 ps
CPU time 1393.78 seconds
Started Aug 18 05:04:16 PM PDT 24
Finished Aug 18 05:27:30 PM PDT 24
Peak memory 1231672 kb
Host smart-fb1135e6-622e-4318-a081-27a6a564ac30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3742635153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.3742635153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_alert_test.3517746645
Short name T407
Test name
Test status
Simulation time 46261784 ps
CPU time 0.81 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:26 PM PDT 24
Peak memory 218284 kb
Host smart-ea446831-67f0-4f60-972b-bec08dc5a849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517746645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3517746645 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.1671501995
Short name T168
Test name
Test status
Simulation time 20221914409 ps
CPU time 364.43 seconds
Started Aug 18 05:04:26 PM PDT 24
Finished Aug 18 05:10:30 PM PDT 24
Peak memory 328836 kb
Host smart-9e826514-e7ba-44b5-958b-0a9e5197fecc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671501995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1671501995 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.978834670
Short name T361
Test name
Test status
Simulation time 128511541095 ps
CPU time 284.34 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:09:09 PM PDT 24
Peak memory 422476 kb
Host smart-1d602b12-0912-4a82-8e6f-199cea3eacf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978834670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_parti
al_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_part
ial_data.978834670 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.1642393065
Short name T597
Test name
Test status
Simulation time 13264154881 ps
CPU time 730.57 seconds
Started Aug 18 05:04:15 PM PDT 24
Finished Aug 18 05:16:26 PM PDT 24
Peak memory 246540 kb
Host smart-95b32b3f-b7a3-462d-a47c-cabc5bf1c504
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642393065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1642393065
+enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.1770670065
Short name T143
Test name
Test status
Simulation time 498903875 ps
CPU time 17.5 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:43 PM PDT 24
Peak memory 227112 kb
Host smart-b5b77258-1f1f-4f3c-91f2-f52f94c9853f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1770670065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1770670065 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.3712297192
Short name T418
Test name
Test status
Simulation time 75522533 ps
CPU time 1.21 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:27 PM PDT 24
Peak memory 218304 kb
Host smart-b7a684da-e017-49e2-b576-9b4b71f5a6e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712297192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3712297192 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.3045369424
Short name T425
Test name
Test status
Simulation time 6057839359 ps
CPU time 73.97 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:05:39 PM PDT 24
Peak memory 224408 kb
Host smart-01b4d66d-cd7d-4f8c-a6cb-71dc146be134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045369424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3045369424 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2187601608
Short name T455
Test name
Test status
Simulation time 18716010247 ps
CPU time 189.05 seconds
Started Aug 18 05:04:23 PM PDT 24
Finished Aug 18 05:07:33 PM PDT 24
Peak memory 376228 kb
Host smart-d05492a5-a19e-4b60-98a8-672aebc742a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187601608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.21
87601608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.2392686517
Short name T610
Test name
Test status
Simulation time 14428096133 ps
CPU time 58.15 seconds
Started Aug 18 05:04:24 PM PDT 24
Finished Aug 18 05:05:22 PM PDT 24
Peak memory 262172 kb
Host smart-62bb8d26-d524-4273-a6fd-2599cf84d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392686517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2392686517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1036037720
Short name T249
Test name
Test status
Simulation time 600844604 ps
CPU time 2.91 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:28 PM PDT 24
Peak memory 226304 kb
Host smart-6d8e649d-00d9-4bca-9473-fce07132c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036037720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1036037720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.305365045
Short name T609
Test name
Test status
Simulation time 84148158 ps
CPU time 1.24 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:04:26 PM PDT 24
Peak memory 226732 kb
Host smart-bc08cc6a-b19b-40f9-8392-7fbec6506442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305365045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.305365045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_mubi.1233538533
Short name T680
Test name
Test status
Simulation time 6119462785 ps
CPU time 398.42 seconds
Started Aug 18 05:04:23 PM PDT 24
Finished Aug 18 05:11:01 PM PDT 24
Peak memory 336880 kb
Host smart-3fdc7ae9-e6e6-4871-9086-1edbf4dfec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233538533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1233538533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.2993276324
Short name T228
Test name
Test status
Simulation time 2966820294 ps
CPU time 244.65 seconds
Started Aug 18 05:04:14 PM PDT 24
Finished Aug 18 05:08:18 PM PDT 24
Peak memory 305300 kb
Host smart-eadeed7c-7ec7-4fb7-b8fb-2eeaae9b31a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993276324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2993276324 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3082266162
Short name T192
Test name
Test status
Simulation time 2892965643 ps
CPU time 29.26 seconds
Started Aug 18 05:04:17 PM PDT 24
Finished Aug 18 05:04:47 PM PDT 24
Peak memory 226688 kb
Host smart-b903718d-b2df-4eac-9a4e-4505392fe5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082266162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3082266162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.3063888798
Short name T395
Test name
Test status
Simulation time 50951169094 ps
CPU time 1631.84 seconds
Started Aug 18 05:04:27 PM PDT 24
Finished Aug 18 05:31:39 PM PDT 24
Peak memory 1090264 kb
Host smart-17078429-ae92-4cff-ad4e-28e007dfe46e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3063888798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3063888798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_alert_test.1870719955
Short name T423
Test name
Test status
Simulation time 29208478 ps
CPU time 0.78 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:04:32 PM PDT 24
Peak memory 218268 kb
Host smart-ce77ee71-7272-48cb-8aea-04d73fa9da35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870719955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1870719955 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.3357052877
Short name T381
Test name
Test status
Simulation time 24654231083 ps
CPU time 225.46 seconds
Started Aug 18 05:04:25 PM PDT 24
Finished Aug 18 05:08:11 PM PDT 24
Peak memory 372740 kb
Host smart-2fd22b51-f31f-41d4-aa9f-fd84045ccc91
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357052877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3357052877 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.1365253576
Short name T414
Test name
Test status
Simulation time 39937438855 ps
CPU time 165.92 seconds
Started Aug 18 05:04:26 PM PDT 24
Finished Aug 18 05:07:12 PM PDT 24
Peak memory 335228 kb
Host smart-23faea44-3481-47f8-bf94-4ac94b052337
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365253576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_part
ial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_par
tial_data.1365253576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.3661880946
Short name T99
Test name
Test status
Simulation time 42675960675 ps
CPU time 1115.52 seconds
Started Aug 18 05:04:27 PM PDT 24
Finished Aug 18 05:23:02 PM PDT 24
Peak memory 243140 kb
Host smart-70e33874-e048-4ff9-a1c9-fa39cbc418f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661880946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3661880946
+enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.4103604311
Short name T309
Test name
Test status
Simulation time 280259526 ps
CPU time 13.26 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:04:41 PM PDT 24
Peak memory 226652 kb
Host smart-fc63633b-0ae6-445b-9624-891d163b3f34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103604311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.4103604311 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.617246981
Short name T75
Test name
Test status
Simulation time 26207262 ps
CPU time 0.98 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:04:29 PM PDT 24
Peak memory 221704 kb
Host smart-a6ccc3ff-dc4a-4956-9df7-aa43413a15eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617246981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.617246981 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.3373842022
Short name T10
Test name
Test status
Simulation time 47043239559 ps
CPU time 45.18 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:05:15 PM PDT 24
Peak memory 224892 kb
Host smart-d6024928-6fe9-40fd-b598-00fa85261dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373842022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3373842022 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3227104074
Short name T382
Test name
Test status
Simulation time 7274106916 ps
CPU time 204.97 seconds
Started Aug 18 05:04:26 PM PDT 24
Finished Aug 18 05:07:51 PM PDT 24
Peak memory 296532 kb
Host smart-9fcebc85-a6c5-4408-981f-bb2d11a346b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227104074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refre
sh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.32
27104074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.114545770
Short name T679
Test name
Test status
Simulation time 17775874454 ps
CPU time 342.89 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:10:11 PM PDT 24
Peak memory 506680 kb
Host smart-2eca445f-0441-4105-80ea-bc9d5c8288e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114545770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.114545770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1770790570
Short name T649
Test name
Test status
Simulation time 649628111 ps
CPU time 6.02 seconds
Started Aug 18 05:04:29 PM PDT 24
Finished Aug 18 05:04:35 PM PDT 24
Peak memory 226428 kb
Host smart-53c212c3-32ce-41db-83e5-55f1326af9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770790570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1770790570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.3980800596
Short name T386
Test name
Test status
Simulation time 66915871 ps
CPU time 1.44 seconds
Started Aug 18 05:04:26 PM PDT 24
Finished Aug 18 05:04:28 PM PDT 24
Peak memory 226548 kb
Host smart-f4870cf3-f60d-4a03-8826-dd34e7a0fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980800596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3980800596 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_mubi.703957935
Short name T663
Test name
Test status
Simulation time 2174181525 ps
CPU time 14.47 seconds
Started Aug 18 05:04:28 PM PDT 24
Finished Aug 18 05:04:43 PM PDT 24
Peak memory 243408 kb
Host smart-8c4ef0c7-b2b4-484f-9dfe-4fe8c7b46336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703957935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.703957935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.1877828226
Short name T485
Test name
Test status
Simulation time 2487737564 ps
CPU time 67.48 seconds
Started Aug 18 05:04:27 PM PDT 24
Finished Aug 18 05:05:35 PM PDT 24
Peak memory 273816 kb
Host smart-3df89ee3-0516-4795-b9b2-3d93310063d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877828226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1877828226 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1838717283
Short name T396
Test name
Test status
Simulation time 5882511917 ps
CPU time 77.9 seconds
Started Aug 18 05:04:26 PM PDT 24
Finished Aug 18 05:05:44 PM PDT 24
Peak memory 226980 kb
Host smart-037a5d67-3f1f-468c-8b20-7519253a1aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838717283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1838717283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.4028985653
Short name T595
Test name
Test status
Simulation time 93065872271 ps
CPU time 846.27 seconds
Started Aug 18 05:04:30 PM PDT 24
Finished Aug 18 05:18:36 PM PDT 24
Peak memory 411184 kb
Host smart-fa803adf-397f-4b0c-840b-23654d4d7218
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4028985653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.4028985653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest
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