Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14536662	1			T1	8522		T3	1945		T7	2478
all_values[1]	14536662	1			T1	8522		T3	1945		T7	2478
all_values[2]	14536662	1			T1	8522		T3	1945		T7	2478

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

452128

1

T1

747

T7

33

T32

158

auto[1]

43157858

1

T1

24819

T3

5835

T7

7401

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43411341

1

T1

25278

T3

5346

T7

7365

auto[1]

198645

1

T1

288

T3

489

T7

69

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	135248	1			T1	389		T7	15		T32	24
all_values[0]	auto[0]	auto[1]	1044	1			T1	6		T7	2		T32	4
all_values[0]	auto[1]	auto[0]	14335199	1			T1	8037		T3	1782		T7	2440
all_values[0]	auto[1]	auto[1]	65171	1			T1	90		T3	163		T7	21
all_values[1]	auto[0]	auto[0]	135548	1			T1	174		T32	101		T34	678
all_values[1]	auto[0]	auto[1]	850	1			T1	2		T32	9		T34	1
all_values[1]	auto[1]	auto[0]	14334899	1			T1	8252		T3	1782		T7	2455
all_values[1]	auto[1]	auto[1]	65365	1			T1	94		T3	163		T7	23
all_values[2]	auto[0]	auto[0]	178597	1			T1	174		T7	14		T32	19
all_values[2]	auto[0]	auto[1]	841	1			T1	2		T7	2		T32	1
all_values[2]	auto[1]	auto[0]	14291850	1			T1	8252		T3	1782		T7	2441
all_values[2]	auto[1]	auto[1]	65374	1			T1	94		T3	163		T7	21