Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53356 |
1 |
|
|
T1 |
2 |
|
T3 |
210 |
|
T7 |
42 |
auto[1] |
49084 |
1 |
|
|
T1 |
202 |
|
T32 |
122 |
|
T34 |
182 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
25813 |
1 |
|
|
T1 |
60 |
|
T3 |
50 |
|
T7 |
16 |
lower_val |
25260 |
1 |
|
|
T1 |
40 |
|
T3 |
52 |
|
T7 |
11 |
zero_val |
811 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
38700 |
1 |
|
|
T1 |
54 |
|
T3 |
98 |
|
T7 |
14 |
lower_val |
38870 |
1 |
|
|
T1 |
52 |
|
T3 |
112 |
|
T7 |
28 |
zero_val |
24870 |
1 |
|
|
T1 |
98 |
|
T32 |
64 |
|
T34 |
86 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
6790 |
1 |
|
|
T3 |
20 |
|
T7 |
7 |
|
T8 |
57 |
higher_val |
higher_val |
auto[1] |
3062 |
1 |
|
|
T1 |
18 |
|
T32 |
10 |
|
T34 |
14 |
higher_val |
lower_val |
auto[0] |
6763 |
1 |
|
|
T3 |
30 |
|
T7 |
9 |
|
T48 |
1 |
higher_val |
lower_val |
auto[1] |
3055 |
1 |
|
|
T1 |
8 |
|
T32 |
12 |
|
T34 |
9 |
higher_val |
zero_val |
auto[0] |
55 |
1 |
|
|
T19 |
1 |
|
T16 |
1 |
|
T13 |
1 |
higher_val |
zero_val |
auto[1] |
6088 |
1 |
|
|
T1 |
34 |
|
T32 |
12 |
|
T34 |
23 |
lower_val |
higher_val |
auto[0] |
6515 |
1 |
|
|
T3 |
27 |
|
T7 |
3 |
|
T8 |
48 |
lower_val |
higher_val |
auto[1] |
2982 |
1 |
|
|
T1 |
7 |
|
T32 |
5 |
|
T34 |
12 |
lower_val |
lower_val |
auto[0] |
6525 |
1 |
|
|
T3 |
25 |
|
T7 |
8 |
|
T8 |
59 |
lower_val |
lower_val |
auto[1] |
3080 |
1 |
|
|
T1 |
12 |
|
T32 |
5 |
|
T34 |
12 |
lower_val |
zero_val |
auto[0] |
55 |
1 |
|
|
T15 |
2 |
|
T38 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
6103 |
1 |
|
|
T1 |
21 |
|
T32 |
14 |
|
T34 |
28 |
zero_val |
higher_val |
auto[0] |
250 |
1 |
|
|
T3 |
1 |
|
T49 |
1 |
|
T37 |
1 |
zero_val |
higher_val |
auto[1] |
47 |
1 |
|
|
T32 |
1 |
|
T63 |
1 |
|
T16 |
3 |
zero_val |
lower_val |
auto[0] |
252 |
1 |
|
|
T7 |
1 |
|
T48 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
51 |
1 |
|
|
T15 |
2 |
|
T16 |
1 |
|
T161 |
1 |
zero_val |
zero_val |
auto[0] |
155 |
1 |
|
|
T1 |
1 |
|
T32 |
1 |
|
T34 |
1 |
zero_val |
zero_val |
auto[1] |
56 |
1 |
|
|
T63 |
1 |
|
T16 |
5 |
|
T89 |
1 |