Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14536662	1			T1	8522		T3	1945		T7	2478
all_pins[1]	14536662	1			T1	8522		T3	1945		T7	2478
all_pins[2]	14536662	1			T1	8522		T3	1945		T7	2478

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43264546	1			T1	25476		T3	5672		T7	7406
values[0x1]	345440	1			T1	90		T3	163		T7	28
transitions[0x0=>0x1]	343645	1			T1	90		T3	163		T7	28
transitions[0x1=>0x0]	343667	1			T1	90		T3	163		T7	28

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14471491	1			T1	8432		T3	1782		T7	2457
all_pins[0]	values[0x1]	65171	1			T1	90		T3	163		T7	21
all_pins[0]	transitions[0x0=>0x1]	65157	1			T1	90		T3	163		T7	21
all_pins[0]	transitions[0x1=>0x0]	5729	1			T7	7		T32	5		T34	52
all_pins[1]	values[0x0]	14530919	1			T1	8522		T3	1945		T7	2471
all_pins[1]	values[0x1]	5743	1			T7	7		T32	5		T34	52
all_pins[1]	transitions[0x0=>0x1]	5572	1			T7	7		T32	5		T34	52
all_pins[1]	transitions[0x1=>0x0]	274355	1			T15	4556		T20	1561		T21	306
all_pins[2]	values[0x0]	14262136	1			T1	8522		T3	1945		T7	2478
all_pins[2]	values[0x1]	274526	1			T15	4567		T20	1561		T21	306
all_pins[2]	transitions[0x0=>0x1]	272916	1			T15	4539		T20	1561		T21	306
all_pins[2]	transitions[0x1=>0x0]	63583	1			T1	90		T3	163		T7	21