Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5814828 |
1 |
|
|
T1 |
12752 |
|
T3 |
1260 |
|
T7 |
2461 |
auto[1] |
5814817 |
1 |
|
|
T1 |
12752 |
|
T3 |
1260 |
|
T7 |
2461 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
11570665 |
1 |
|
|
T1 |
25412 |
|
T3 |
2520 |
|
T7 |
4898 |
triple_byte_access |
19532 |
1 |
|
|
T1 |
30 |
|
T7 |
10 |
|
T32 |
28 |
halfword_access |
19610 |
1 |
|
|
T1 |
28 |
|
T7 |
2 |
|
T32 |
28 |
byte_access |
19838 |
1 |
|
|
T1 |
34 |
|
T7 |
12 |
|
T32 |
36 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
5785338 |
1 |
|
|
T1 |
12706 |
|
T3 |
1260 |
|
T7 |
2449 |
auto[0] |
triple_byte_access |
9766 |
1 |
|
|
T1 |
15 |
|
T7 |
5 |
|
T32 |
14 |
auto[0] |
halfword_access |
9805 |
1 |
|
|
T1 |
14 |
|
T7 |
1 |
|
T32 |
14 |
auto[0] |
byte_access |
9919 |
1 |
|
|
T1 |
17 |
|
T7 |
6 |
|
T32 |
18 |
auto[1] |
word_access |
5785327 |
1 |
|
|
T1 |
12706 |
|
T3 |
1260 |
|
T7 |
2449 |
auto[1] |
triple_byte_access |
9766 |
1 |
|
|
T1 |
15 |
|
T7 |
5 |
|
T32 |
14 |
auto[1] |
halfword_access |
9805 |
1 |
|
|
T1 |
14 |
|
T7 |
1 |
|
T32 |
14 |
auto[1] |
byte_access |
9919 |
1 |
|
|
T1 |
17 |
|
T7 |
6 |
|
T32 |
18 |