Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	2	16	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	2	16	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T115	4		T116	7		T117	7
all_values[1]	281	1			T115	4		T116	7		T117	7
all_values[2]	281	1			T115	4		T116	7		T117	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

432

1

T115

7

T116

11

T117

8

auto[1]

411

1

T115

5

T116

10

T117

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

423

1

T115

4

T116

14

T117

14

auto[1]

420

1

T115

8

T116

7

T117

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

513

1

T115

6

T116

16

T117

15

auto[1]

330

1

T115

6

T116

5

T117

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	2	16	88.89	2
Automatically Generated Cross Bins	18	2	16	88.89	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

62

1

T116

2

T117

3

T144

1

all_values[0]

auto[0]

auto[0]

auto[1]

16

1

T145

1

T146

1

T147

1

all_values[0]

auto[0]

auto[1]

auto[0]

69

1

T116

3

T117

1

T144

4

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T115

1

T116

1

T117

1

all_values[0]

auto[1]

auto[0]

auto[1]

50

1

T115

1

T116

1

T145

1

all_values[0]

auto[1]

auto[1]

auto[1]

60

1

T115

2

T117

2

T144

1

all_values[1]

auto[0]

auto[0]

auto[0]

98

1

T115

1

T116

4

T117

1

all_values[1]

auto[0]

auto[1]

auto[0]

67

1

T115

2

T117

2

T144

3

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T115

1

T116

2

T117

1

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T116

1

T117

3

T144

2

all_values[2]

auto[0]

auto[0]

auto[0]

56

1

T115

1

T116

2

T117

3

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T115

1

T144

2

T148

2

all_values[2]

auto[0]

auto[1]

auto[0]

71

1

T116

3

T117

4

T144

1

all_values[2]

auto[0]

auto[1]

auto[1]

21

1

T116

1

T144

1

T148

3

all_values[2]

auto[1]

auto[0]

auto[1]

55

1

T115

2

T144

2

T148

2

all_values[2]

auto[1]

auto[1]

auto[1]

49

1

T116

1

T144

1

T149

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal