Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17703325	1			T1	1974		T2	3547		T3	3204
all_values[1]	17703325	1			T1	1974		T2	3547		T3	3204
all_values[2]	17703325	1			T1	1974		T2	3547		T3	3204

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

537331

1

T1

18

T2

3

T3

13

auto[1]

52572644

1

T1

5904

T2

10638

T3

9599

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52886745

1

T1

5445

T2

10002

T3

8988

auto[1]

223230

1

T1

477

T2

639

T3

624

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	208748	1			T1	5		T3	1		T43	8
all_values[0]	auto[0]	auto[1]	1308	1			T1	6		T3	2		T43	8
all_values[0]	auto[1]	auto[0]	17420167	1			T1	1810		T2	3334		T3	2995
all_values[0]	auto[1]	auto[1]	73102	1			T1	153		T2	213		T3	206
all_values[1]	auto[0]	auto[0]	145538	1			T1	3		T3	1		T29	38
all_values[1]	auto[0]	auto[1]	1038	1			T1	4		T3	2		T29	4
all_values[1]	auto[1]	auto[0]	17483377	1			T1	1812		T2	3334		T3	2995
all_values[1]	auto[1]	auto[1]	73372	1			T1	155		T2	213		T3	206
all_values[2]	auto[0]	auto[0]	179752	1			T2	2		T3	4		T29	10
all_values[2]	auto[0]	auto[1]	947	1			T2	1		T3	3		T29	1
all_values[2]	auto[1]	auto[0]	17449163	1			T1	1815		T2	3332		T3	2992
all_values[2]	auto[1]	auto[1]	73463	1			T1	159		T2	212		T3	205