Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	357	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	2871	1			T75	18		T139	6		T68	11
len_5001_7500	6969	1			T75	18		T139	38		T68	7
len_2501_5000	1641	1			T75	8		T139	4		T69	4
len_1025_2500	932	1			T75	6		T139	5		T69	1
len_769_1024	5516	1			T20	4		T9	2		T10	6
len_513_768	5995	1			T20	10		T9	3		T10	3
len_257_512	6226	1			T20	11		T9	1		T10	3
len_0_256	19051	1			T1	105		T2	145		T3	137
len_keccak_block_sizes[72]	34	1			T1	1		T2	1		T3	1
len_keccak_block_sizes[104]	32	1			T1	1		T2	1		T3	1
len_keccak_block_sizes[136]	27	1			T2	1		T3	1		T51	1
len_keccak_block_sizes[144]	27	1			T2	1		T51	1		T106	1
len_keccak_block_sizes[168]	18	1			T51	1		T106	1		T74	1
len_1	60	1			T1	1		T2	1		T3	1
len_0	500	1			T1	1		T2	1		T3	1