Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17703325	1			T1	1974		T2	3547		T3	3204
all_pins[1]	17703325	1			T1	1974		T2	3547		T3	3204
all_pins[2]	17703325	1			T1	1974		T2	3547		T3	3204

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52681051	1			T1	5769		T2	10428		T3	9406
values[0x1]	428924	1			T1	153		T2	213		T3	206
transitions[0x0=>0x1]	426543	1			T1	153		T2	213		T3	206
transitions[0x1=>0x0]	426570	1			T1	153		T2	213		T3	206

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17630223	1			T1	1821		T2	3334		T3	2998
all_pins[0]	values[0x1]	73102	1			T1	153		T2	213		T3	206
all_pins[0]	transitions[0x0=>0x1]	73090	1			T1	153		T2	213		T3	206
all_pins[0]	transitions[0x1=>0x0]	5374	1			T11	1		T16	1		T12	32
all_pins[1]	values[0x0]	17697939	1			T1	1974		T2	3547		T3	3204
all_pins[1]	values[0x1]	5386	1			T11	1		T16	1		T12	32
all_pins[1]	transitions[0x0=>0x1]	5127	1			T16	1		T12	32		T24	57
all_pins[1]	transitions[0x1=>0x0]	350177	1			T11	10763		T32	5397		T17	511
all_pins[2]	values[0x0]	17352889	1			T1	1974		T2	3547		T3	3204
all_pins[2]	values[0x1]	350436	1			T11	10764		T32	5397		T17	511
all_pins[2]	transitions[0x0=>0x1]	348326	1			T11	10697		T32	5364		T17	511
all_pins[2]	transitions[0x1=>0x0]	71019	1			T1	153		T2	213		T3	206