Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6528736 |
1 |
|
|
T1 |
1260 |
|
T2 |
1015 |
|
T3 |
1096 |
auto[1] |
6528692 |
1 |
|
|
T1 |
1260 |
|
T2 |
1015 |
|
T3 |
1096 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
12990696 |
1 |
|
|
T1 |
2520 |
|
T2 |
2030 |
|
T3 |
2192 |
triple_byte_access |
22248 |
1 |
|
|
T20 |
14 |
|
T29 |
74 |
|
T9 |
2 |
halfword_access |
22228 |
1 |
|
|
T20 |
14 |
|
T29 |
110 |
|
T9 |
2 |
byte_access |
22256 |
1 |
|
|
T20 |
14 |
|
T29 |
98 |
|
T9 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
6495370 |
1 |
|
|
T1 |
1260 |
|
T2 |
1015 |
|
T3 |
1096 |
auto[0] |
triple_byte_access |
11124 |
1 |
|
|
T20 |
7 |
|
T29 |
37 |
|
T9 |
1 |
auto[0] |
halfword_access |
11114 |
1 |
|
|
T20 |
7 |
|
T29 |
55 |
|
T9 |
1 |
auto[0] |
byte_access |
11128 |
1 |
|
|
T20 |
7 |
|
T29 |
49 |
|
T9 |
2 |
auto[1] |
word_access |
6495326 |
1 |
|
|
T1 |
1260 |
|
T2 |
1015 |
|
T3 |
1096 |
auto[1] |
triple_byte_access |
11124 |
1 |
|
|
T20 |
7 |
|
T29 |
37 |
|
T9 |
1 |
auto[1] |
halfword_access |
11114 |
1 |
|
|
T20 |
7 |
|
T29 |
55 |
|
T9 |
1 |
auto[1] |
byte_access |
11128 |
1 |
|
|
T20 |
7 |
|
T29 |
49 |
|
T9 |
2 |