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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.28 97.89 92.55 99.89 77.46 95.53 98.89 97.73


Total test records in report: 880
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T761 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3594463571 Aug 21 02:10:13 PM UTC 24 Aug 21 02:10:19 PM UTC 24 51697895 ps
T762 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.369944659 Aug 21 02:10:17 PM UTC 24 Aug 21 02:10:22 PM UTC 24 154949332 ps
T166 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3515100222 Aug 21 02:10:13 PM UTC 24 Aug 21 02:10:22 PM UTC 24 196553474 ps
T175 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1909551331 Aug 21 02:10:19 PM UTC 24 Aug 21 02:10:22 PM UTC 24 65447501 ps
T763 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3852400601 Aug 21 02:10:18 PM UTC 24 Aug 21 02:10:23 PM UTC 24 66708592 ps
T764 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.154984542 Aug 21 02:10:19 PM UTC 24 Aug 21 02:10:24 PM UTC 24 88926011 ps
T765 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1128843923 Aug 21 02:10:23 PM UTC 24 Aug 21 02:10:26 PM UTC 24 10787862 ps
T766 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1894361968 Aug 21 02:10:19 PM UTC 24 Aug 21 02:10:26 PM UTC 24 226214768 ps
T767 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2346450099 Aug 21 02:10:24 PM UTC 24 Aug 21 02:10:27 PM UTC 24 26026923 ps
T768 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1301040985 Aug 21 02:10:24 PM UTC 24 Aug 21 02:10:28 PM UTC 24 42687076 ps
T769 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1643532144 Aug 21 02:10:20 PM UTC 24 Aug 21 02:10:28 PM UTC 24 2184345329 ps
T770 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3378953196 Aug 21 02:10:25 PM UTC 24 Aug 21 02:10:29 PM UTC 24 42624255 ps
T771 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1967300970 Aug 21 02:10:24 PM UTC 24 Aug 21 02:10:29 PM UTC 24 343970637 ps
T772 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1380097309 Aug 21 02:10:26 PM UTC 24 Aug 21 02:10:30 PM UTC 24 74313132 ps
T773 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2101299635 Aug 21 02:10:25 PM UTC 24 Aug 21 02:10:30 PM UTC 24 209909385 ps
T774 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.804644350 Aug 21 02:10:29 PM UTC 24 Aug 21 02:10:31 PM UTC 24 19121335 ps
T775 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3878794897 Aug 21 02:10:29 PM UTC 24 Aug 21 02:10:32 PM UTC 24 26582800 ps
T776 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1926073336 Aug 21 02:10:30 PM UTC 24 Aug 21 02:10:33 PM UTC 24 66619144 ps
T777 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.38411222 Aug 21 02:10:30 PM UTC 24 Aug 21 02:10:34 PM UTC 24 98812868 ps
T778 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.174297450 Aug 21 02:10:32 PM UTC 24 Aug 21 02:10:35 PM UTC 24 59735847 ps
T779 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1376343353 Aug 21 02:10:30 PM UTC 24 Aug 21 02:10:35 PM UTC 24 75877402 ps
T780 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2554243946 Aug 21 02:10:31 PM UTC 24 Aug 21 02:10:36 PM UTC 24 92705441 ps
T781 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1699811268 Aug 21 02:10:34 PM UTC 24 Aug 21 02:10:37 PM UTC 24 28021578 ps
T782 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.605605453 Aug 21 02:10:31 PM UTC 24 Aug 21 02:10:37 PM UTC 24 145393953 ps
T168 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3323243217 Aug 21 02:10:27 PM UTC 24 Aug 21 02:10:38 PM UTC 24 386465385 ps
T783 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.620461700 Aug 21 02:10:35 PM UTC 24 Aug 21 02:10:38 PM UTC 24 162693048 ps
T784 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2163857334 Aug 21 02:10:34 PM UTC 24 Aug 21 02:10:38 PM UTC 24 581554627 ps
T171 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.4207516766 Aug 21 02:10:32 PM UTC 24 Aug 21 02:10:39 PM UTC 24 105378794 ps
T785 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2127314929 Aug 21 02:10:36 PM UTC 24 Aug 21 02:10:40 PM UTC 24 48519449 ps
T786 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2560981044 Aug 21 02:10:39 PM UTC 24 Aug 21 02:10:42 PM UTC 24 27743562 ps
T787 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1702308050 Aug 21 02:10:36 PM UTC 24 Aug 21 02:10:42 PM UTC 24 510855534 ps
T788 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2770597416 Aug 21 02:10:39 PM UTC 24 Aug 21 02:10:42 PM UTC 24 26504585 ps
T789 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.717097667 Aug 21 02:10:40 PM UTC 24 Aug 21 02:10:43 PM UTC 24 88303962 ps
T790 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2639475866 Aug 21 02:10:39 PM UTC 24 Aug 21 02:10:44 PM UTC 24 35670058 ps
T791 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1813063579 Aug 21 02:10:39 PM UTC 24 Aug 21 02:10:44 PM UTC 24 129890879 ps
T169 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.400329417 Aug 21 02:10:37 PM UTC 24 Aug 21 02:10:44 PM UTC 24 135959058 ps
T792 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2325844434 Aug 21 02:10:40 PM UTC 24 Aug 21 02:10:44 PM UTC 24 103156557 ps
T793 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2737896405 Aug 21 02:10:37 PM UTC 24 Aug 21 02:10:45 PM UTC 24 633199455 ps
T157 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3325510882 Aug 21 02:10:43 PM UTC 24 Aug 21 02:10:47 PM UTC 24 115762405 ps
T794 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3203277810 Aug 21 02:10:41 PM UTC 24 Aug 21 02:10:47 PM UTC 24 817800741 ps
T795 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.749777551 Aug 21 02:10:43 PM UTC 24 Aug 21 02:10:47 PM UTC 24 15866996 ps
T796 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3548479000 Aug 21 02:10:45 PM UTC 24 Aug 21 02:10:49 PM UTC 24 37261533 ps
T797 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1569048101 Aug 21 02:10:45 PM UTC 24 Aug 21 02:10:49 PM UTC 24 26547973 ps
T798 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.549796348 Aug 21 02:10:43 PM UTC 24 Aug 21 02:10:50 PM UTC 24 2276558177 ps
T799 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.112349547 Aug 21 02:10:45 PM UTC 24 Aug 21 02:10:50 PM UTC 24 69068836 ps
T800 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1265674794 Aug 21 02:10:47 PM UTC 24 Aug 21 02:10:51 PM UTC 24 24893679 ps
T801 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1711122502 Aug 21 02:10:47 PM UTC 24 Aug 21 02:10:51 PM UTC 24 66007573 ps
T802 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.742389105 Aug 21 02:10:46 PM UTC 24 Aug 21 02:10:52 PM UTC 24 186046216 ps
T803 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3107367395 Aug 21 02:10:46 PM UTC 24 Aug 21 02:10:52 PM UTC 24 270648239 ps
T804 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2431712984 Aug 21 02:10:49 PM UTC 24 Aug 21 02:10:53 PM UTC 24 26685809 ps
T805 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2218198200 Aug 21 02:10:49 PM UTC 24 Aug 21 02:10:53 PM UTC 24 45902034 ps
T806 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2491975940 Aug 21 02:10:46 PM UTC 24 Aug 21 02:10:53 PM UTC 24 137304321 ps
T807 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2672491113 Aug 21 02:10:50 PM UTC 24 Aug 21 02:10:54 PM UTC 24 155329136 ps
T158 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1659076349 Aug 21 02:10:52 PM UTC 24 Aug 21 02:10:55 PM UTC 24 17214925 ps
T808 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3659741001 Aug 21 02:10:51 PM UTC 24 Aug 21 02:10:55 PM UTC 24 24036152 ps
T809 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2916481032 Aug 21 02:10:51 PM UTC 24 Aug 21 02:10:55 PM UTC 24 211704436 ps
T810 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2616190975 Aug 21 02:10:52 PM UTC 24 Aug 21 02:10:55 PM UTC 24 395281488 ps
T811 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1565748442 Aug 21 02:10:51 PM UTC 24 Aug 21 02:10:56 PM UTC 24 166896880 ps
T812 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1591484171 Aug 21 02:10:54 PM UTC 24 Aug 21 02:10:57 PM UTC 24 163010435 ps
T813 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2682343382 Aug 21 02:10:54 PM UTC 24 Aug 21 02:10:57 PM UTC 24 30997130 ps
T814 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2797276780 Aug 21 02:10:54 PM UTC 24 Aug 21 02:10:57 PM UTC 24 118696976 ps
T815 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3007106581 Aug 21 02:10:54 PM UTC 24 Aug 21 02:10:58 PM UTC 24 69576724 ps
T816 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2690664683 Aug 21 02:10:56 PM UTC 24 Aug 21 02:10:59 PM UTC 24 15189094 ps
T173 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2573174232 Aug 21 02:10:55 PM UTC 24 Aug 21 02:10:59 PM UTC 24 176605201 ps
T817 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1964784673 Aug 21 02:10:56 PM UTC 24 Aug 21 02:10:59 PM UTC 24 14290535 ps
T818 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2000034002 Aug 21 02:10:56 PM UTC 24 Aug 21 02:11:00 PM UTC 24 35464602 ps
T819 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.840429480 Aug 21 02:10:58 PM UTC 24 Aug 21 02:11:00 PM UTC 24 70789808 ps
T820 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2575120150 Aug 21 02:10:56 PM UTC 24 Aug 21 02:11:00 PM UTC 24 69806261 ps
T821 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.591755119 Aug 21 02:10:58 PM UTC 24 Aug 21 02:11:01 PM UTC 24 58625197 ps
T822 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2313706139 Aug 21 02:10:58 PM UTC 24 Aug 21 02:11:02 PM UTC 24 74581337 ps
T823 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3890982692 Aug 21 02:10:55 PM UTC 24 Aug 21 02:11:02 PM UTC 24 712493577 ps
T824 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4051411705 Aug 21 02:10:59 PM UTC 24 Aug 21 02:11:02 PM UTC 24 27769427 ps
T825 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3337369460 Aug 21 02:10:58 PM UTC 24 Aug 21 02:11:03 PM UTC 24 426409898 ps
T826 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.728150706 Aug 21 02:10:59 PM UTC 24 Aug 21 02:11:03 PM UTC 24 183432437 ps
T827 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4068172507 Aug 21 02:11:00 PM UTC 24 Aug 21 02:11:03 PM UTC 24 39647148 ps
T828 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2581963775 Aug 21 02:10:59 PM UTC 24 Aug 21 02:11:04 PM UTC 24 90672848 ps
T829 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3782577938 Aug 21 02:11:02 PM UTC 24 Aug 21 02:11:04 PM UTC 24 13885597 ps
T830 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1229723508 Aug 21 02:11:01 PM UTC 24 Aug 21 02:11:06 PM UTC 24 484390629 ps
T170 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3722075469 Aug 21 02:10:58 PM UTC 24 Aug 21 02:11:06 PM UTC 24 193954863 ps
T831 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.4119315128 Aug 21 02:11:03 PM UTC 24 Aug 21 02:11:06 PM UTC 24 16927803 ps
T832 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2877145817 Aug 21 02:11:04 PM UTC 24 Aug 21 02:11:07 PM UTC 24 30515276 ps
T172 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.12191998 Aug 21 02:11:02 PM UTC 24 Aug 21 02:11:07 PM UTC 24 78708408 ps
T833 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2472580915 Aug 21 02:11:01 PM UTC 24 Aug 21 02:11:07 PM UTC 24 461074681 ps
T834 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1348383118 Aug 21 02:11:03 PM UTC 24 Aug 21 02:11:07 PM UTC 24 312853926 ps
T835 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.821518980 Aug 21 02:11:04 PM UTC 24 Aug 21 02:11:07 PM UTC 24 83873923 ps
T836 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1507561275 Aug 21 02:11:05 PM UTC 24 Aug 21 02:11:07 PM UTC 24 18857780 ps
T837 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.637606393 Aug 21 02:11:04 PM UTC 24 Aug 21 02:11:08 PM UTC 24 171741863 ps
T838 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2091086639 Aug 21 02:11:04 PM UTC 24 Aug 21 02:11:10 PM UTC 24 250563159 ps
T839 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3541802798 Aug 21 02:11:07 PM UTC 24 Aug 21 02:11:10 PM UTC 24 20046314 ps
T840 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3547481850 Aug 21 02:11:07 PM UTC 24 Aug 21 02:11:10 PM UTC 24 39717810 ps
T841 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.461856720 Aug 21 02:11:07 PM UTC 24 Aug 21 02:11:11 PM UTC 24 41229183 ps
T842 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3987106639 Aug 21 02:11:08 PM UTC 24 Aug 21 02:11:11 PM UTC 24 38987208 ps
T843 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1225397962 Aug 21 02:11:09 PM UTC 24 Aug 21 02:11:11 PM UTC 24 13775882 ps
T844 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4014639138 Aug 21 02:11:09 PM UTC 24 Aug 21 02:11:12 PM UTC 24 17969645 ps
T845 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.299185811 Aug 21 02:11:07 PM UTC 24 Aug 21 02:11:12 PM UTC 24 48183576 ps
T846 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3230666161 Aug 21 02:11:05 PM UTC 24 Aug 21 02:11:12 PM UTC 24 254504462 ps
T847 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.1404725366 Aug 21 02:11:10 PM UTC 24 Aug 21 02:11:13 PM UTC 24 13497084 ps
T848 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2354071245 Aug 21 02:11:10 PM UTC 24 Aug 21 02:11:13 PM UTC 24 22070775 ps
T849 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3440854377 Aug 21 02:11:09 PM UTC 24 Aug 21 02:11:13 PM UTC 24 355353456 ps
T850 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.153506407 Aug 21 02:11:10 PM UTC 24 Aug 21 02:11:13 PM UTC 24 71054525 ps
T851 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.448868203 Aug 21 02:11:12 PM UTC 24 Aug 21 02:11:14 PM UTC 24 43388120 ps
T852 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3898545453 Aug 21 02:11:09 PM UTC 24 Aug 21 02:11:14 PM UTC 24 199996102 ps
T853 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3165821959 Aug 21 02:11:12 PM UTC 24 Aug 21 02:11:14 PM UTC 24 16171180 ps
T854 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2519755825 Aug 21 02:11:12 PM UTC 24 Aug 21 02:11:14 PM UTC 24 32193276 ps
T855 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2805204016 Aug 21 02:11:12 PM UTC 24 Aug 21 02:11:14 PM UTC 24 113634500 ps
T856 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3313494161 Aug 21 02:11:13 PM UTC 24 Aug 21 02:11:16 PM UTC 24 71367110 ps
T857 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2030392938 Aug 21 02:11:13 PM UTC 24 Aug 21 02:11:16 PM UTC 24 21346445 ps
T858 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2231066404 Aug 21 02:11:13 PM UTC 24 Aug 21 02:11:16 PM UTC 24 41725038 ps
T859 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.44617806 Aug 21 02:11:13 PM UTC 24 Aug 21 02:11:16 PM UTC 24 17226644 ps
T860 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.728932573 Aug 21 02:11:09 PM UTC 24 Aug 21 02:11:16 PM UTC 24 104650034 ps
T861 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3602045002 Aug 21 02:11:14 PM UTC 24 Aug 21 02:11:16 PM UTC 24 16551072 ps
T862 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1025224846 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:17 PM UTC 24 14135412 ps
T863 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.645763092 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:17 PM UTC 24 57839795 ps
T864 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.723271524 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:17 PM UTC 24 64574757 ps
T865 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2389452158 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:18 PM UTC 24 38485598 ps
T866 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2099387324 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:18 PM UTC 24 39647253 ps
T867 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3630160424 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:18 PM UTC 24 50166174 ps
T868 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2823722418 Aug 21 02:11:15 PM UTC 24 Aug 21 02:11:18 PM UTC 24 18350649 ps
T869 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1614708175 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 40518224 ps
T870 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.955861451 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 37385629 ps
T871 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3891251198 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 26759048 ps
T872 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4065490944 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 55954519 ps
T873 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1669344666 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 15325221 ps
T874 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1228781812 Aug 21 02:11:17 PM UTC 24 Aug 21 02:11:19 PM UTC 24 126220300 ps
T875 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1253768276 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 13463935 ps
T876 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2164972495 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 40703486 ps
T877 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.929403620 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 14641292 ps
T878 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.546365870 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 48329874 ps
T879 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3823861457 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 61727577 ps
T880 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1147652855 Aug 21 02:11:19 PM UTC 24 Aug 21 02:11:21 PM UTC 24 14405832 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1940844462
Short name T20
Test name
Test status
Simulation time 6222574771 ps
CPU time 124.55 seconds
Started Aug 21 12:38:11 PM UTC 24
Finished Aug 21 12:40:19 PM UTC 24
Peak memory 295212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194084
4462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.
1940844462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.4217232298
Short name T12
Test name
Test status
Simulation time 5502573910 ps
CPU time 355.47 seconds
Started Aug 21 12:40:18 PM UTC 24
Finished Aug 21 12:46:19 PM UTC 24
Peak memory 323844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42172322
98 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entr
opy_refresh.4217232298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.1316397255
Short name T115
Test name
Test status
Simulation time 819849663 ps
CPU time 4.55 seconds
Started Aug 21 02:08:30 PM UTC 24
Finished Aug 21 02:08:36 PM UTC 24
Peak memory 225752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1316
397255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_
intg_err.1316397255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2289796299
Short name T9
Test name
Test status
Simulation time 698564487 ps
CPU time 24.39 seconds
Started Aug 21 12:40:41 PM UTC 24
Finished Aug 21 12:41:07 PM UTC 24
Peak memory 262480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289796299 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2289796299 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.3934391129
Short name T40
Test name
Test status
Simulation time 8398607698 ps
CPU time 113.11 seconds
Started Aug 21 12:45:37 PM UTC 24
Finished Aug 21 12:47:33 PM UTC 24
Peak memory 315700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3934391129 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3934391129
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.966471980
Short name T68
Test name
Test status
Simulation time 5072909375 ps
CPU time 479.39 seconds
Started Aug 21 12:52:43 PM UTC 24
Finished Aug 21 01:00:51 PM UTC 24
Peak memory 332496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/
lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966471980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.966471980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.1395550461
Short name T8
Test name
Test status
Simulation time 703300775 ps
CPU time 6.52 seconds
Started Aug 21 12:44:06 PM UTC 24
Finished Aug 21 12:44:14 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395550461 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1395550461 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_error.1980562982
Short name T17
Test name
Test status
Simulation time 70431233757 ps
CPU time 555.11 seconds
Started Aug 21 12:40:22 PM UTC 24
Finished Aug 21 12:49:45 PM UTC 24
Peak memory 565560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980562982 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1980562982 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.101721392
Short name T16
Test name
Test status
Simulation time 3766063516 ps
CPU time 36.99 seconds
Started Aug 21 12:44:54 PM UTC 24
Finished Aug 21 12:45:34 PM UTC 24
Peak memory 250196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=101721392 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.101721392 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2317964516
Short name T99
Test name
Test status
Simulation time 29069603 ps
CPU time 1.57 seconds
Started Aug 21 02:09:26 PM UTC 24
Finished Aug 21 02:09:29 PM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2317964516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.km
ac_shadow_reg_errors.2317964516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.2410863930
Short name T5
Test name
Test status
Simulation time 35905128894 ps
CPU time 118.08 seconds
Started Aug 21 12:44:41 PM UTC 24
Finished Aug 21 12:46:42 PM UTC 24
Peak memory 234012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410863930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.241086393
0 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.3178387930
Short name T58
Test name
Test status
Simulation time 38322650 ps
CPU time 1.99 seconds
Started Aug 21 01:26:57 PM UTC 24
Finished Aug 21 01:27:00 PM UTC 24
Peak memory 231376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178387930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3178387930 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3012402063
Short name T44
Test name
Test status
Simulation time 24570133 ps
CPU time 1.14 seconds
Started Aug 21 12:40:36 PM UTC 24
Finished Aug 21 12:40:38 PM UTC 24
Peak memory 227380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012402063 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.301
2402063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2657370640
Short name T155
Test name
Test status
Simulation time 23757674 ps
CPU time 1.21 seconds
Started Aug 21 02:09:48 PM UTC 24
Finished Aug 21 02:09:50 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2657370640 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.26573
70640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.944341181
Short name T62
Test name
Test status
Simulation time 1092655379 ps
CPU time 3.38 seconds
Started Aug 21 01:15:46 PM UTC 24
Finished Aug 21 01:15:50 PM UTC 24
Peak memory 234536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944341181 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.944341181 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.2611723165
Short name T45
Test name
Test status
Simulation time 39703884 ps
CPU time 1.34 seconds
Started Aug 21 12:40:38 PM UTC 24
Finished Aug 21 12:40:40 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611723165 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2
611723165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.1614851903
Short name T74
Test name
Test status
Simulation time 9474578480 ps
CPU time 172.18 seconds
Started Aug 21 12:43:16 PM UTC 24
Finished Aug 21 12:46:11 PM UTC 24
Peak memory 291060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1614851903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1614851903 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.988753177
Short name T78
Test name
Test status
Simulation time 128432842 ps
CPU time 2.98 seconds
Started Aug 21 01:45:37 PM UTC 24
Finished Aug 21 01:45:42 PM UTC 24
Peak memory 234752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988753177 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.988753177 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.3758055475
Short name T61
Test name
Test status
Simulation time 33356595 ps
CPU time 2.01 seconds
Started Aug 21 01:55:13 PM UTC 24
Finished Aug 21 01:55:16 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3758055475 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3758055475 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.2866132315
Short name T142
Test name
Test status
Simulation time 11013240893 ps
CPU time 470.36 seconds
Started Aug 21 01:01:28 PM UTC 24
Finished Aug 21 01:09:25 PM UTC 24
Peak memory 313988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2866132315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_stress_all.2866132315 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.2739239512
Short name T134
Test name
Test status
Simulation time 149217907 ps
CPU time 2.45 seconds
Started Aug 21 02:08:28 PM UTC 24
Finished Aug 21 02:08:32 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=2739239512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
mac_mem_partial_access.2739239512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.1809406654
Short name T29
Test name
Test status
Simulation time 4485911534 ps
CPU time 131.59 seconds
Started Aug 21 12:38:06 PM UTC 24
Finished Aug 21 12:40:21 PM UTC 24
Peak memory 235832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1809406654 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1809406654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3048150861
Short name T98
Test name
Test status
Simulation time 568807711 ps
CPU time 2.21 seconds
Started Aug 21 02:08:48 PM UTC 24
Finished Aug 21 02:08:52 PM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3048150861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.km
ac_shadow_reg_errors.3048150861 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.2309473756
Short name T42
Test name
Test status
Simulation time 4153166264 ps
CPU time 41.38 seconds
Started Aug 21 12:48:46 PM UTC 24
Finished Aug 21 12:49:31 PM UTC 24
Peak memory 268692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2309473756 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2309473756 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.2712381467
Short name T93
Test name
Test status
Simulation time 37819164 ps
CPU time 1.96 seconds
Started Aug 21 01:25:51 PM UTC 24
Finished Aug 21 01:25:54 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712381467 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2712381467 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.1283615126
Short name T53
Test name
Test status
Simulation time 94004967 ps
CPU time 1.99 seconds
Started Aug 21 01:49:42 PM UTC 24
Finished Aug 21 01:49:45 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1283615126 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.1283615126 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.2529872184
Short name T46
Test name
Test status
Simulation time 26518356 ps
CPU time 1.31 seconds
Started Aug 21 12:41:07 PM UTC 24
Finished Aug 21 12:41:10 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529872184
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.25298
72184 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_error.1991345087
Short name T151
Test name
Test status
Simulation time 14154443078 ps
CPU time 331.88 seconds
Started Aug 21 01:00:58 PM UTC 24
Finished Aug 21 01:06:35 PM UTC 24
Peak memory 340292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991345087 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1991345087 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.3722075469
Short name T170
Test name
Test status
Simulation time 193954863 ps
CPU time 7.01 seconds
Started Aug 21 02:10:58 PM UTC 24
Finished Aug 21 02:11:06 PM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3722
075469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl
_intg_err.3722075469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.454749239
Short name T90
Test name
Test status
Simulation time 25639321061 ps
CPU time 209.91 seconds
Started Aug 21 01:22:37 PM UTC 24
Finished Aug 21 01:26:10 PM UTC 24
Peak memory 338176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45474923
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entr
opy_refresh.454749239 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2272090507
Short name T120
Test name
Test status
Simulation time 32624584 ps
CPU time 1.2 seconds
Started Aug 21 02:08:56 PM UTC 24
Finished Aug 21 02:08:59 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2272090507 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.22720
90507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.400329417
Short name T169
Test name
Test status
Simulation time 135959058 ps
CPU time 4.98 seconds
Started Aug 21 02:10:37 PM UTC 24
Finished Aug 21 02:10:44 PM UTC 24
Peak memory 225580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003
29417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_
intg_err.400329417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.4040213174
Short name T178
Test name
Test status
Simulation time 39519739825 ps
CPU time 414.47 seconds
Started Aug 21 12:47:04 PM UTC 24
Finished Aug 21 12:54:06 PM UTC 24
Peak memory 270500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4040213174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.4040213174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2087537467
Short name T11
Test name
Test status
Simulation time 18542635934 ps
CPU time 219.19 seconds
Started Aug 21 12:40:20 PM UTC 24
Finished Aug 21 12:44:03 PM UTC 24
Peak memory 402048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087537467 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2087537467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2101299635
Short name T773
Test name
Test status
Simulation time 209909385 ps
CPU time 3.26 seconds
Started Aug 21 02:10:25 PM UTC 24
Finished Aug 21 02:10:30 PM UTC 24
Peak memory 230016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2101299635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.kmac_shadow_reg_errors_with_csr_rw.2101299635 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3325510882
Short name T157
Test name
Test status
Simulation time 115762405 ps
CPU time 1.22 seconds
Started Aug 21 02:10:43 PM UTC 24
Finished Aug 21 02:10:47 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3325510882 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3325
510882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.2905167062
Short name T597
Test name
Test status
Simulation time 88138709834 ps
CPU time 2794.53 seconds
Started Aug 21 01:13:47 PM UTC 24
Finished Aug 21 02:00:54 PM UTC 24
Peak memory 1327832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2905167062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 11.kmac_stress_all.2905167062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_app.2604519200
Short name T10
Test name
Test status
Simulation time 2344523338 ps
CPU time 51.84 seconds
Started Aug 21 12:40:17 PM UTC 24
Finished Aug 21 12:41:10 PM UTC 24
Peak memory 272672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26045192
00 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2604519200 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_error.1602104026
Short name T35
Test name
Test status
Simulation time 68853265080 ps
CPU time 556.3 seconds
Started Aug 21 01:26:32 PM UTC 24
Finished Aug 21 01:35:55 PM UTC 24
Peak memory 596220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1602104026 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1602104026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_app.1011107924
Short name T25
Test name
Test status
Simulation time 6209093714 ps
CPU time 338.55 seconds
Started Aug 21 12:43:45 PM UTC 24
Finished Aug 21 12:49:29 PM UTC 24
Peak memory 352696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10111079
24 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1011107924 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.4068876377
Short name T146
Test name
Test status
Simulation time 506103450 ps
CPU time 13.6 seconds
Started Aug 21 02:08:39 PM UTC 24
Finished Aug 21 02:08:54 PM UTC 24
Peak memory 225608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068876
377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_al
iasing.4068876377 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.387021822
Short name T720
Test name
Test status
Simulation time 165221072 ps
CPU time 10.73 seconds
Started Aug 21 02:08:37 PM UTC 24
Finished Aug 21 02:08:48 PM UTC 24
Peak memory 225472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870218
22 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit
_bash.387021822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.4289201594
Short name T119
Test name
Test status
Simulation time 113380501 ps
CPU time 1.71 seconds
Started Aug 21 02:08:35 PM UTC 24
Finished Aug 21 02:08:38 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4289201
594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw
_reset.4289201594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.961518342
Short name T122
Test name
Test status
Simulation time 27816498 ps
CPU time 2.28 seconds
Started Aug 21 02:08:44 PM UTC 24
Finished Aug 21 02:08:47 PM UTC 24
Peak memory 229656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=961518342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.961518342 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.846270978
Short name T174
Test name
Test status
Simulation time 61267416 ps
CPU time 1.64 seconds
Started Aug 21 02:08:37 PM UTC 24
Finished Aug 21 02:08:39 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=846270978 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.846270
978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.4266702785
Short name T118
Test name
Test status
Simulation time 70650392 ps
CPU time 1.16 seconds
Started Aug 21 02:08:32 PM UTC 24
Finished Aug 21 02:08:34 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4266702785 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.42667
02785 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.687317029
Short name T718
Test name
Test status
Simulation time 33819994 ps
CPU time 1.08 seconds
Started Aug 21 02:08:27 PM UTC 24
Finished Aug 21 02:08:29 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6873170
29 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_wal
k.687317029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.4207705200
Short name T719
Test name
Test status
Simulation time 45742557 ps
CPU time 2.1 seconds
Started Aug 21 02:08:40 PM UTC 24
Finished Aug 21 02:08:43 PM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4207705200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.kmac_same_csr_outstanding.4207705200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3530117459
Short name T96
Test name
Test status
Simulation time 253063436 ps
CPU time 1.74 seconds
Started Aug 21 02:08:21 PM UTC 24
Finished Aug 21 02:08:24 PM UTC 24
Peak memory 225308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3530117459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.km
ac_shadow_reg_errors.3530117459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2151221422
Short name T97
Test name
Test status
Simulation time 177296565 ps
CPU time 3.23 seconds
Started Aug 21 02:08:25 PM UTC 24
Finished Aug 21 02:08:29 PM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2151221422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.kmac_shadow_reg_errors_with_csr_rw.2151221422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.1857912342
Short name T121
Test name
Test status
Simulation time 58670927 ps
CPU time 3.97 seconds
Started Aug 21 02:08:30 PM UTC 24
Finished Aug 21 02:08:35 PM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1857912342 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.18579
12342 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.2191680659
Short name T726
Test name
Test status
Simulation time 526759634 ps
CPU time 10.93 seconds
Started Aug 21 02:09:02 PM UTC 24
Finished Aug 21 02:09:14 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2191680
659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_al
iasing.2191680659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2100062769
Short name T727
Test name
Test status
Simulation time 947961362 ps
CPU time 14.49 seconds
Started Aug 21 02:09:00 PM UTC 24
Finished Aug 21 02:09:16 PM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100062
769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bi
t_bash.2100062769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3759873774
Short name T722
Test name
Test status
Simulation time 38864754 ps
CPU time 1.49 seconds
Started Aug 21 02:08:57 PM UTC 24
Finished Aug 21 02:09:00 PM UTC 24
Peak memory 224224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3759873
774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw
_reset.3759873774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1638803931
Short name T124
Test name
Test status
Simulation time 40168281 ps
CPU time 2.38 seconds
Started Aug 21 02:09:03 PM UTC 24
Finished Aug 21 02:09:06 PM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=1638803931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1638803931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2590113638
Short name T723
Test name
Test status
Simulation time 27032127 ps
CPU time 1.42 seconds
Started Aug 21 02:08:59 PM UTC 24
Finished Aug 21 02:09:02 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590113638 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.25901
13638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3240830962
Short name T135
Test name
Test status
Simulation time 28564772 ps
CPU time 1.74 seconds
Started Aug 21 02:08:53 PM UTC 24
Finished Aug 21 02:08:56 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=3240830962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
mac_mem_partial_access.3240830962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.445446930
Short name T721
Test name
Test status
Simulation time 34639003 ps
CPU time 1.13 seconds
Started Aug 21 02:08:49 PM UTC 24
Finished Aug 21 02:08:52 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4454469
30 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_wal
k.445446930 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.790021113
Short name T150
Test name
Test status
Simulation time 64143067 ps
CPU time 2.45 seconds
Started Aug 21 02:09:03 PM UTC 24
Finished Aug 21 02:09:06 PM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=790021113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
kmac_same_csr_outstanding.790021113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1836882985
Short name T105
Test name
Test status
Simulation time 492528008 ps
CPU time 4.27 seconds
Started Aug 21 02:08:49 PM UTC 24
Finished Aug 21 02:08:55 PM UTC 24
Peak memory 230016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1836882985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1836882985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.1890514113
Short name T123
Test name
Test status
Simulation time 46756183 ps
CPU time 3.78 seconds
Started Aug 21 02:08:53 PM UTC 24
Finished Aug 21 02:08:58 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890514113 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.18905
14113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1006339490
Short name T116
Test name
Test status
Simulation time 259066488 ps
CPU time 6.76 seconds
Started Aug 21 02:08:54 PM UTC 24
Finished Aug 21 02:09:02 PM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1006
339490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_
intg_err.1006339490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.620461700
Short name T783
Test name
Test status
Simulation time 162693048 ps
CPU time 1.6 seconds
Started Aug 21 02:10:35 PM UTC 24
Finished Aug 21 02:10:38 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=620461700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.620461700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1699811268
Short name T781
Test name
Test status
Simulation time 28021578 ps
CPU time 1.65 seconds
Started Aug 21 02:10:34 PM UTC 24
Finished Aug 21 02:10:37 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1699811268 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1699
811268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.174297450
Short name T778
Test name
Test status
Simulation time 59735847 ps
CPU time 1.19 seconds
Started Aug 21 02:10:32 PM UTC 24
Finished Aug 21 02:10:35 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174297450 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.17429
7450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2163857334
Short name T784
Test name
Test status
Simulation time 581554627 ps
CPU time 3.52 seconds
Started Aug 21 02:10:34 PM UTC 24
Finished Aug 21 02:10:38 PM UTC 24
Peak memory 225468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2163857334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.kmac_same_csr_outstanding.2163857334 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.1926073336
Short name T776
Test name
Test status
Simulation time 66619144 ps
CPU time 1.12 seconds
Started Aug 21 02:10:30 PM UTC 24
Finished Aug 21 02:10:33 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1926073336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
mac_shadow_reg_errors.1926073336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2554243946
Short name T780
Test name
Test status
Simulation time 92705441 ps
CPU time 3.71 seconds
Started Aug 21 02:10:31 PM UTC 24
Finished Aug 21 02:10:36 PM UTC 24
Peak memory 229964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2554243946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 10.kmac_shadow_reg_errors_with_csr_rw.2554243946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.605605453
Short name T782
Test name
Test status
Simulation time 145393953 ps
CPU time 4.88 seconds
Started Aug 21 02:10:31 PM UTC 24
Finished Aug 21 02:10:37 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605605453 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.60560
5453 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.4207516766
Short name T171
Test name
Test status
Simulation time 105378794 ps
CPU time 5.65 seconds
Started Aug 21 02:10:32 PM UTC 24
Finished Aug 21 02:10:39 PM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4207
516766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl
_intg_err.4207516766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2639475866
Short name T790
Test name
Test status
Simulation time 35670058 ps
CPU time 3.27 seconds
Started Aug 21 02:10:39 PM UTC 24
Finished Aug 21 02:10:44 PM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=2639475866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2639475866 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2770597416
Short name T788
Test name
Test status
Simulation time 26504585 ps
CPU time 1.77 seconds
Started Aug 21 02:10:39 PM UTC 24
Finished Aug 21 02:10:42 PM UTC 24
Peak memory 224208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2770597416 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2770
597416 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.2560981044
Short name T786
Test name
Test status
Simulation time 27743562 ps
CPU time 1.2 seconds
Started Aug 21 02:10:39 PM UTC 24
Finished Aug 21 02:10:42 PM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560981044 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2560
981044 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1813063579
Short name T791
Test name
Test status
Simulation time 129890879 ps
CPU time 3.18 seconds
Started Aug 21 02:10:39 PM UTC 24
Finished Aug 21 02:10:44 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1813063579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.kmac_same_csr_outstanding.1813063579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2127314929
Short name T785
Test name
Test status
Simulation time 48519449 ps
CPU time 2.05 seconds
Started Aug 21 02:10:36 PM UTC 24
Finished Aug 21 02:10:40 PM UTC 24
Peak memory 225836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2127314929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
mac_shadow_reg_errors.2127314929 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1702308050
Short name T787
Test name
Test status
Simulation time 510855534 ps
CPU time 4.34 seconds
Started Aug 21 02:10:36 PM UTC 24
Finished Aug 21 02:10:42 PM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1702308050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 11.kmac_shadow_reg_errors_with_csr_rw.1702308050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2737896405
Short name T793
Test name
Test status
Simulation time 633199455 ps
CPU time 5.84 seconds
Started Aug 21 02:10:37 PM UTC 24
Finished Aug 21 02:10:45 PM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737896405 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2737
896405 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1569048101
Short name T797
Test name
Test status
Simulation time 26547973 ps
CPU time 2.28 seconds
Started Aug 21 02:10:45 PM UTC 24
Finished Aug 21 02:10:49 PM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=1569048101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1569048101 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.749777551
Short name T795
Test name
Test status
Simulation time 15866996 ps
CPU time 1.63 seconds
Started Aug 21 02:10:43 PM UTC 24
Finished Aug 21 02:10:47 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749777551 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.74977
7551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.112349547
Short name T799
Test name
Test status
Simulation time 69068836 ps
CPU time 3.01 seconds
Started Aug 21 02:10:45 PM UTC 24
Finished Aug 21 02:10:50 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=112349547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.kmac_same_csr_outstanding.112349547 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.717097667
Short name T789
Test name
Test status
Simulation time 88303962 ps
CPU time 1.63 seconds
Started Aug 21 02:10:40 PM UTC 24
Finished Aug 21 02:10:43 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=717097667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.km
ac_shadow_reg_errors.717097667 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2325844434
Short name T792
Test name
Test status
Simulation time 103156557 ps
CPU time 2.97 seconds
Started Aug 21 02:10:40 PM UTC 24
Finished Aug 21 02:10:44 PM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2325844434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 12.kmac_shadow_reg_errors_with_csr_rw.2325844434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3203277810
Short name T794
Test name
Test status
Simulation time 817800741 ps
CPU time 4.19 seconds
Started Aug 21 02:10:41 PM UTC 24
Finished Aug 21 02:10:47 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3203277810 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3203
277810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.549796348
Short name T798
Test name
Test status
Simulation time 2276558177 ps
CPU time 4.23 seconds
Started Aug 21 02:10:43 PM UTC 24
Finished Aug 21 02:10:50 PM UTC 24
Peak memory 225664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5497
96348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_
intg_err.549796348 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2431712984
Short name T804
Test name
Test status
Simulation time 26685809 ps
CPU time 2.13 seconds
Started Aug 21 02:10:49 PM UTC 24
Finished Aug 21 02:10:53 PM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=2431712984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2431712984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.1711122502
Short name T801
Test name
Test status
Simulation time 66007573 ps
CPU time 1.48 seconds
Started Aug 21 02:10:47 PM UTC 24
Finished Aug 21 02:10:51 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711122502 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1711
122502 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.1265674794
Short name T800
Test name
Test status
Simulation time 24893679 ps
CPU time 1.21 seconds
Started Aug 21 02:10:47 PM UTC 24
Finished Aug 21 02:10:51 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265674794 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.1265
674794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2218198200
Short name T805
Test name
Test status
Simulation time 45902034 ps
CPU time 2.37 seconds
Started Aug 21 02:10:49 PM UTC 24
Finished Aug 21 02:10:53 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2218198200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.kmac_same_csr_outstanding.2218198200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3548479000
Short name T796
Test name
Test status
Simulation time 37261533 ps
CPU time 1.84 seconds
Started Aug 21 02:10:45 PM UTC 24
Finished Aug 21 02:10:49 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3548479000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
mac_shadow_reg_errors.3548479000 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.742389105
Short name T802
Test name
Test status
Simulation time 186046216 ps
CPU time 3.91 seconds
Started Aug 21 02:10:46 PM UTC 24
Finished Aug 21 02:10:52 PM UTC 24
Peak memory 225908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=742389105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.kmac_shadow_reg_errors_with_csr_rw.742389105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2491975940
Short name T806
Test name
Test status
Simulation time 137304321 ps
CPU time 4.93 seconds
Started Aug 21 02:10:46 PM UTC 24
Finished Aug 21 02:10:53 PM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491975940 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2491
975940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3107367395
Short name T803
Test name
Test status
Simulation time 270648239 ps
CPU time 3.68 seconds
Started Aug 21 02:10:46 PM UTC 24
Finished Aug 21 02:10:52 PM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3107
367395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl
_intg_err.3107367395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3007106581
Short name T815
Test name
Test status
Simulation time 69576724 ps
CPU time 3.46 seconds
Started Aug 21 02:10:54 PM UTC 24
Finished Aug 21 02:10:58 PM UTC 24
Peak memory 231840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=3007106581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3007106581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.2616190975
Short name T810
Test name
Test status
Simulation time 395281488 ps
CPU time 1.85 seconds
Started Aug 21 02:10:52 PM UTC 24
Finished Aug 21 02:10:55 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616190975 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2616
190975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1659076349
Short name T158
Test name
Test status
Simulation time 17214925 ps
CPU time 1.2 seconds
Started Aug 21 02:10:52 PM UTC 24
Finished Aug 21 02:10:55 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659076349 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1659
076349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2682343382
Short name T813
Test name
Test status
Simulation time 30997130 ps
CPU time 2.32 seconds
Started Aug 21 02:10:54 PM UTC 24
Finished Aug 21 02:10:57 PM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2682343382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.kmac_same_csr_outstanding.2682343382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2672491113
Short name T807
Test name
Test status
Simulation time 155329136 ps
CPU time 2.1 seconds
Started Aug 21 02:10:50 PM UTC 24
Finished Aug 21 02:10:54 PM UTC 24
Peak memory 225864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2672491113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
mac_shadow_reg_errors.2672491113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2916481032
Short name T809
Test name
Test status
Simulation time 211704436 ps
CPU time 2.64 seconds
Started Aug 21 02:10:51 PM UTC 24
Finished Aug 21 02:10:55 PM UTC 24
Peak memory 229956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2916481032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 14.kmac_shadow_reg_errors_with_csr_rw.2916481032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3659741001
Short name T808
Test name
Test status
Simulation time 24036152 ps
CPU time 2.35 seconds
Started Aug 21 02:10:51 PM UTC 24
Finished Aug 21 02:10:55 PM UTC 24
Peak memory 225564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3659741001 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3659
741001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1565748442
Short name T811
Test name
Test status
Simulation time 166896880 ps
CPU time 3.58 seconds
Started Aug 21 02:10:51 PM UTC 24
Finished Aug 21 02:10:56 PM UTC 24
Peak memory 225496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1565
748442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl
_intg_err.1565748442 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2000034002
Short name T818
Test name
Test status
Simulation time 35464602 ps
CPU time 2 seconds
Started Aug 21 02:10:56 PM UTC 24
Finished Aug 21 02:11:00 PM UTC 24
Peak memory 228552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=2000034002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2000034002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1964784673
Short name T817
Test name
Test status
Simulation time 14290535 ps
CPU time 1.44 seconds
Started Aug 21 02:10:56 PM UTC 24
Finished Aug 21 02:10:59 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1964784673 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1964
784673 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2690664683
Short name T816
Test name
Test status
Simulation time 15189094 ps
CPU time 1.25 seconds
Started Aug 21 02:10:56 PM UTC 24
Finished Aug 21 02:10:59 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690664683 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2690
664683 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2575120150
Short name T820
Test name
Test status
Simulation time 69806261 ps
CPU time 2.98 seconds
Started Aug 21 02:10:56 PM UTC 24
Finished Aug 21 02:11:00 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2575120150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.kmac_same_csr_outstanding.2575120150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1591484171
Short name T812
Test name
Test status
Simulation time 163010435 ps
CPU time 2.16 seconds
Started Aug 21 02:10:54 PM UTC 24
Finished Aug 21 02:10:57 PM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1591484171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
mac_shadow_reg_errors.1591484171 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2797276780
Short name T814
Test name
Test status
Simulation time 118696976 ps
CPU time 2.54 seconds
Started Aug 21 02:10:54 PM UTC 24
Finished Aug 21 02:10:57 PM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2797276780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 15.kmac_shadow_reg_errors_with_csr_rw.2797276780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3890982692
Short name T823
Test name
Test status
Simulation time 712493577 ps
CPU time 6.01 seconds
Started Aug 21 02:10:55 PM UTC 24
Finished Aug 21 02:11:02 PM UTC 24
Peak memory 225596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3890982692 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3890
982692 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2573174232
Short name T173
Test name
Test status
Simulation time 176605201 ps
CPU time 2.7 seconds
Started Aug 21 02:10:55 PM UTC 24
Finished Aug 21 02:10:59 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2573
174232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl
_intg_err.2573174232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2581963775
Short name T828
Test name
Test status
Simulation time 90672848 ps
CPU time 2.76 seconds
Started Aug 21 02:10:59 PM UTC 24
Finished Aug 21 02:11:04 PM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=2581963775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2581963775 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.4051411705
Short name T824
Test name
Test status
Simulation time 27769427 ps
CPU time 1.41 seconds
Started Aug 21 02:10:59 PM UTC 24
Finished Aug 21 02:11:02 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4051411705 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.4051
411705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.840429480
Short name T819
Test name
Test status
Simulation time 70789808 ps
CPU time 1.15 seconds
Started Aug 21 02:10:58 PM UTC 24
Finished Aug 21 02:11:00 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840429480 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.84042
9480 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.728150706
Short name T826
Test name
Test status
Simulation time 183432437 ps
CPU time 2.16 seconds
Started Aug 21 02:10:59 PM UTC 24
Finished Aug 21 02:11:03 PM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=728150706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.kmac_same_csr_outstanding.728150706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.591755119
Short name T821
Test name
Test status
Simulation time 58625197 ps
CPU time 1.55 seconds
Started Aug 21 02:10:58 PM UTC 24
Finished Aug 21 02:11:01 PM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=591755119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.km
ac_shadow_reg_errors.591755119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2313706139
Short name T822
Test name
Test status
Simulation time 74581337 ps
CPU time 2.86 seconds
Started Aug 21 02:10:58 PM UTC 24
Finished Aug 21 02:11:02 PM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2313706139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 16.kmac_shadow_reg_errors_with_csr_rw.2313706139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3337369460
Short name T825
Test name
Test status
Simulation time 426409898 ps
CPU time 3.73 seconds
Started Aug 21 02:10:58 PM UTC 24
Finished Aug 21 02:11:03 PM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337369460 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3337
369460 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.821518980
Short name T835
Test name
Test status
Simulation time 83873923 ps
CPU time 2.57 seconds
Started Aug 21 02:11:04 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 227784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=821518980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.821518980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.4119315128
Short name T831
Test name
Test status
Simulation time 16927803 ps
CPU time 1.65 seconds
Started Aug 21 02:11:03 PM UTC 24
Finished Aug 21 02:11:06 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4119315128 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4119
315128 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.3782577938
Short name T829
Test name
Test status
Simulation time 13885597 ps
CPU time 1.25 seconds
Started Aug 21 02:11:02 PM UTC 24
Finished Aug 21 02:11:04 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3782577938 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3782
577938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1348383118
Short name T834
Test name
Test status
Simulation time 312853926 ps
CPU time 2.47 seconds
Started Aug 21 02:11:03 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1348383118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.kmac_same_csr_outstanding.1348383118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4068172507
Short name T827
Test name
Test status
Simulation time 39647148 ps
CPU time 1.99 seconds
Started Aug 21 02:11:00 PM UTC 24
Finished Aug 21 02:11:03 PM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=4068172507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
mac_shadow_reg_errors.4068172507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1229723508
Short name T830
Test name
Test status
Simulation time 484390629 ps
CPU time 4.17 seconds
Started Aug 21 02:11:01 PM UTC 24
Finished Aug 21 02:11:06 PM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1229723508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 17.kmac_shadow_reg_errors_with_csr_rw.1229723508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2472580915
Short name T833
Test name
Test status
Simulation time 461074681 ps
CPU time 5.14 seconds
Started Aug 21 02:11:01 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2472580915 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2472
580915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.12191998
Short name T172
Test name
Test status
Simulation time 78708408 ps
CPU time 3.56 seconds
Started Aug 21 02:11:02 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1219
1998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_i
ntg_err.12191998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.461856720
Short name T841
Test name
Test status
Simulation time 41229183 ps
CPU time 2.37 seconds
Started Aug 21 02:11:07 PM UTC 24
Finished Aug 21 02:11:11 PM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=461856720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.461856720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3541802798
Short name T839
Test name
Test status
Simulation time 20046314 ps
CPU time 1.46 seconds
Started Aug 21 02:11:07 PM UTC 24
Finished Aug 21 02:11:10 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541802798 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3541
802798 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1507561275
Short name T836
Test name
Test status
Simulation time 18857780 ps
CPU time 1.19 seconds
Started Aug 21 02:11:05 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1507561275 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1507
561275 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.299185811
Short name T845
Test name
Test status
Simulation time 48183576 ps
CPU time 3.2 seconds
Started Aug 21 02:11:07 PM UTC 24
Finished Aug 21 02:11:12 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=299185811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.kmac_same_csr_outstanding.299185811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2877145817
Short name T832
Test name
Test status
Simulation time 30515276 ps
CPU time 1.72 seconds
Started Aug 21 02:11:04 PM UTC 24
Finished Aug 21 02:11:07 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2877145817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.k
mac_shadow_reg_errors.2877145817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.637606393
Short name T837
Test name
Test status
Simulation time 171741863 ps
CPU time 2.69 seconds
Started Aug 21 02:11:04 PM UTC 24
Finished Aug 21 02:11:08 PM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=637606393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.kmac_shadow_reg_errors_with_csr_rw.637606393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2091086639
Short name T838
Test name
Test status
Simulation time 250563159 ps
CPU time 4.56 seconds
Started Aug 21 02:11:04 PM UTC 24
Finished Aug 21 02:11:10 PM UTC 24
Peak memory 225536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2091086639 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2091
086639 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3230666161
Short name T846
Test name
Test status
Simulation time 254504462 ps
CPU time 6.28 seconds
Started Aug 21 02:11:05 PM UTC 24
Finished Aug 21 02:11:12 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230
666161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl
_intg_err.3230666161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.153506407
Short name T850
Test name
Test status
Simulation time 71054525 ps
CPU time 1.8 seconds
Started Aug 21 02:11:10 PM UTC 24
Finished Aug 21 02:11:13 PM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=153506407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.153506407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.4014639138
Short name T844
Test name
Test status
Simulation time 17969645 ps
CPU time 1.49 seconds
Started Aug 21 02:11:09 PM UTC 24
Finished Aug 21 02:11:12 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4014639138 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.4014
639138 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1225397962
Short name T843
Test name
Test status
Simulation time 13775882 ps
CPU time 1.21 seconds
Started Aug 21 02:11:09 PM UTC 24
Finished Aug 21 02:11:11 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225397962 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1225
397962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3898545453
Short name T852
Test name
Test status
Simulation time 199996102 ps
CPU time 3.72 seconds
Started Aug 21 02:11:09 PM UTC 24
Finished Aug 21 02:11:14 PM UTC 24
Peak memory 225536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3898545453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.kmac_same_csr_outstanding.3898545453 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3547481850
Short name T840
Test name
Test status
Simulation time 39717810 ps
CPU time 1.53 seconds
Started Aug 21 02:11:07 PM UTC 24
Finished Aug 21 02:11:10 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3547481850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
mac_shadow_reg_errors.3547481850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3987106639
Short name T842
Test name
Test status
Simulation time 38987208 ps
CPU time 2.51 seconds
Started Aug 21 02:11:08 PM UTC 24
Finished Aug 21 02:11:11 PM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=3987106639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 19.kmac_shadow_reg_errors_with_csr_rw.3987106639 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3440854377
Short name T849
Test name
Test status
Simulation time 355353456 ps
CPU time 2.87 seconds
Started Aug 21 02:11:09 PM UTC 24
Finished Aug 21 02:11:13 PM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3440854377 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3440
854377 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.728932573
Short name T860
Test name
Test status
Simulation time 104650034 ps
CPU time 5.69 seconds
Started Aug 21 02:11:09 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 225512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7289
32573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_
intg_err.728932573 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.2585278232
Short name T729
Test name
Test status
Simulation time 386114506 ps
CPU time 6.73 seconds
Started Aug 21 02:09:21 PM UTC 24
Finished Aug 21 02:09:29 PM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585278
232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_al
iasing.2585278232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.92835253
Short name T739
Test name
Test status
Simulation time 1012616496 ps
CPU time 27.83 seconds
Started Aug 21 02:09:21 PM UTC 24
Finished Aug 21 02:09:50 PM UTC 24
Peak memory 225504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=9283525
3 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_
bash.92835253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1879857370
Short name T147
Test name
Test status
Simulation time 73198628 ps
CPU time 1.85 seconds
Started Aug 21 02:09:16 PM UTC 24
Finished Aug 21 02:09:20 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1879857
370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw
_reset.1879857370 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.422520131
Short name T131
Test name
Test status
Simulation time 38958391 ps
CPU time 3.51 seconds
Started Aug 21 02:09:23 PM UTC 24
Finished Aug 21 02:09:28 PM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=422520131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.422520131 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.811868044
Short name T728
Test name
Test status
Simulation time 29814918 ps
CPU time 1.61 seconds
Started Aug 21 02:09:19 PM UTC 24
Finished Aug 21 02:09:22 PM UTC 24
Peak memory 224224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811868044 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.811868
044 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3844122413
Short name T154
Test name
Test status
Simulation time 16544521 ps
CPU time 1.18 seconds
Started Aug 21 02:09:15 PM UTC 24
Finished Aug 21 02:09:18 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844122413 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.38441
22413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.1739539339
Short name T136
Test name
Test status
Simulation time 117320338 ps
CPU time 2 seconds
Started Aug 21 02:09:11 PM UTC 24
Finished Aug 21 02:09:15 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=1739539339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
mac_mem_partial_access.1739539339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2720264496
Short name T725
Test name
Test status
Simulation time 13000426 ps
CPU time 1.15 seconds
Started Aug 21 02:09:11 PM UTC 24
Finished Aug 21 02:09:14 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2720264
496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_wa
lk.2720264496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.980096809
Short name T148
Test name
Test status
Simulation time 69247244 ps
CPU time 2.46 seconds
Started Aug 21 02:09:22 PM UTC 24
Finished Aug 21 02:09:25 PM UTC 24
Peak memory 225628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=980096809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
kmac_same_csr_outstanding.980096809 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.4069820200
Short name T114
Test name
Test status
Simulation time 42868625 ps
CPU time 1.86 seconds
Started Aug 21 02:09:07 PM UTC 24
Finished Aug 21 02:09:10 PM UTC 24
Peak memory 224288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=4069820200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.km
ac_shadow_reg_errors.4069820200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1437042800
Short name T724
Test name
Test status
Simulation time 31423709 ps
CPU time 2.39 seconds
Started Aug 21 02:09:07 PM UTC 24
Finished Aug 21 02:09:11 PM UTC 24
Peak memory 225852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1437042800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.kmac_shadow_reg_errors_with_csr_rw.1437042800 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.162567997
Short name T125
Test name
Test status
Simulation time 93980305 ps
CPU time 4.72 seconds
Started Aug 21 02:09:14 PM UTC 24
Finished Aug 21 02:09:21 PM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162567997 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.162567
997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2957920570
Short name T117
Test name
Test status
Simulation time 445789243 ps
CPU time 3.93 seconds
Started Aug 21 02:09:14 PM UTC 24
Finished Aug 21 02:09:20 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2957
920570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_
intg_err.2957920570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2354071245
Short name T848
Test name
Test status
Simulation time 22070775 ps
CPU time 1.13 seconds
Started Aug 21 02:11:10 PM UTC 24
Finished Aug 21 02:11:13 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354071245 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2354
071245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.1404725366
Short name T847
Test name
Test status
Simulation time 13497084 ps
CPU time 1.16 seconds
Started Aug 21 02:11:10 PM UTC 24
Finished Aug 21 02:11:13 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1404725366 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1404
725366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.448868203
Short name T851
Test name
Test status
Simulation time 43388120 ps
CPU time 1.22 seconds
Started Aug 21 02:11:12 PM UTC 24
Finished Aug 21 02:11:14 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448868203 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.44886
8203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3165821959
Short name T853
Test name
Test status
Simulation time 16171180 ps
CPU time 1.22 seconds
Started Aug 21 02:11:12 PM UTC 24
Finished Aug 21 02:11:14 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165821959 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3165
821959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.2805204016
Short name T855
Test name
Test status
Simulation time 113634500 ps
CPU time 1.07 seconds
Started Aug 21 02:11:12 PM UTC 24
Finished Aug 21 02:11:14 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2805204016 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2805
204016 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2519755825
Short name T854
Test name
Test status
Simulation time 32193276 ps
CPU time 1.01 seconds
Started Aug 21 02:11:12 PM UTC 24
Finished Aug 21 02:11:14 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519755825 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2519
755825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.2030392938
Short name T857
Test name
Test status
Simulation time 21346445 ps
CPU time 1.15 seconds
Started Aug 21 02:11:13 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030392938 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2030
392938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3313494161
Short name T856
Test name
Test status
Simulation time 71367110 ps
CPU time 1.15 seconds
Started Aug 21 02:11:13 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3313494161 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3313
494161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2231066404
Short name T858
Test name
Test status
Simulation time 41725038 ps
CPU time 1.16 seconds
Started Aug 21 02:11:13 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231066404 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2231
066404 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.44617806
Short name T859
Test name
Test status
Simulation time 17226644 ps
CPU time 1.21 seconds
Started Aug 21 02:11:13 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44617806 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.446178
06 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3305952934
Short name T737
Test name
Test status
Simulation time 145004867 ps
CPU time 10.56 seconds
Started Aug 21 02:09:35 PM UTC 24
Finished Aug 21 02:09:47 PM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305952
934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_al
iasing.3305952934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2419337878
Short name T750
Test name
Test status
Simulation time 1505905371 ps
CPU time 31.23 seconds
Started Aug 21 02:09:35 PM UTC 24
Finished Aug 21 02:10:08 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2419337
878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bi
t_bash.2419337878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2710985506
Short name T149
Test name
Test status
Simulation time 67772893 ps
CPU time 1.46 seconds
Started Aug 21 02:09:33 PM UTC 24
Finished Aug 21 02:09:35 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710985
506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw
_reset.2710985506 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.467239314
Short name T734
Test name
Test status
Simulation time 65350758 ps
CPU time 3.28 seconds
Started Aug 21 02:09:37 PM UTC 24
Finished Aug 21 02:09:42 PM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=467239314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.467239314 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.924005195
Short name T732
Test name
Test status
Simulation time 14491271 ps
CPU time 1.42 seconds
Started Aug 21 02:09:34 PM UTC 24
Finished Aug 21 02:09:36 PM UTC 24
Peak memory 224224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924005195 -as
sert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.924005
195 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2028417194
Short name T160
Test name
Test status
Simulation time 15975999 ps
CPU time 1.24 seconds
Started Aug 21 02:09:32 PM UTC 24
Finished Aug 21 02:09:34 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028417194 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.20284
17194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.4086916833
Short name T137
Test name
Test status
Simulation time 200096234 ps
CPU time 2.49 seconds
Started Aug 21 02:09:29 PM UTC 24
Finished Aug 21 02:09:33 PM UTC 24
Peak memory 225508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=4086916833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
mac_mem_partial_access.4086916833 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.122140427
Short name T730
Test name
Test status
Simulation time 33066507 ps
CPU time 1.12 seconds
Started Aug 21 02:09:28 PM UTC 24
Finished Aug 21 02:09:30 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221404
27 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_wal
k.122140427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.760838348
Short name T733
Test name
Test status
Simulation time 519260388 ps
CPU time 3.03 seconds
Started Aug 21 02:09:36 PM UTC 24
Finished Aug 21 02:09:41 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=760838348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
kmac_same_csr_outstanding.760838348 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3545591830
Short name T100
Test name
Test status
Simulation time 50502671 ps
CPU time 2.94 seconds
Started Aug 21 02:09:26 PM UTC 24
Finished Aug 21 02:09:30 PM UTC 24
Peak memory 229696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=3545591830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3545591830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1591548710
Short name T731
Test name
Test status
Simulation time 232723290 ps
CPU time 3.13 seconds
Started Aug 21 02:09:29 PM UTC 24
Finished Aug 21 02:09:34 PM UTC 24
Peak memory 225692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591548710 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.15915
48710 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1027009090
Short name T165
Test name
Test status
Simulation time 308158320 ps
CPU time 5.66 seconds
Started Aug 21 02:09:31 PM UTC 24
Finished Aug 21 02:09:38 PM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027
009090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_
intg_err.1027009090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.3602045002
Short name T861
Test name
Test status
Simulation time 16551072 ps
CPU time 1.13 seconds
Started Aug 21 02:11:14 PM UTC 24
Finished Aug 21 02:11:16 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602045002 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3602
045002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1025224846
Short name T862
Test name
Test status
Simulation time 14135412 ps
CPU time 1.17 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:17 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1025224846 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1025
224846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.645763092
Short name T863
Test name
Test status
Simulation time 57839795 ps
CPU time 1.14 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:17 PM UTC 24
Peak memory 224156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=645763092 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.64576
3092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.723271524
Short name T864
Test name
Test status
Simulation time 64574757 ps
CPU time 1.15 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:17 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723271524 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.72327
1524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2389452158
Short name T865
Test name
Test status
Simulation time 38485598 ps
CPU time 1.19 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:18 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2389452158 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2389
452158 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.3630160424
Short name T867
Test name
Test status
Simulation time 50166174 ps
CPU time 1.22 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:18 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3630160424 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3630
160424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2099387324
Short name T866
Test name
Test status
Simulation time 39647253 ps
CPU time 1.15 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:18 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2099387324 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2099
387324 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2823722418
Short name T868
Test name
Test status
Simulation time 18350649 ps
CPU time 1.23 seconds
Started Aug 21 02:11:15 PM UTC 24
Finished Aug 21 02:11:18 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823722418 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2823
722418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.3891251198
Short name T871
Test name
Test status
Simulation time 26759048 ps
CPU time 1.25 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3891251198 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3891
251198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1614708175
Short name T869
Test name
Test status
Simulation time 40518224 ps
CPU time 1.21 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 224188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614708175 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1614
708175 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.2891457629
Short name T749
Test name
Test status
Simulation time 1881173571 ps
CPU time 14.08 seconds
Started Aug 21 02:09:51 PM UTC 24
Finished Aug 21 02:10:07 PM UTC 24
Peak memory 225608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891457
629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_al
iasing.2891457629 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3037924206
Short name T751
Test name
Test status
Simulation time 1898175874 ps
CPU time 15.78 seconds
Started Aug 21 02:09:51 PM UTC 24
Finished Aug 21 02:10:08 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037924
206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bi
t_bash.3037924206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.4255952992
Short name T740
Test name
Test status
Simulation time 31616794 ps
CPU time 1.57 seconds
Started Aug 21 02:09:48 PM UTC 24
Finished Aug 21 02:09:51 PM UTC 24
Peak memory 224224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4255952
992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw
_reset.4255952992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2349036752
Short name T744
Test name
Test status
Simulation time 39610725 ps
CPU time 3.29 seconds
Started Aug 21 02:09:52 PM UTC 24
Finished Aug 21 02:09:57 PM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=2349036752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2349036752 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2889040169
Short name T741
Test name
Test status
Simulation time 111256183 ps
CPU time 1.48 seconds
Started Aug 21 02:09:50 PM UTC 24
Finished Aug 21 02:09:53 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2889040169 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.28890
40169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.55081803
Short name T138
Test name
Test status
Simulation time 32953001 ps
CPU time 2.18 seconds
Started Aug 21 02:09:43 PM UTC 24
Finished Aug 21 02:09:47 PM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_se
ed=55081803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kma
c_mem_partial_access.55081803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1584311112
Short name T735
Test name
Test status
Simulation time 20138065 ps
CPU time 1.21 seconds
Started Aug 21 02:09:42 PM UTC 24
Finished Aug 21 02:09:45 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1584311
112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_wa
lk.1584311112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3384570130
Short name T742
Test name
Test status
Simulation time 24621283 ps
CPU time 2.21 seconds
Started Aug 21 02:09:51 PM UTC 24
Finished Aug 21 02:09:55 PM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3384570130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.kmac_same_csr_outstanding.3384570130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2541590535
Short name T102
Test name
Test status
Simulation time 195729501 ps
CPU time 1.89 seconds
Started Aug 21 02:09:39 PM UTC 24
Finished Aug 21 02:09:42 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2541590535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.km
ac_shadow_reg_errors.2541590535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1097498452
Short name T736
Test name
Test status
Simulation time 46345976 ps
CPU time 3.46 seconds
Started Aug 21 02:09:41 PM UTC 24
Finished Aug 21 02:09:46 PM UTC 24
Peak memory 230036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1097498452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 4.kmac_shadow_reg_errors_with_csr_rw.1097498452 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.646394986
Short name T738
Test name
Test status
Simulation time 32304424 ps
CPU time 2.84 seconds
Started Aug 21 02:09:46 PM UTC 24
Finished Aug 21 02:09:49 PM UTC 24
Peak memory 225604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646394986 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.646394
986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2221006333
Short name T167
Test name
Test status
Simulation time 77913990 ps
CPU time 3.38 seconds
Started Aug 21 02:09:47 PM UTC 24
Finished Aug 21 02:09:51 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221
006333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_
intg_err.2221006333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.955861451
Short name T870
Test name
Test status
Simulation time 37385629 ps
CPU time 1.23 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 223880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955861451 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.95586
1451 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4065490944
Short name T872
Test name
Test status
Simulation time 55954519 ps
CPU time 1.25 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065490944 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4065
490944 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1669344666
Short name T873
Test name
Test status
Simulation time 15325221 ps
CPU time 1.25 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1669344666 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1669
344666 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1228781812
Short name T874
Test name
Test status
Simulation time 126220300 ps
CPU time 1.24 seconds
Started Aug 21 02:11:17 PM UTC 24
Finished Aug 21 02:11:19 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1228781812 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1228
781812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1253768276
Short name T875
Test name
Test status
Simulation time 13463935 ps
CPU time 1.25 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 223620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1253768276 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1253
768276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2164972495
Short name T876
Test name
Test status
Simulation time 40703486 ps
CPU time 1.2 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 224228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164972495 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2164
972495 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.546365870
Short name T878
Test name
Test status
Simulation time 48329874 ps
CPU time 1.24 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546365870 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.54636
5870 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3823861457
Short name T879
Test name
Test status
Simulation time 61727577 ps
CPU time 1.13 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823861457 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3823
861457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.929403620
Short name T877
Test name
Test status
Simulation time 14641292 ps
CPU time 1.19 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=929403620 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.92940
3620 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.1147652855
Short name T880
Test name
Test status
Simulation time 14405832 ps
CPU time 1.17 seconds
Started Aug 21 02:11:19 PM UTC 24
Finished Aug 21 02:11:21 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1147652855 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1147
652855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4014779206
Short name T753
Test name
Test status
Simulation time 70545825 ps
CPU time 3.59 seconds
Started Aug 21 02:10:05 PM UTC 24
Finished Aug 21 02:10:10 PM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=4014779206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.4014779206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.2439796318
Short name T748
Test name
Test status
Simulation time 44950033 ps
CPU time 1.39 seconds
Started Aug 21 02:10:04 PM UTC 24
Finished Aug 21 02:10:06 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439796318 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.24397
96318 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3267475864
Short name T156
Test name
Test status
Simulation time 15507591 ps
CPU time 1.23 seconds
Started Aug 21 02:10:02 PM UTC 24
Finished Aug 21 02:10:04 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3267475864 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.32674
75864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.482720584
Short name T752
Test name
Test status
Simulation time 43501434 ps
CPU time 3.06 seconds
Started Aug 21 02:10:05 PM UTC 24
Finished Aug 21 02:10:09 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=482720584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
kmac_same_csr_outstanding.482720584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2287466339
Short name T743
Test name
Test status
Simulation time 45217199 ps
CPU time 1.79 seconds
Started Aug 21 02:09:53 PM UTC 24
Finished Aug 21 02:09:56 PM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2287466339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.km
ac_shadow_reg_errors.2287466339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1234576772
Short name T745
Test name
Test status
Simulation time 175078103 ps
CPU time 4.12 seconds
Started Aug 21 02:09:55 PM UTC 24
Finished Aug 21 02:10:01 PM UTC 24
Peak memory 230080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=1234576772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 5.kmac_shadow_reg_errors_with_csr_rw.1234576772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.819420046
Short name T747
Test name
Test status
Simulation time 2251760078 ps
CPU time 6.79 seconds
Started Aug 21 02:09:57 PM UTC 24
Finished Aug 21 02:10:04 PM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=819420046 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.819420
046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3660834063
Short name T746
Test name
Test status
Simulation time 272779110 ps
CPU time 4.46 seconds
Started Aug 21 02:09:58 PM UTC 24
Finished Aug 21 02:10:03 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660
834063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_
intg_err.3660834063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1852106565
Short name T758
Test name
Test status
Simulation time 316801883 ps
CPU time 3.62 seconds
Started Aug 21 02:10:11 PM UTC 24
Finished Aug 21 02:10:16 PM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=1852106565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1852106565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1676786745
Short name T754
Test name
Test status
Simulation time 22878962 ps
CPU time 1.4 seconds
Started Aug 21 02:10:10 PM UTC 24
Finished Aug 21 02:10:12 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676786745 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.16767
86745 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3719979307
Short name T161
Test name
Test status
Simulation time 11691609 ps
CPU time 1.16 seconds
Started Aug 21 02:10:10 PM UTC 24
Finished Aug 21 02:10:12 PM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3719979307 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.37199
79307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2153341885
Short name T757
Test name
Test status
Simulation time 72984823 ps
CPU time 2.14 seconds
Started Aug 21 02:10:11 PM UTC 24
Finished Aug 21 02:10:14 PM UTC 24
Peak memory 225564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2153341885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.kmac_same_csr_outstanding.2153341885 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2379242722
Short name T103
Test name
Test status
Simulation time 27667659 ps
CPU time 1.75 seconds
Started Aug 21 02:10:07 PM UTC 24
Finished Aug 21 02:10:10 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2379242722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.km
ac_shadow_reg_errors.2379242722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2576378577
Short name T101
Test name
Test status
Simulation time 103036914 ps
CPU time 4.19 seconds
Started Aug 21 02:10:07 PM UTC 24
Finished Aug 21 02:10:13 PM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=2576378577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 6.kmac_shadow_reg_errors_with_csr_rw.2576378577 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.3888411538
Short name T755
Test name
Test status
Simulation time 103982080 ps
CPU time 2.71 seconds
Started Aug 21 02:10:08 PM UTC 24
Finished Aug 21 02:10:12 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3888411538 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.38884
11538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2964631640
Short name T756
Test name
Test status
Simulation time 206830183 ps
CPU time 3.48 seconds
Started Aug 21 02:10:10 PM UTC 24
Finished Aug 21 02:10:14 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2964
631640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_
intg_err.2964631640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3852400601
Short name T763
Test name
Test status
Simulation time 66708592 ps
CPU time 3.34 seconds
Started Aug 21 02:10:18 PM UTC 24
Finished Aug 21 02:10:23 PM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=3852400601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3852400601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2189319864
Short name T760
Test name
Test status
Simulation time 33718973 ps
CPU time 1.56 seconds
Started Aug 21 02:10:16 PM UTC 24
Finished Aug 21 02:10:19 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2189319864 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.21893
19864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.2819568749
Short name T159
Test name
Test status
Simulation time 35711638 ps
CPU time 1.25 seconds
Started Aug 21 02:10:16 PM UTC 24
Finished Aug 21 02:10:18 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819568749 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.28195
68749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.369944659
Short name T762
Test name
Test status
Simulation time 154949332 ps
CPU time 3.42 seconds
Started Aug 21 02:10:17 PM UTC 24
Finished Aug 21 02:10:22 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=369944659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
kmac_same_csr_outstanding.369944659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.40075245
Short name T104
Test name
Test status
Simulation time 91192043 ps
CPU time 1.52 seconds
Started Aug 21 02:10:13 PM UTC 24
Finished Aug 21 02:10:17 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=40075245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors.40075245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3159228184
Short name T759
Test name
Test status
Simulation time 141627037 ps
CPU time 2.98 seconds
Started Aug 21 02:10:13 PM UTC 24
Finished Aug 21 02:10:18 PM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=3159228184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.kmac_shadow_reg_errors_with_csr_rw.3159228184 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3594463571
Short name T761
Test name
Test status
Simulation time 51697895 ps
CPU time 4.14 seconds
Started Aug 21 02:10:13 PM UTC 24
Finished Aug 21 02:10:19 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594463571 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.35944
63571 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3515100222
Short name T166
Test name
Test status
Simulation time 196553474 ps
CPU time 6.93 seconds
Started Aug 21 02:10:13 PM UTC 24
Finished Aug 21 02:10:22 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515
100222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_
intg_err.3515100222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1301040985
Short name T768
Test name
Test status
Simulation time 42687076 ps
CPU time 2.34 seconds
Started Aug 21 02:10:24 PM UTC 24
Finished Aug 21 02:10:28 PM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=1301040985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1301040985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2346450099
Short name T767
Test name
Test status
Simulation time 26026923 ps
CPU time 1.58 seconds
Started Aug 21 02:10:24 PM UTC 24
Finished Aug 21 02:10:27 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2346450099 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.23464
50099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1128843923
Short name T765
Test name
Test status
Simulation time 10787862 ps
CPU time 1.2 seconds
Started Aug 21 02:10:23 PM UTC 24
Finished Aug 21 02:10:26 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128843923 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.11288
43923 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1967300970
Short name T771
Test name
Test status
Simulation time 343970637 ps
CPU time 3.57 seconds
Started Aug 21 02:10:24 PM UTC 24
Finished Aug 21 02:10:29 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1967300970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.kmac_same_csr_outstanding.1967300970 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1909551331
Short name T175
Test name
Test status
Simulation time 65447501 ps
CPU time 1.58 seconds
Started Aug 21 02:10:19 PM UTC 24
Finished Aug 21 02:10:22 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1909551331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.km
ac_shadow_reg_errors.1909551331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.154984542
Short name T764
Test name
Test status
Simulation time 88926011 ps
CPU time 3.47 seconds
Started Aug 21 02:10:19 PM UTC 24
Finished Aug 21 02:10:24 PM UTC 24
Peak memory 230144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +nt
b_random_seed=154984542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.kmac_shadow_reg_errors_with_csr_rw.154984542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.1894361968
Short name T766
Test name
Test status
Simulation time 226214768 ps
CPU time 5.37 seconds
Started Aug 21 02:10:19 PM UTC 24
Finished Aug 21 02:10:26 PM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1894361968 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.18943
61968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1643532144
Short name T769
Test name
Test status
Simulation time 2184345329 ps
CPU time 5.55 seconds
Started Aug 21 02:10:20 PM UTC 24
Finished Aug 21 02:10:28 PM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1643
532144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_
intg_err.1643532144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1376343353
Short name T779
Test name
Test status
Simulation time 75877402 ps
CPU time 3.37 seconds
Started Aug 21 02:10:30 PM UTC 24
Finished Aug 21 02:10:35 PM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo
ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit
an/hw/dv/tools/sim.tcl +ntb_random_seed=1376343353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1376343353 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.3878794897
Short name T775
Test name
Test status
Simulation time 26582800 ps
CPU time 1.81 seconds
Started Aug 21 02:10:29 PM UTC 24
Finished Aug 21 02:10:32 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3878794897 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.38787
94897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.804644350
Short name T774
Test name
Test status
Simulation time 19121335 ps
CPU time 1.3 seconds
Started Aug 21 02:10:29 PM UTC 24
Finished Aug 21 02:10:31 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804644350 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.804644
350 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.38411222
Short name T777
Test name
Test status
Simulation time 98812868 ps
CPU time 2.26 seconds
Started Aug 21 02:10:30 PM UTC 24
Finished Aug 21 02:10:34 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=38411222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
mac_same_csr_outstanding.38411222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3378953196
Short name T770
Test name
Test status
Simulation time 42624255 ps
CPU time 1.98 seconds
Started Aug 21 02:10:25 PM UTC 24
Finished Aug 21 02:10:29 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=3378953196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.km
ac_shadow_reg_errors.3378953196 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1380097309
Short name T772
Test name
Test status
Simulation time 74313132 ps
CPU time 1.96 seconds
Started Aug 21 02:10:26 PM UTC 24
Finished Aug 21 02:10:30 PM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380097309 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.13800
97309 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3323243217
Short name T168
Test name
Test status
Simulation time 386465385 ps
CPU time 8.5 seconds
Started Aug 21 02:10:27 PM UTC 24
Finished Aug 21 02:10:38 PM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3323
243217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_
intg_err.3323243217 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.3557203694
Short name T13
Test name
Test status
Simulation time 18892935080 ps
CPU time 447.39 seconds
Started Aug 21 12:40:18 PM UTC 24
Finished Aug 21 12:47:51 PM UTC 24
Peak memory 542972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35572036
94 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kma
c_app_with_partial_data.3557203694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.414391365
Short name T75
Test name
Test status
Simulation time 10579282965 ps
CPU time 542.93 seconds
Started Aug 21 12:38:19 PM UTC 24
Finished Aug 21 12:47:30 PM UTC 24
Peak memory 250140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41439136
5 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_wri
te.414391365 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3437930943
Short name T4
Test name
Test status
Simulation time 3650581899 ps
CPU time 17.65 seconds
Started Aug 21 12:40:39 PM UTC 24
Finished Aug 21 12:40:58 PM UTC 24
Peak memory 235820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3437930943 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.343793094
3 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.2891442273
Short name T7
Test name
Test status
Simulation time 728254778 ps
CPU time 3.51 seconds
Started Aug 21 12:40:31 PM UTC 24
Finished Aug 21 12:40:36 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891442273 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2891442273 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2865359812
Short name T206
Test name
Test status
Simulation time 39215988784 ps
CPU time 1452.43 seconds
Started Aug 21 12:38:11 PM UTC 24
Finished Aug 21 01:02:41 PM UTC 24
Peak memory 913668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28653
59812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.km
ac_long_msg_and_output.2865359812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.4264207845
Short name T15
Test name
Test status
Simulation time 7770367769 ps
CPU time 167.31 seconds
Started Aug 21 12:40:59 PM UTC 24
Finished Aug 21 12:43:50 PM UTC 24
Peak memory 321096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4264207845 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4264207845
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.673673604
Short name T296
Test name
Test status
Simulation time 103950409317 ps
CPU time 2303.29 seconds
Started Aug 21 12:40:48 PM UTC 24
Finished Aug 21 01:19:39 PM UTC 24
Peak memory 1266476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=673673604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.kmac_stress_all.673673604 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.175959947
Short name T30
Test name
Test status
Simulation time 211211818 ps
CPU time 4.55 seconds
Started Aug 21 12:40:10 PM UTC 24
Finished Aug 21 12:40:16 PM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=175959947 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.175959947 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.1184329750
Short name T31
Test name
Test status
Simulation time 102524768 ps
CPU time 4.88 seconds
Started Aug 21 12:40:11 PM UTC 24
Finished Aug 21 12:40:17 PM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1184329750 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1184329
750 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.3735525604
Short name T2
Test name
Test status
Simulation time 1217448553 ps
CPU time 44.33 seconds
Started Aug 21 12:38:47 PM UTC 24
Finished Aug 21 12:39:33 PM UTC 24
Peak memory 234352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=3735525604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3735525604 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3547321485
Short name T3
Test name
Test status
Simulation time 7737798786 ps
CPU time 64.11 seconds
Started Aug 21 12:38:58 PM UTC 24
Finished Aug 21 12:40:04 PM UTC 24
Peak memory 258256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=3547321485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3547321485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.529952046
Short name T1
Test name
Test status
Simulation time 853679267 ps
CPU time 32.02 seconds
Started Aug 21 12:38:58 PM UTC 24
Finished Aug 21 12:39:32 PM UTC 24
Peak memory 229748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=529952046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.kmac_test_vectors_sha3_384.529952046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.425650371
Short name T43
Test name
Test status
Simulation time 6645363655 ps
CPU time 34.48 seconds
Started Aug 21 12:39:32 PM UTC 24
Finished Aug 21 12:40:10 PM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=425650371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.kmac_test_vectors_sha3_512.425650371 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2059647723
Short name T106
Test name
Test status
Simulation time 31439833409 ps
CPU time 247.69 seconds
Started Aug 21 12:39:34 PM UTC 24
Finished Aug 21 12:43:47 PM UTC 24
Peak memory 446660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2059647723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2059647723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3818121092
Short name T51
Test name
Test status
Simulation time 13238509556 ps
CPU time 215.59 seconds
Started Aug 21 12:40:05 PM UTC 24
Finished Aug 21 12:43:46 PM UTC 24
Peak memory 362752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3818121092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3818121092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.2591878978
Short name T73
Test name
Test status
Simulation time 56805677 ps
CPU time 1.24 seconds
Started Aug 21 12:45:59 PM UTC 24
Finished Aug 21 12:46:03 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2591878978
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.25918
78978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.3301161802
Short name T27
Test name
Test status
Simulation time 71103617678 ps
CPU time 386.45 seconds
Started Aug 21 12:43:47 PM UTC 24
Finished Aug 21 12:50:20 PM UTC 24
Peak memory 354564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33011618
02 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kma
c_app_with_partial_data.3301161802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.2065295038
Short name T141
Test name
Test status
Simulation time 65483935570 ps
CPU time 1458.35 seconds
Started Aug 21 12:41:52 PM UTC 24
Finished Aug 21 01:06:27 PM UTC 24
Peak memory 256320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20652950
38 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_wr
ite.2065295038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3830023321
Short name T23
Test name
Test status
Simulation time 17901819564 ps
CPU time 78.84 seconds
Started Aug 21 12:44:15 PM UTC 24
Finished Aug 21 12:45:37 PM UTC 24
Peak memory 237744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830023321 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.383
0023321 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.1703672323
Short name T72
Test name
Test status
Simulation time 41356905 ps
CPU time 1.39 seconds
Started Aug 21 12:44:37 PM UTC 24
Finished Aug 21 12:44:40 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1703672323 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1
703672323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1532265233
Short name T34
Test name
Test status
Simulation time 56150667571 ps
CPU time 404.36 seconds
Started Aug 21 12:43:47 PM UTC 24
Finished Aug 21 12:50:38 PM UTC 24
Peak memory 442600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15322652
33 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entr
opy_refresh.1532265233 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_error.1508402419
Short name T18
Test name
Test status
Simulation time 146483940132 ps
CPU time 772.34 seconds
Started Aug 21 12:44:04 PM UTC 24
Finished Aug 21 12:57:06 PM UTC 24
Peak memory 678204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1508402419 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1508402419 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.3082340527
Short name T267
Test name
Test status
Simulation time 169677339702 ps
CPU time 1983.08 seconds
Started Aug 21 12:41:12 PM UTC 24
Finished Aug 21 01:14:37 PM UTC 24
Peak memory 2128136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30823
40527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.km
ac_long_msg_and_output.3082340527 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.4083494828
Short name T32
Test name
Test status
Simulation time 42339517486 ps
CPU time 136.39 seconds
Started Aug 21 12:43:52 PM UTC 24
Finished Aug 21 12:46:12 PM UTC 24
Peak memory 307896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083494828 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.4083494828 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.4252280403
Short name T24
Test name
Test status
Simulation time 46042614942 ps
CPU time 290.23 seconds
Started Aug 21 12:41:32 PM UTC 24
Finished Aug 21 12:46:27 PM UTC 24
Peak memory 309552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425228
0403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.
4252280403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.343085351
Short name T47
Test name
Test status
Simulation time 3774343221 ps
CPU time 18.19 seconds
Started Aug 21 12:41:10 PM UTC 24
Finished Aug 21 12:41:30 PM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343085351 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.343085351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.3336012113
Short name T71
Test name
Test status
Simulation time 52270753868 ps
CPU time 1301.65 seconds
Started Aug 21 12:45:04 PM UTC 24
Finished Aug 21 01:07:01 PM UTC 24
Peak memory 449300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3336012113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.kmac_stress_all.3336012113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.1253903872
Short name T49
Test name
Test status
Simulation time 393454852 ps
CPU time 4.99 seconds
Started Aug 21 12:43:31 PM UTC 24
Finished Aug 21 12:43:38 PM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1253903872 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.1253903872 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1723068079
Short name T50
Test name
Test status
Simulation time 43224513 ps
CPU time 4.26 seconds
Started Aug 21 12:43:38 PM UTC 24
Finished Aug 21 12:43:44 PM UTC 24
Peak memory 229768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723068079 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1723068
079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.4191428128
Short name T439
Test name
Test status
Simulation time 671950820443 ps
CPU time 3392.97 seconds
Started Aug 21 12:41:57 PM UTC 24
Finished Aug 21 01:39:08 PM UTC 24
Peak memory 3242236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=4191428128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.kmac_test_vectors_sha3_224.4191428128 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1636100724
Short name T321
Test name
Test status
Simulation time 243635057953 ps
CPU time 2414.03 seconds
Started Aug 21 12:42:16 PM UTC 24
Finished Aug 21 01:22:57 PM UTC 24
Peak memory 3023008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=1636100724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1636100724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1162625837
Short name T241
Test name
Test status
Simulation time 13788845650 ps
CPU time 1687.77 seconds
Started Aug 21 12:42:47 PM UTC 24
Finished Aug 21 01:11:16 PM UTC 24
Peak memory 919704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=1162625837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1162625837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.471322127
Short name T48
Test name
Test status
Simulation time 2269263235 ps
CPU time 24.89 seconds
Started Aug 21 12:43:04 PM UTC 24
Finished Aug 21 12:43:30 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=471322127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.kmac_test_vectors_sha3_512.471322127 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.3505275457
Short name T272
Test name
Test status
Simulation time 91422703871 ps
CPU time 1863.37 seconds
Started Aug 21 12:43:22 PM UTC 24
Finished Aug 21 01:14:47 PM UTC 24
Peak memory 1093792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3505275457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3505275457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.1564858071
Short name T249
Test name
Test status
Simulation time 121860691 ps
CPU time 1.41 seconds
Started Aug 21 01:12:24 PM UTC 24
Finished Aug 21 01:12:27 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1564858071
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1564
858071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_app.1904384958
Short name T261
Test name
Test status
Simulation time 7694071937 ps
CPU time 147.93 seconds
Started Aug 21 01:11:29 PM UTC 24
Finished Aug 21 01:14:00 PM UTC 24
Peak memory 272636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19043849
58 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1904384958
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.1172399137
Short name T376
Test name
Test status
Simulation time 89210975691 ps
CPU time 1150.68 seconds
Started Aug 21 01:11:23 PM UTC 24
Finished Aug 21 01:30:48 PM UTC 24
Peak memory 264508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11723991
37 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_w
rite.1172399137 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.3745011627
Short name T82
Test name
Test status
Simulation time 107874565 ps
CPU time 1.67 seconds
Started Aug 21 01:12:18 PM UTC 24
Finished Aug 21 01:12:21 PM UTC 24
Peak memory 227400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3745011627 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.37
45011627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.45756127
Short name T247
Test name
Test status
Simulation time 45040977 ps
CPU time 1.75 seconds
Started Aug 21 01:12:19 PM UTC 24
Finished Aug 21 01:12:22 PM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45756127 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.45
756127 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.51352180
Short name T284
Test name
Test status
Simulation time 38588322143 ps
CPU time 251.25 seconds
Started Aug 21 01:11:38 PM UTC 24
Finished Aug 21 01:15:53 PM UTC 24
Peak memory 401664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51352180
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entro
py_refresh.51352180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_error.3143370746
Short name T265
Test name
Test status
Simulation time 3909190280 ps
CPU time 163.23 seconds
Started Aug 21 01:11:45 PM UTC 24
Finished Aug 21 01:14:31 PM UTC 24
Peak memory 332028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3143370746 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3143370746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.1497944635
Short name T245
Test name
Test status
Simulation time 4308572074 ps
CPU time 8.72 seconds
Started Aug 21 01:12:07 PM UTC 24
Finished Aug 21 01:12:17 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1497944635 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1497944635 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.1552159448
Short name T54
Test name
Test status
Simulation time 134043052 ps
CPU time 2.26 seconds
Started Aug 21 01:12:21 PM UTC 24
Finished Aug 21 01:12:25 PM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1552159448 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1552159448 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2208640937
Short name T525
Test name
Test status
Simulation time 64380003034 ps
CPU time 2340.37 seconds
Started Aug 21 01:11:12 PM UTC 24
Finished Aug 21 01:50:40 PM UTC 24
Peak memory 2638136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22086
40937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.k
mac_long_msg_and_output.2208640937 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.524463807
Short name T254
Test name
Test status
Simulation time 5294149508 ps
CPU time 140.41 seconds
Started Aug 21 01:11:16 PM UTC 24
Finished Aug 21 01:13:40 PM UTC 24
Peak memory 329988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=524463
807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.
524463807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.2176878393
Short name T246
Test name
Test status
Simulation time 1870340703 ps
CPU time 64.76 seconds
Started Aug 21 01:11:11 PM UTC 24
Finished Aug 21 01:12:18 PM UTC 24
Peak memory 235844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176878393 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2176878393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.2913366449
Short name T381
Test name
Test status
Simulation time 41121259045 ps
CPU time 1122.3 seconds
Started Aug 21 01:12:23 PM UTC 24
Finished Aug 21 01:31:18 PM UTC 24
Peak memory 737988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2913366449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 10.kmac_stress_all.2913366449 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.2624644816
Short name T259
Test name
Test status
Simulation time 24518057 ps
CPU time 1.14 seconds
Started Aug 21 01:13:49 PM UTC 24
Finished Aug 21 01:13:52 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2624644816
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2624
644816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_app.3503745281
Short name T279
Test name
Test status
Simulation time 16608181169 ps
CPU time 159.27 seconds
Started Aug 21 01:12:53 PM UTC 24
Finished Aug 21 01:15:35 PM UTC 24
Peak memory 344312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35037452
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3503745281
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.3133305699
Short name T325
Test name
Test status
Simulation time 16255350715 ps
CPU time 626.9 seconds
Started Aug 21 01:12:51 PM UTC 24
Finished Aug 21 01:23:26 PM UTC 24
Peak memory 254320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31333056
99 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_w
rite.3133305699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.1439763625
Short name T256
Test name
Test status
Simulation time 26821585 ps
CPU time 1.57 seconds
Started Aug 21 01:13:40 PM UTC 24
Finished Aug 21 01:13:44 PM UTC 24
Peak memory 227380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1439763625 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.14
39763625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.929217688
Short name T258
Test name
Test status
Simulation time 44603639 ps
CPU time 1.27 seconds
Started Aug 21 01:13:43 PM UTC 24
Finished Aug 21 01:13:47 PM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=929217688 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.9
29217688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.4182101281
Short name T306
Test name
Test status
Simulation time 30526097413 ps
CPU time 463.21 seconds
Started Aug 21 01:12:56 PM UTC 24
Finished Aug 21 01:20:46 PM UTC 24
Peak memory 369028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41821012
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_ent
ropy_refresh.4182101281 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_error.69000126
Short name T274
Test name
Test status
Simulation time 1284974877 ps
CPU time 132.02 seconds
Started Aug 21 01:12:58 PM UTC 24
Finished Aug 21 01:15:13 PM UTC 24
Peak memory 280820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69000126 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.69000126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.41665394
Short name T257
Test name
Test status
Simulation time 1932552918 ps
CPU time 12.5 seconds
Started Aug 21 01:13:31 PM UTC 24
Finished Aug 21 01:13:45 PM UTC 24
Peak memory 229556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41665394 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.41665394 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.1502866923
Short name T266
Test name
Test status
Simulation time 2839619678 ps
CPU time 48.91 seconds
Started Aug 21 01:13:44 PM UTC 24
Finished Aug 21 01:14:36 PM UTC 24
Peak memory 262476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1502866923 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1502866923 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1940330146
Short name T667
Test name
Test status
Simulation time 31211915256 ps
CPU time 3460.65 seconds
Started Aug 21 01:12:28 PM UTC 24
Finished Aug 21 02:10:46 PM UTC 24
Peak memory 2027832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19403
30146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.k
mac_long_msg_and_output.1940330146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.1214136214
Short name T285
Test name
Test status
Simulation time 24105241244 ps
CPU time 197.15 seconds
Started Aug 21 01:12:40 PM UTC 24
Finished Aug 21 01:16:01 PM UTC 24
Peak memory 401664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121413
6214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload
.1214136214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.3410505683
Short name T252
Test name
Test status
Simulation time 733553058 ps
CPU time 25.31 seconds
Started Aug 21 01:12:26 PM UTC 24
Finished Aug 21 01:12:52 PM UTC 24
Peak memory 235688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410505683 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3410505683 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.2876912813
Short name T273
Test name
Test status
Simulation time 29286239 ps
CPU time 1.19 seconds
Started Aug 21 01:14:47 PM UTC 24
Finished Aug 21 01:14:49 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2876912813
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2876
912813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_app.3579458795
Short name T164
Test name
Test status
Simulation time 16275550304 ps
CPU time 311.04 seconds
Started Aug 21 01:14:08 PM UTC 24
Finished Aug 21 01:19:24 PM UTC 24
Peak memory 332076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35794587
95 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3579458795
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.84414501
Short name T370
Test name
Test status
Simulation time 20401336303 ps
CPU time 921.41 seconds
Started Aug 21 01:14:05 PM UTC 24
Finished Aug 21 01:29:38 PM UTC 24
Peak memory 260480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84414501
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_wri
te.84414501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.581012738
Short name T275
Test name
Test status
Simulation time 2041635422 ps
CPU time 37.4 seconds
Started Aug 21 01:14:38 PM UTC 24
Finished Aug 21 01:15:17 PM UTC 24
Peak memory 235580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=581012738 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.581
012738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2394290114
Short name T269
Test name
Test status
Simulation time 26380701 ps
CPU time 1.37 seconds
Started Aug 21 01:14:40 PM UTC 24
Finished Aug 21 01:14:42 PM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2394290114 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.
2394290114 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2694991882
Short name T85
Test name
Test status
Simulation time 13263408676 ps
CPU time 80.26 seconds
Started Aug 21 01:14:22 PM UTC 24
Finished Aug 21 01:15:44 PM UTC 24
Peak memory 295204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26949918
82 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_ent
ropy_refresh.2694991882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_error.3717306876
Short name T294
Test name
Test status
Simulation time 20354889503 ps
CPU time 192.47 seconds
Started Aug 21 01:14:32 PM UTC 24
Finished Aug 21 01:17:48 PM UTC 24
Peak memory 360784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3717306876 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3717306876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3006828730
Short name T270
Test name
Test status
Simulation time 258034479 ps
CPU time 4.89 seconds
Started Aug 21 01:14:37 PM UTC 24
Finished Aug 21 01:14:43 PM UTC 24
Peak memory 227592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3006828730 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3006828730 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.212605210
Short name T271
Test name
Test status
Simulation time 204070204 ps
CPU time 2.38 seconds
Started Aug 21 01:14:43 PM UTC 24
Finished Aug 21 01:14:46 PM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212605210 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.212605210 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.689961207
Short name T474
Test name
Test status
Simulation time 63154845780 ps
CPU time 1788.65 seconds
Started Aug 21 01:13:55 PM UTC 24
Finished Aug 21 01:44:04 PM UTC 24
Peak memory 1122552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68996
1207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.km
ac_long_msg_and_output.689961207 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.396619393
Short name T297
Test name
Test status
Simulation time 15429773421 ps
CPU time 356.36 seconds
Started Aug 21 01:14:01 PM UTC 24
Finished Aug 21 01:20:02 PM UTC 24
Peak memory 575800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396619
393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.
396619393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2682619092
Short name T268
Test name
Test status
Simulation time 1631231411 ps
CPU time 43.17 seconds
Started Aug 21 01:13:53 PM UTC 24
Finished Aug 21 01:14:38 PM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2682619092 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2682619092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.1140925110
Short name T441
Test name
Test status
Simulation time 90544344718 ps
CPU time 1463.21 seconds
Started Aug 21 01:14:45 PM UTC 24
Finished Aug 21 01:39:25 PM UTC 24
Peak memory 492212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1140925110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 12.kmac_stress_all.1140925110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.701674531
Short name T283
Test name
Test status
Simulation time 41858120 ps
CPU time 1.23 seconds
Started Aug 21 01:15:48 PM UTC 24
Finished Aug 21 01:15:50 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701674531 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.70167
4531 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_app.3386762576
Short name T307
Test name
Test status
Simulation time 14463681512 ps
CPU time 344.74 seconds
Started Aug 21 01:15:18 PM UTC 24
Finished Aug 21 01:21:08 PM UTC 24
Peak memory 487804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33867625
76 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3386762576
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2340973768
Short name T330
Test name
Test status
Simulation time 56423051380 ps
CPU time 554.93 seconds
Started Aug 21 01:15:14 PM UTC 24
Finished Aug 21 01:24:36 PM UTC 24
Peak memory 254252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23409737
68 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_w
rite.2340973768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.814072371
Short name T287
Test name
Test status
Simulation time 3844645453 ps
CPU time 58.1 seconds
Started Aug 21 01:15:37 PM UTC 24
Finished Aug 21 01:16:36 PM UTC 24
Peak memory 235652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=814072371 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.814
072371 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.3619356786
Short name T282
Test name
Test status
Simulation time 100883062 ps
CPU time 1.68 seconds
Started Aug 21 01:15:45 PM UTC 24
Finished Aug 21 01:15:47 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3619356786 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.
3619356786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1839961813
Short name T312
Test name
Test status
Simulation time 35359646571 ps
CPU time 365.26 seconds
Started Aug 21 01:15:26 PM UTC 24
Finished Aug 21 01:21:38 PM UTC 24
Peak memory 323968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18399618
13 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_ent
ropy_refresh.1839961813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1349552737
Short name T288
Test name
Test status
Simulation time 3558595722 ps
CPU time 64.95 seconds
Started Aug 21 01:15:30 PM UTC 24
Finished Aug 21 01:16:38 PM UTC 24
Peak memory 268596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349552737 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1349552737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.956888538
Short name T281
Test name
Test status
Simulation time 976807813 ps
CPU time 10.63 seconds
Started Aug 21 01:15:35 PM UTC 24
Finished Aug 21 01:15:47 PM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=956888538 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.956888538 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1551398193
Short name T617
Test name
Test status
Simulation time 22617382310 ps
CPU time 2882.74 seconds
Started Aug 21 01:14:50 PM UTC 24
Finished Aug 21 02:03:27 PM UTC 24
Peak memory 1564916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15513
98193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.k
mac_long_msg_and_output.1551398193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.3917910787
Short name T336
Test name
Test status
Simulation time 31105418578 ps
CPU time 614.73 seconds
Started Aug 21 01:14:52 PM UTC 24
Finished Aug 21 01:25:15 PM UTC 24
Peak memory 645428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=391791
0787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload
.3917910787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.1787780635
Short name T278
Test name
Test status
Simulation time 959451974 ps
CPU time 44.88 seconds
Started Aug 21 01:14:48 PM UTC 24
Finished Aug 21 01:15:34 PM UTC 24
Peak memory 235752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1787780635 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1787780635 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.154443623
Short name T362
Test name
Test status
Simulation time 28403033377 ps
CPU time 709.88 seconds
Started Aug 21 01:15:48 PM UTC 24
Finished Aug 21 01:27:46 PM UTC 24
Peak memory 701136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=154443623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.kmac_stress_all.154443623 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.1312574547
Short name T293
Test name
Test status
Simulation time 19773113 ps
CPU time 1.31 seconds
Started Aug 21 01:16:54 PM UTC 24
Finished Aug 21 01:16:58 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1312574547
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1312
574547 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_app.1135051250
Short name T302
Test name
Test status
Simulation time 16714758132 ps
CPU time 252.52 seconds
Started Aug 21 01:16:06 PM UTC 24
Finished Aug 21 01:20:23 PM UTC 24
Peak memory 299452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11350512
50 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1135051250
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.3678003424
Short name T403
Test name
Test status
Simulation time 18947036349 ps
CPU time 1075.19 seconds
Started Aug 21 01:16:01 PM UTC 24
Finished Aug 21 01:34:10 PM UTC 24
Peak memory 248152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36780034
24 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_w
rite.3678003424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2606056484
Short name T290
Test name
Test status
Simulation time 87208331 ps
CPU time 1.79 seconds
Started Aug 21 01:16:39 PM UTC 24
Finished Aug 21 01:16:43 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2606056484 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.26
06056484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1117545422
Short name T291
Test name
Test status
Simulation time 103044472 ps
CPU time 1.59 seconds
Started Aug 21 01:16:44 PM UTC 24
Finished Aug 21 01:16:47 PM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117545422 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.
1117545422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.1507586464
Short name T289
Test name
Test status
Simulation time 637334763 ps
CPU time 15.86 seconds
Started Aug 21 01:16:21 PM UTC 24
Finished Aug 21 01:16:38 PM UTC 24
Peak memory 244152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15075864
64 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_ent
ropy_refresh.1507586464 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_error.4005199513
Short name T298
Test name
Test status
Simulation time 25010805334 ps
CPU time 206.05 seconds
Started Aug 21 01:16:38 PM UTC 24
Finished Aug 21 01:20:08 PM UTC 24
Peak memory 393500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4005199513 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.4005199513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.4121011186
Short name T292
Test name
Test status
Simulation time 2665823006 ps
CPU time 11.92 seconds
Started Aug 21 01:16:39 PM UTC 24
Finished Aug 21 01:16:53 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4121011186 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.4121011186 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.2968648935
Short name T56
Test name
Test status
Simulation time 69634835 ps
CPU time 2.27 seconds
Started Aug 21 01:16:48 PM UTC 24
Finished Aug 21 01:16:52 PM UTC 24
Peak memory 231840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968648935 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2968648935 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.2091857329
Short name T373
Test name
Test status
Simulation time 6648883091 ps
CPU time 869.99 seconds
Started Aug 21 01:15:51 PM UTC 24
Finished Aug 21 01:30:33 PM UTC 24
Peak memory 622904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20918
57329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.k
mac_long_msg_and_output.2091857329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.1475364365
Short name T317
Test name
Test status
Simulation time 36740139522 ps
CPU time 395.8 seconds
Started Aug 21 01:15:54 PM UTC 24
Finished Aug 21 01:22:35 PM UTC 24
Peak memory 356656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=147536
4365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload
.1475364365 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3818955962
Short name T286
Test name
Test status
Simulation time 854123710 ps
CPU time 12.88 seconds
Started Aug 21 01:15:51 PM UTC 24
Finished Aug 21 01:16:05 PM UTC 24
Peak memory 235752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3818955962 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3818955962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.2096394822
Short name T388
Test name
Test status
Simulation time 101051021336 ps
CPU time 912.37 seconds
Started Aug 21 01:16:53 PM UTC 24
Finished Aug 21 01:32:17 PM UTC 24
Peak memory 883020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2096394822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_stress_all.2096394822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.2830009966
Short name T303
Test name
Test status
Simulation time 20720935 ps
CPU time 1.29 seconds
Started Aug 21 01:20:23 PM UTC 24
Finished Aug 21 01:20:26 PM UTC 24
Peak memory 226000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2830009966
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2830
009966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3373129441
Short name T314
Test name
Test status
Simulation time 5426316557 ps
CPU time 167.73 seconds
Started Aug 21 01:19:24 PM UTC 24
Finished Aug 21 01:22:15 PM UTC 24
Peak memory 282928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33731294
41 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3373129441
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.793958110
Short name T433
Test name
Test status
Simulation time 58658251998 ps
CPU time 1152.93 seconds
Started Aug 21 01:18:59 PM UTC 24
Finished Aug 21 01:38:27 PM UTC 24
Peak memory 252152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79395811
0 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_wr
ite.793958110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2263307133
Short name T304
Test name
Test status
Simulation time 240474503 ps
CPU time 24.94 seconds
Started Aug 21 01:20:09 PM UTC 24
Finished Aug 21 01:20:35 PM UTC 24
Peak memory 243980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263307133 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.22
63307133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1802379898
Short name T300
Test name
Test status
Simulation time 34646278 ps
CPU time 1.75 seconds
Started Aug 21 01:20:17 PM UTC 24
Finished Aug 21 01:20:20 PM UTC 24
Peak memory 227532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1802379898 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.
1802379898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.4232894687
Short name T305
Test name
Test status
Simulation time 3220396639 ps
CPU time 52.91 seconds
Started Aug 21 01:19:40 PM UTC 24
Finished Aug 21 01:20:36 PM UTC 24
Peak memory 264416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42328946
87 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_ent
ropy_refresh.4232894687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_error.892057379
Short name T326
Test name
Test status
Simulation time 21526161173 ps
CPU time 236.89 seconds
Started Aug 21 01:19:56 PM UTC 24
Finished Aug 21 01:23:56 PM UTC 24
Peak memory 350528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892057379 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.892057379 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.3015565234
Short name T299
Test name
Test status
Simulation time 1058975113 ps
CPU time 11.82 seconds
Started Aug 21 01:20:03 PM UTC 24
Finished Aug 21 01:20:16 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3015565234 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3015565234 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.791838537
Short name T63
Test name
Test status
Simulation time 714846041 ps
CPU time 8.07 seconds
Started Aug 21 01:20:21 PM UTC 24
Finished Aug 21 01:20:30 PM UTC 24
Peak memory 244236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791838537 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.791838537 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2798394224
Short name T585
Test name
Test status
Simulation time 60354983526 ps
CPU time 2473.39 seconds
Started Aug 21 01:17:39 PM UTC 24
Finished Aug 21 01:59:18 PM UTC 24
Peak memory 2933040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27983
94224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.k
mac_long_msg_and_output.2798394224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.970771048
Short name T353
Test name
Test status
Simulation time 61891020998 ps
CPU time 514.29 seconds
Started Aug 21 01:17:49 PM UTC 24
Finished Aug 21 01:26:30 PM UTC 24
Peak memory 520512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=970771
048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.
970771048 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.3859185284
Short name T295
Test name
Test status
Simulation time 24763319008 ps
CPU time 115.71 seconds
Started Aug 21 01:16:58 PM UTC 24
Finished Aug 21 01:18:58 PM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3859185284 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3859185284 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.766639529
Short name T442
Test name
Test status
Simulation time 114938283535 ps
CPU time 1152.4 seconds
Started Aug 21 01:20:23 PM UTC 24
Finished Aug 21 01:39:50 PM UTC 24
Peak memory 563848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=766639529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.kmac_stress_all.766639529 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.4180099574
Short name T313
Test name
Test status
Simulation time 47339243 ps
CPU time 1.27 seconds
Started Aug 21 01:21:39 PM UTC 24
Finished Aug 21 01:21:42 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180099574
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.4180
099574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_app.1768616971
Short name T354
Test name
Test status
Simulation time 39653679652 ps
CPU time 358.16 seconds
Started Aug 21 01:20:47 PM UTC 24
Finished Aug 21 01:26:50 PM UTC 24
Peak memory 440572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17686169
71 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1768616971
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.320891363
Short name T494
Test name
Test status
Simulation time 14407249514 ps
CPU time 1521.2 seconds
Started Aug 21 01:20:37 PM UTC 24
Finished Aug 21 01:46:15 PM UTC 24
Peak memory 256312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32089136
3 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_wr
ite.320891363 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.1966240127
Short name T310
Test name
Test status
Simulation time 41906780 ps
CPU time 1.6 seconds
Started Aug 21 01:21:24 PM UTC 24
Finished Aug 21 01:21:28 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1966240127 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.19
66240127 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.1899301550
Short name T311
Test name
Test status
Simulation time 53939810 ps
CPU time 1.59 seconds
Started Aug 21 01:21:28 PM UTC 24
Finished Aug 21 01:21:31 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1899301550 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.
1899301550 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.1600856738
Short name T340
Test name
Test status
Simulation time 14081479572 ps
CPU time 251.15 seconds
Started Aug 21 01:21:03 PM UTC 24
Finished Aug 21 01:25:18 PM UTC 24
Peak memory 317768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16008567
38 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_ent
ropy_refresh.1600856738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_error.3127520680
Short name T350
Test name
Test status
Simulation time 8566374225 ps
CPU time 305.34 seconds
Started Aug 21 01:21:09 PM UTC 24
Finished Aug 21 01:26:19 PM UTC 24
Peak memory 350520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3127520680 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3127520680 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.1823309769
Short name T309
Test name
Test status
Simulation time 2743831487 ps
CPU time 9.1 seconds
Started Aug 21 01:21:13 PM UTC 24
Finished Aug 21 01:21:24 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823309769 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1823309769 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.2295431138
Short name T55
Test name
Test status
Simulation time 55016695 ps
CPU time 1.82 seconds
Started Aug 21 01:21:32 PM UTC 24
Finished Aug 21 01:21:37 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295431138 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2295431138 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.2446591555
Short name T392
Test name
Test status
Simulation time 52065994515 ps
CPU time 737.8 seconds
Started Aug 21 01:20:31 PM UTC 24
Finished Aug 21 01:32:59 PM UTC 24
Peak memory 606516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24465
91555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.k
mac_long_msg_and_output.2446591555 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.3437584067
Short name T357
Test name
Test status
Simulation time 11495274929 ps
CPU time 385.81 seconds
Started Aug 21 01:20:37 PM UTC 24
Finished Aug 21 01:27:08 PM UTC 24
Peak memory 358628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=343758
4067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload
.3437584067 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.2029306249
Short name T316
Test name
Test status
Simulation time 3837068396 ps
CPU time 122.64 seconds
Started Aug 21 01:20:26 PM UTC 24
Finished Aug 21 01:22:32 PM UTC 24
Peak memory 235776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2029306249 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2029306249 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.1137672980
Short name T379
Test name
Test status
Simulation time 45328705930 ps
CPU time 544.5 seconds
Started Aug 21 01:21:38 PM UTC 24
Finished Aug 21 01:30:51 PM UTC 24
Peak memory 334140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1137672980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.kmac_stress_all.1137672980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.577192173
Short name T324
Test name
Test status
Simulation time 15364606 ps
CPU time 1.27 seconds
Started Aug 21 01:23:06 PM UTC 24
Finished Aug 21 01:23:09 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=577192173 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.57719
2173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_app.641481921
Short name T318
Test name
Test status
Simulation time 929421888 ps
CPU time 11.28 seconds
Started Aug 21 01:22:36 PM UTC 24
Finished Aug 21 01:22:48 PM UTC 24
Peak memory 235668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=64148192
1 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.641481921 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.599032280
Short name T361
Test name
Test status
Simulation time 2784947216 ps
CPU time 309.51 seconds
Started Aug 21 01:22:32 PM UTC 24
Finished Aug 21 01:27:46 PM UTC 24
Peak memory 248116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59903228
0 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_wr
ite.599032280 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1225278497
Short name T322
Test name
Test status
Simulation time 25959240 ps
CPU time 1.26 seconds
Started Aug 21 01:22:58 PM UTC 24
Finished Aug 21 01:23:01 PM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225278497 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.12
25278497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.2145550962
Short name T323
Test name
Test status
Simulation time 156070071 ps
CPU time 1.75 seconds
Started Aug 21 01:22:58 PM UTC 24
Finished Aug 21 01:23:02 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2145550962 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.
2145550962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_error.913040817
Short name T328
Test name
Test status
Simulation time 4745448312 ps
CPU time 87.51 seconds
Started Aug 21 01:22:49 PM UTC 24
Finished Aug 21 01:24:20 PM UTC 24
Peak memory 280872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=913040817 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.913040817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.3337414561
Short name T320
Test name
Test status
Simulation time 1471715313 ps
CPU time 3.09 seconds
Started Aug 21 01:22:51 PM UTC 24
Finished Aug 21 01:22:57 PM UTC 24
Peak memory 227596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337414561 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3337414561 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.3248062490
Short name T57
Test name
Test status
Simulation time 37939597 ps
CPU time 1.59 seconds
Started Aug 21 01:23:02 PM UTC 24
Finished Aug 21 01:23:05 PM UTC 24
Peak memory 229332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3248062490 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3248062490 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1946489423
Short name T691
Test name
Test status
Simulation time 68730408442 ps
CPU time 3317.26 seconds
Started Aug 21 01:22:17 PM UTC 24
Finished Aug 21 02:18:12 PM UTC 24
Peak memory 3379608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19464
89423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.k
mac_long_msg_and_output.1946489423 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.2403912783
Short name T342
Test name
Test status
Simulation time 10723131333 ps
CPU time 181.43 seconds
Started Aug 21 01:22:30 PM UTC 24
Finished Aug 21 01:25:34 PM UTC 24
Peak memory 303408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240391
2783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload
.2403912783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.2171404327
Short name T319
Test name
Test status
Simulation time 5055287038 ps
CPU time 64.1 seconds
Started Aug 21 01:21:43 PM UTC 24
Finished Aug 21 01:22:50 PM UTC 24
Peak memory 235844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2171404327 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2171404327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.781689410
Short name T443
Test name
Test status
Simulation time 21821733959 ps
CPU time 998.31 seconds
Started Aug 21 01:23:02 PM UTC 24
Finished Aug 21 01:39:53 PM UTC 24
Peak memory 459380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=781689410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.kmac_stress_all.781689410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.1327899843
Short name T339
Test name
Test status
Simulation time 134533912 ps
CPU time 1.35 seconds
Started Aug 21 01:25:13 PM UTC 24
Finished Aug 21 01:25:15 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1327899843
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1327
899843 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_app.1044029405
Short name T372
Test name
Test status
Simulation time 92281662476 ps
CPU time 366.81 seconds
Started Aug 21 01:24:13 PM UTC 24
Finished Aug 21 01:30:26 PM UTC 24
Peak memory 475388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10440294
05 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1044029405
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.88025718
Short name T332
Test name
Test status
Simulation time 4571191727 ps
CPU time 55.66 seconds
Started Aug 21 01:23:57 PM UTC 24
Finished Aug 21 01:24:55 PM UTC 24
Peak memory 233968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=88025718
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_wri
te.88025718 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2177133569
Short name T337
Test name
Test status
Simulation time 1499899414 ps
CPU time 28.05 seconds
Started Aug 21 01:24:46 PM UTC 24
Finished Aug 21 01:25:15 PM UTC 24
Peak memory 234988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177133569 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.21
77133569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2031817778
Short name T338
Test name
Test status
Simulation time 369379313 ps
CPU time 18.02 seconds
Started Aug 21 01:24:56 PM UTC 24
Finished Aug 21 01:25:15 PM UTC 24
Peak memory 245856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2031817778 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.
2031817778 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.2190931064
Short name T335
Test name
Test status
Simulation time 1665729071 ps
CPU time 48.26 seconds
Started Aug 21 01:24:21 PM UTC 24
Finished Aug 21 01:25:12 PM UTC 24
Peak memory 252100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21909310
64 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_ent
ropy_refresh.2190931064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3971692113
Short name T344
Test name
Test status
Simulation time 5895583293 ps
CPU time 71.46 seconds
Started Aug 21 01:24:34 PM UTC 24
Finished Aug 21 01:25:48 PM UTC 24
Peak memory 284988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3971692113 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3971692113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.1496649493
Short name T331
Test name
Test status
Simulation time 1195379565 ps
CPU time 5.42 seconds
Started Aug 21 01:24:37 PM UTC 24
Finished Aug 21 01:24:45 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1496649493 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1496649493 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.1345680685
Short name T334
Test name
Test status
Simulation time 34406834 ps
CPU time 1.68 seconds
Started Aug 21 01:24:58 PM UTC 24
Finished Aug 21 01:25:01 PM UTC 24
Peak memory 231320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1345680685 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1345680685 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3317529282
Short name T555
Test name
Test status
Simulation time 82589296043 ps
CPU time 1875.67 seconds
Started Aug 21 01:23:11 PM UTC 24
Finished Aug 21 01:54:48 PM UTC 24
Peak memory 2136380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33175
29282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.k
mac_long_msg_and_output.3317529282 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.1495173120
Short name T333
Test name
Test status
Simulation time 3447596088 ps
CPU time 87.83 seconds
Started Aug 21 01:23:27 PM UTC 24
Finished Aug 21 01:24:57 PM UTC 24
Peak memory 258332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=149517
3120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload
.1495173120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.2621195575
Short name T329
Test name
Test status
Simulation time 3232569751 ps
CPU time 81.76 seconds
Started Aug 21 01:23:09 PM UTC 24
Finished Aug 21 01:24:33 PM UTC 24
Peak memory 235848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621195575 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2621195575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.4021551562
Short name T385
Test name
Test status
Simulation time 17038144023 ps
CPU time 417.38 seconds
Started Aug 21 01:25:02 PM UTC 24
Finished Aug 21 01:32:06 PM UTC 24
Peak memory 318096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=4021551562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_stress_all.4021551562 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.1372164016
Short name T349
Test name
Test status
Simulation time 202255453 ps
CPU time 1.33 seconds
Started Aug 21 01:25:55 PM UTC 24
Finished Aug 21 01:25:58 PM UTC 24
Peak memory 225340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372164016
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1372
164016 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_app.3233928457
Short name T383
Test name
Test status
Simulation time 91002969740 ps
CPU time 396.88 seconds
Started Aug 21 01:25:19 PM UTC 24
Finished Aug 21 01:32:02 PM UTC 24
Peak memory 508216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32339284
57 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3233928457
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.1464518038
Short name T380
Test name
Test status
Simulation time 15871448118 ps
CPU time 354.73 seconds
Started Aug 21 01:25:16 PM UTC 24
Finished Aug 21 01:31:16 PM UTC 24
Peak memory 244036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14645180
38 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_w
rite.1464518038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.2924141334
Short name T351
Test name
Test status
Simulation time 411691338 ps
CPU time 29.86 seconds
Started Aug 21 01:25:49 PM UTC 24
Finished Aug 21 01:26:21 PM UTC 24
Peak memory 251900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2924141334 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.29
24141334 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.866091944
Short name T348
Test name
Test status
Simulation time 72975922 ps
CPU time 1.66 seconds
Started Aug 21 01:25:51 PM UTC 24
Finished Aug 21 01:25:54 PM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=866091944 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.8
66091944 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.2282997078
Short name T363
Test name
Test status
Simulation time 5451590332 ps
CPU time 144.97 seconds
Started Aug 21 01:25:21 PM UTC 24
Finished Aug 21 01:27:49 PM UTC 24
Peak memory 309524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22829970
78 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_ent
ropy_refresh.2282997078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_error.3007271925
Short name T343
Test name
Test status
Simulation time 601572314 ps
CPU time 7.85 seconds
Started Aug 21 01:25:35 PM UTC 24
Finished Aug 21 01:25:45 PM UTC 24
Peak memory 234632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007271925 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3007271925 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1791526929
Short name T346
Test name
Test status
Simulation time 409552655 ps
CPU time 1.77 seconds
Started Aug 21 01:25:47 PM UTC 24
Finished Aug 21 01:25:50 PM UTC 24
Peak memory 224312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791526929 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1791526929 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.794823342
Short name T514
Test name
Test status
Simulation time 135776679784 ps
CPU time 1427.55 seconds
Started Aug 21 01:25:16 PM UTC 24
Finished Aug 21 01:49:20 PM UTC 24
Peak memory 1831228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79482
3342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.km
ac_long_msg_and_output.794823342 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.1619000929
Short name T347
Test name
Test status
Simulation time 779358359 ps
CPU time 35.51 seconds
Started Aug 21 01:25:16 PM UTC 24
Finished Aug 21 01:25:53 PM UTC 24
Peak memory 250312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161900
0929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload
.1619000929 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.3396235568
Short name T345
Test name
Test status
Simulation time 910170796 ps
CPU time 32.31 seconds
Started Aug 21 01:25:16 PM UTC 24
Finished Aug 21 01:25:50 PM UTC 24
Peak memory 235752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3396235568 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3396235568 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.286165318
Short name T368
Test name
Test status
Simulation time 44854817303 ps
CPU time 180.32 seconds
Started Aug 21 01:25:54 PM UTC 24
Finished Aug 21 01:28:57 PM UTC 24
Peak memory 278840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=286165318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.kmac_stress_all.286165318 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.1822672826
Short name T108
Test name
Test status
Simulation time 76313897 ps
CPU time 1.28 seconds
Started Aug 21 12:49:24 PM UTC 24
Finished Aug 21 12:49:27 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1822672826
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.18226
72826 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_app.887245179
Short name T196
Test name
Test status
Simulation time 13572819344 ps
CPU time 468.04 seconds
Started Aug 21 12:47:22 PM UTC 24
Finished Aug 21 12:55:16 PM UTC 24
Peak memory 510264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=88724517
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.887245179 +en
able_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3729963247
Short name T107
Test name
Test status
Simulation time 20923495153 ps
CPU time 341.99 seconds
Started Aug 21 12:47:26 PM UTC 24
Finished Aug 21 12:53:13 PM UTC 24
Peak memory 479544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37299632
47 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kma
c_app_with_partial_data.3729963247 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.3976516520
Short name T139
Test name
Test status
Simulation time 49843433111 ps
CPU time 602.75 seconds
Started Aug 21 12:46:13 PM UTC 24
Finished Aug 21 12:56:24 PM UTC 24
Peak memory 248124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39765165
20 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_wr
ite.3976516520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1969681010
Short name T133
Test name
Test status
Simulation time 1800445761 ps
CPU time 62.15 seconds
Started Aug 21 12:48:11 PM UTC 24
Finished Aug 21 12:49:16 PM UTC 24
Peak memory 245756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1969681010 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.196
9681010 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.1881835686
Short name T86
Test name
Test status
Simulation time 81822953 ps
CPU time 1.39 seconds
Started Aug 21 12:48:12 PM UTC 24
Finished Aug 21 12:48:15 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1881835686 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1
881835686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3629917405
Short name T6
Test name
Test status
Simulation time 3362988290 ps
CPU time 27.75 seconds
Started Aug 21 12:48:16 PM UTC 24
Finished Aug 21 12:48:45 PM UTC 24
Peak memory 235880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3629917405 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.362991740
5 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.4179049343
Short name T79
Test name
Test status
Simulation time 30673390570 ps
CPU time 180.52 seconds
Started Aug 21 12:47:30 PM UTC 24
Finished Aug 21 12:50:34 PM UTC 24
Peak memory 350464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41790493
43 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entr
opy_refresh.4179049343 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_error.3988619090
Short name T26
Test name
Test status
Simulation time 41507996205 ps
CPU time 209.12 seconds
Started Aug 21 12:47:34 PM UTC 24
Finished Aug 21 12:51:07 PM UTC 24
Peak memory 377140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988619090 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3988619090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.653268370
Short name T14
Test name
Test status
Simulation time 4957187520 ps
CPU time 18.68 seconds
Started Aug 21 12:47:52 PM UTC 24
Finished Aug 21 12:48:12 PM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=653268370 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.653268370 +enable_masking=1 +s
w_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2380805119
Short name T620
Test name
Test status
Simulation time 224715939908 ps
CPU time 4638.95 seconds
Started Aug 21 12:46:08 PM UTC 24
Finished Aug 21 02:04:19 PM UTC 24
Peak memory 4249932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23808
05119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.km
ac_long_msg_and_output.2380805119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.3541903485
Short name T65
Test name
Test status
Simulation time 59619658387 ps
CPU time 411.95 seconds
Started Aug 21 12:47:31 PM UTC 24
Finished Aug 21 12:54:29 PM UTC 24
Peak memory 508624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541903485 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3541903485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.3054764030
Short name T41
Test name
Test status
Simulation time 8961229866 ps
CPU time 113.76 seconds
Started Aug 21 12:49:17 PM UTC 24
Finished Aug 21 12:51:14 PM UTC 24
Peak memory 316940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3054764030 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3054764030
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.1215761168
Short name T21
Test name
Test status
Simulation time 14326751735 ps
CPU time 417.18 seconds
Started Aug 21 12:46:12 PM UTC 24
Finished Aug 21 12:53:15 PM UTC 24
Peak memory 547120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121576
1168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.
1215761168 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.1280684665
Short name T132
Test name
Test status
Simulation time 8142850468 ps
CPU time 58.24 seconds
Started Aug 21 12:46:03 PM UTC 24
Finished Aug 21 12:47:04 PM UTC 24
Peak memory 231928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1280684665 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1280684665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.1497043769
Short name T33
Test name
Test status
Simulation time 1355200022 ps
CPU time 64.84 seconds
Started Aug 21 12:49:04 PM UTC 24
Finished Aug 21 12:50:11 PM UTC 24
Peak memory 268924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1497043769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_stress_all.1497043769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.2310621900
Short name T184
Test name
Test status
Simulation time 239043543 ps
CPU time 3.9 seconds
Started Aug 21 12:47:10 PM UTC 24
Finished Aug 21 12:47:16 PM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2310621900 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.2310621900 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3594803471
Short name T185
Test name
Test status
Simulation time 38018275 ps
CPU time 2.84 seconds
Started Aug 21 12:47:17 PM UTC 24
Finished Aug 21 12:47:20 PM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594803471 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3594803
471 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.1362351597
Short name T391
Test name
Test status
Simulation time 129253545810 ps
CPU time 2765.71 seconds
Started Aug 21 12:46:20 PM UTC 24
Finished Aug 21 01:32:58 PM UTC 24
Peak memory 3260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=1362351597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1362351597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.149826690
Short name T176
Test name
Test status
Simulation time 4360080517 ps
CPU time 62.53 seconds
Started Aug 21 12:46:20 PM UTC 24
Finished Aug 21 12:47:25 PM UTC 24
Peak memory 258292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=149826690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.kmac_test_vectors_sha3_256.149826690 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.2634378927
Short name T260
Test name
Test status
Simulation time 54826600406 ps
CPU time 1624.92 seconds
Started Aug 21 12:46:28 PM UTC 24
Finished Aug 21 01:13:54 PM UTC 24
Peak memory 897176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=2634378927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2634378927 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.4079983541
Short name T183
Test name
Test status
Simulation time 4654657088 ps
CPU time 31.18 seconds
Started Aug 21 12:46:36 PM UTC 24
Finished Aug 21 12:47:09 PM UTC 24
Peak memory 233860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=4079983541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.kmac_test_vectors_sha3_512.4079983541 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3818898952
Short name T179
Test name
Test status
Simulation time 16982114403 ps
CPU time 342.49 seconds
Started Aug 21 12:46:43 PM UTC 24
Finished Aug 21 12:52:32 PM UTC 24
Peak memory 284912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3818898952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3818898952 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3536963349
Short name T358
Test name
Test status
Simulation time 50240695 ps
CPU time 1.16 seconds
Started Aug 21 01:27:08 PM UTC 24
Finished Aug 21 01:27:10 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3536963349
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3536
963349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_app.2935238230
Short name T352
Test name
Test status
Simulation time 1138275474 ps
CPU time 5.98 seconds
Started Aug 21 01:26:21 PM UTC 24
Finished Aug 21 01:26:29 PM UTC 24
Peak memory 231948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29352382
30 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2935238230
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.3117850527
Short name T436
Test name
Test status
Simulation time 30694999578 ps
CPU time 749.67 seconds
Started Aug 21 01:26:19 PM UTC 24
Finished Aug 21 01:38:58 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31178505
27 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_w
rite.3117850527 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.3324062532
Short name T365
Test name
Test status
Simulation time 14459800375 ps
CPU time 136.21 seconds
Started Aug 21 01:26:29 PM UTC 24
Finished Aug 21 01:28:48 PM UTC 24
Peak memory 276752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33240625
32 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_ent
ropy_refresh.3324062532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.1987822092
Short name T356
Test name
Test status
Simulation time 5845631577 ps
CPU time 15.12 seconds
Started Aug 21 01:26:51 PM UTC 24
Finished Aug 21 01:27:07 PM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1987822092 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1987822092 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2428282911
Short name T714
Test name
Test status
Simulation time 856402864929 ps
CPU time 5048.92 seconds
Started Aug 21 01:25:58 PM UTC 24
Finished Aug 21 02:51:01 PM UTC 24
Peak memory 4895048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24282
82911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.k
mac_long_msg_and_output.2428282911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.1813672371
Short name T393
Test name
Test status
Simulation time 52291308453 ps
CPU time 403.61 seconds
Started Aug 21 01:26:11 PM UTC 24
Finished Aug 21 01:33:01 PM UTC 24
Peak memory 475512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=181367
2371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload
.1813672371 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.453332126
Short name T359
Test name
Test status
Simulation time 3034028498 ps
CPU time 81.86 seconds
Started Aug 21 01:25:55 PM UTC 24
Finished Aug 21 01:27:19 PM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=453332126 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.453332126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2601823039
Short name T608
Test name
Test status
Simulation time 59918172351 ps
CPU time 2093.87 seconds
Started Aug 21 01:27:01 PM UTC 24
Finished Aug 21 02:02:19 PM UTC 24
Peak memory 1563280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2601823039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 20.kmac_stress_all.2601823039 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.2788846057
Short name T367
Test name
Test status
Simulation time 28115841 ps
CPU time 1.22 seconds
Started Aug 21 01:28:53 PM UTC 24
Finished Aug 21 01:28:55 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2788846057
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2788
846057 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_app.3432497002
Short name T420
Test name
Test status
Simulation time 142596226453 ps
CPU time 513.33 seconds
Started Aug 21 01:27:47 PM UTC 24
Finished Aug 21 01:36:28 PM UTC 24
Peak memory 481588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34324970
02 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3432497002
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.1743787892
Short name T375
Test name
Test status
Simulation time 2775632551 ps
CPU time 181.92 seconds
Started Aug 21 01:27:38 PM UTC 24
Finished Aug 21 01:30:44 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17437878
92 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_w
rite.1743787892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.4001999890
Short name T421
Test name
Test status
Simulation time 18288829120 ps
CPU time 518.34 seconds
Started Aug 21 01:27:48 PM UTC 24
Finished Aug 21 01:36:33 PM UTC 24
Peak memory 518484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40019998
90 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_ent
ropy_refresh.4001999890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_error.4159584949
Short name T36
Test name
Test status
Simulation time 26938879330 ps
CPU time 492.85 seconds
Started Aug 21 01:27:51 PM UTC 24
Finished Aug 21 01:36:11 PM UTC 24
Peak memory 596356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159584949 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.4159584949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2564184599
Short name T366
Test name
Test status
Simulation time 1333208865 ps
CPU time 17.62 seconds
Started Aug 21 01:28:30 PM UTC 24
Finished Aug 21 01:28:49 PM UTC 24
Peak memory 229624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564184599 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2564184599 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.1771514002
Short name T59
Test name
Test status
Simulation time 44793787 ps
CPU time 2.03 seconds
Started Aug 21 01:28:49 PM UTC 24
Finished Aug 21 01:28:52 PM UTC 24
Peak memory 231900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771514002 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1771514002 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3067451535
Short name T690
Test name
Test status
Simulation time 266275028676 ps
CPU time 3024.98 seconds
Started Aug 21 01:27:11 PM UTC 24
Finished Aug 21 02:18:10 PM UTC 24
Peak memory 3307800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30674
51535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.k
mac_long_msg_and_output.3067451535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.2025620127
Short name T402
Test name
Test status
Simulation time 76238061316 ps
CPU time 389.27 seconds
Started Aug 21 01:27:20 PM UTC 24
Finished Aug 21 01:33:55 PM UTC 24
Peak memory 602364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=202562
0127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload
.2025620127 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.1632798346
Short name T364
Test name
Test status
Simulation time 11584509098 ps
CPU time 78.11 seconds
Started Aug 21 01:27:09 PM UTC 24
Finished Aug 21 01:28:29 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1632798346 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1632798346 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.3141937523
Short name T699
Test name
Test status
Simulation time 401073793486 ps
CPU time 3405.48 seconds
Started Aug 21 01:28:50 PM UTC 24
Finished Aug 21 02:26:13 PM UTC 24
Peak memory 1252040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3141937523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_stress_all.3141937523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.117096295
Short name T377
Test name
Test status
Simulation time 16418944 ps
CPU time 1.25 seconds
Started Aug 21 01:30:45 PM UTC 24
Finished Aug 21 01:30:48 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=117096295 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.11709
6295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_app.2864068866
Short name T390
Test name
Test status
Simulation time 12400195530 ps
CPU time 161.2 seconds
Started Aug 21 01:29:39 PM UTC 24
Finished Aug 21 01:32:23 PM UTC 24
Peak memory 356668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28640688
66 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2864068866
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.2613957534
Short name T454
Test name
Test status
Simulation time 214845150751 ps
CPU time 759.61 seconds
Started Aug 21 01:29:22 PM UTC 24
Finished Aug 21 01:42:12 PM UTC 24
Peak memory 252168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26139575
34 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_w
rite.2613957534 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1021034373
Short name T422
Test name
Test status
Simulation time 24063718042 ps
CPU time 362.8 seconds
Started Aug 21 01:30:26 PM UTC 24
Finished Aug 21 01:36:34 PM UTC 24
Peak memory 444656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10210343
73 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_ent
ropy_refresh.1021034373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_error.32598191
Short name T419
Test name
Test status
Simulation time 3365681385 ps
CPU time 345.28 seconds
Started Aug 21 01:30:26 PM UTC 24
Finished Aug 21 01:36:17 PM UTC 24
Peak memory 328124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32598191 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.32598191 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.1702539370
Short name T374
Test name
Test status
Simulation time 563854104 ps
CPU time 3.2 seconds
Started Aug 21 01:30:33 PM UTC 24
Finished Aug 21 01:30:38 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1702539370 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1702539370 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.1722341911
Short name T52
Test name
Test status
Simulation time 51588005 ps
CPU time 1.88 seconds
Started Aug 21 01:30:38 PM UTC 24
Finished Aug 21 01:30:41 PM UTC 24
Peak memory 233376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722341911 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1722341911 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.84899079
Short name T679
Test name
Test status
Simulation time 55573490568 ps
CPU time 2662.64 seconds
Started Aug 21 01:28:58 PM UTC 24
Finished Aug 21 02:13:50 PM UTC 24
Peak memory 1724728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84899
079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kma
c_long_msg_and_output.84899079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.2512727498
Short name T412
Test name
Test status
Simulation time 10457775363 ps
CPU time 370.28 seconds
Started Aug 21 01:29:09 PM UTC 24
Finished Aug 21 01:35:25 PM UTC 24
Peak memory 510192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251272
7498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload
.2512727498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.2097832911
Short name T371
Test name
Test status
Simulation time 3594010630 ps
CPU time 87.11 seconds
Started Aug 21 01:28:56 PM UTC 24
Finished Aug 21 01:30:25 PM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097832911 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2097832911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.3694934279
Short name T507
Test name
Test status
Simulation time 148026234672 ps
CPU time 1051.23 seconds
Started Aug 21 01:30:42 PM UTC 24
Finished Aug 21 01:48:26 PM UTC 24
Peak memory 1139024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3694934279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 22.kmac_stress_all.3694934279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.3075280063
Short name T386
Test name
Test status
Simulation time 14151832 ps
CPU time 1.26 seconds
Started Aug 21 01:32:08 PM UTC 24
Finished Aug 21 01:32:11 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3075280063
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3075
280063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_app.3518017097
Short name T424
Test name
Test status
Simulation time 32085216653 ps
CPU time 319.98 seconds
Started Aug 21 01:31:17 PM UTC 24
Finished Aug 21 01:36:43 PM UTC 24
Peak memory 407932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35180170
97 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3518017097
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.1962386746
Short name T398
Test name
Test status
Simulation time 2789673166 ps
CPU time 159.64 seconds
Started Aug 21 01:30:52 PM UTC 24
Finished Aug 21 01:33:35 PM UTC 24
Peak memory 246076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19623867
46 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_w
rite.1962386746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.4073655953
Short name T409
Test name
Test status
Simulation time 24497262083 ps
CPU time 187.87 seconds
Started Aug 21 01:31:19 PM UTC 24
Finished Aug 21 01:34:31 PM UTC 24
Peak memory 356772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40736559
53 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_ent
ropy_refresh.4073655953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_error.2646915293
Short name T404
Test name
Test status
Simulation time 7045191831 ps
CPU time 140.68 seconds
Started Aug 21 01:31:50 PM UTC 24
Finished Aug 21 01:34:14 PM UTC 24
Peak memory 284996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2646915293 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.2646915293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.3934133921
Short name T387
Test name
Test status
Simulation time 583658596 ps
CPU time 8.73 seconds
Started Aug 21 01:32:02 PM UTC 24
Finished Aug 21 01:32:12 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3934133921 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.3934133921 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.234310732
Short name T94
Test name
Test status
Simulation time 91528729 ps
CPU time 1.8 seconds
Started Aug 21 01:32:03 PM UTC 24
Finished Aug 21 01:32:07 PM UTC 24
Peak memory 233360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=234310732 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.234310732 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.103993696
Short name T401
Test name
Test status
Simulation time 4219215963 ps
CPU time 177.19 seconds
Started Aug 21 01:30:49 PM UTC 24
Finished Aug 21 01:33:49 PM UTC 24
Peak memory 381244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10399
3696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.km
ac_long_msg_and_output.103993696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.3831855111
Short name T399
Test name
Test status
Simulation time 2229843020 ps
CPU time 172.66 seconds
Started Aug 21 01:30:50 PM UTC 24
Finished Aug 21 01:33:45 PM UTC 24
Peak memory 293180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=383185
5111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload
.3831855111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.255362553
Short name T382
Test name
Test status
Simulation time 4710143373 ps
CPU time 59.22 seconds
Started Aug 21 01:30:49 PM UTC 24
Finished Aug 21 01:31:50 PM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255362553 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.255362553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.2839754357
Short name T405
Test name
Test status
Simulation time 6762553018 ps
CPU time 134.66 seconds
Started Aug 21 01:32:06 PM UTC 24
Finished Aug 21 01:34:25 PM UTC 24
Peak memory 283328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2839754357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 23.kmac_stress_all.2839754357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2731645940
Short name T397
Test name
Test status
Simulation time 20852321 ps
CPU time 1.11 seconds
Started Aug 21 01:33:21 PM UTC 24
Finished Aug 21 01:33:23 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2731645940
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2731
645940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_app.147722284
Short name T431
Test name
Test status
Simulation time 21029203138 ps
CPU time 339.97 seconds
Started Aug 21 01:32:24 PM UTC 24
Finished Aug 21 01:38:09 PM UTC 24
Peak memory 348468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14772228
4 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.147722284 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.1562089244
Short name T452
Test name
Test status
Simulation time 5056436437 ps
CPU time 522.81 seconds
Started Aug 21 01:32:21 PM UTC 24
Finished Aug 21 01:41:11 PM UTC 24
Peak memory 243972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15620892
44 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_w
rite.1562089244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1167162411
Short name T415
Test name
Test status
Simulation time 13882335119 ps
CPU time 187.33 seconds
Started Aug 21 01:32:59 PM UTC 24
Finished Aug 21 01:36:10 PM UTC 24
Peak memory 348420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11671624
11 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_ent
ropy_refresh.1167162411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_error.626980030
Short name T426
Test name
Test status
Simulation time 8903354761 ps
CPU time 225.29 seconds
Started Aug 21 01:32:59 PM UTC 24
Finished Aug 21 01:36:48 PM UTC 24
Peak memory 442628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=626980030 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.626980030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.995260654
Short name T394
Test name
Test status
Simulation time 57048601 ps
CPU time 2.09 seconds
Started Aug 21 01:33:03 PM UTC 24
Finished Aug 21 01:33:06 PM UTC 24
Peak memory 227432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=995260654 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.995260654 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.1198670149
Short name T395
Test name
Test status
Simulation time 153587938 ps
CPU time 2.23 seconds
Started Aug 21 01:33:07 PM UTC 24
Finished Aug 21 01:33:10 PM UTC 24
Peak memory 233968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1198670149 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1198670149 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.2234098774
Short name T717
Test name
Test status
Simulation time 271526201605 ps
CPU time 5188.73 seconds
Started Aug 21 01:32:13 PM UTC 24
Finished Aug 21 02:59:38 PM UTC 24
Peak memory 4989268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22340
98774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.k
mac_long_msg_and_output.2234098774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.3621568319
Short name T414
Test name
Test status
Simulation time 2590529201 ps
CPU time 222.99 seconds
Started Aug 21 01:32:19 PM UTC 24
Finished Aug 21 01:36:06 PM UTC 24
Peak memory 295156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362156
8319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload
.3621568319 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.3939282743
Short name T389
Test name
Test status
Simulation time 401679161 ps
CPU time 6.55 seconds
Started Aug 21 01:32:12 PM UTC 24
Finished Aug 21 01:32:20 PM UTC 24
Peak memory 235748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939282743 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3939282743 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3815363157
Short name T703
Test name
Test status
Simulation time 162794384565 ps
CPU time 3449.01 seconds
Started Aug 21 01:33:11 PM UTC 24
Finished Aug 21 02:31:19 PM UTC 24
Peak memory 1469068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3815363157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.kmac_stress_all.3815363157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.3824544639
Short name T410
Test name
Test status
Simulation time 44572677 ps
CPU time 1.31 seconds
Started Aug 21 01:34:29 PM UTC 24
Finished Aug 21 01:34:31 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3824544639
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3824
544639 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_app.2615518129
Short name T444
Test name
Test status
Simulation time 31648845251 ps
CPU time 358.27 seconds
Started Aug 21 01:33:50 PM UTC 24
Finished Aug 21 01:39:54 PM UTC 24
Peak memory 452916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26155181
29 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2615518129
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.2680757580
Short name T447
Test name
Test status
Simulation time 14202127232 ps
CPU time 372.69 seconds
Started Aug 21 01:33:48 PM UTC 24
Finished Aug 21 01:40:06 PM UTC 24
Peak memory 252220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26807575
80 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_w
rite.2680757580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1167286748
Short name T91
Test name
Test status
Simulation time 14006984035 ps
CPU time 346.89 seconds
Started Aug 21 01:33:55 PM UTC 24
Finished Aug 21 01:39:48 PM UTC 24
Peak memory 473424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11672867
48 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_ent
ropy_refresh.1167286748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_error.576209530
Short name T407
Test name
Test status
Simulation time 183616101 ps
CPU time 15.36 seconds
Started Aug 21 01:34:10 PM UTC 24
Finished Aug 21 01:34:28 PM UTC 24
Peak memory 245568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=576209530 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.576209530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.2678919265
Short name T406
Test name
Test status
Simulation time 606985333 ps
CPU time 8.33 seconds
Started Aug 21 01:34:16 PM UTC 24
Finished Aug 21 01:34:25 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678919265 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2678919265 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.678573665
Short name T408
Test name
Test status
Simulation time 43448814 ps
CPU time 2.22 seconds
Started Aug 21 01:34:26 PM UTC 24
Finished Aug 21 01:34:29 PM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678573665 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.678573665 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.313592082
Short name T558
Test name
Test status
Simulation time 83783657265 ps
CPU time 1267.78 seconds
Started Aug 21 01:33:35 PM UTC 24
Finished Aug 21 01:54:59 PM UTC 24
Peak memory 1636668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31359
2082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.km
ac_long_msg_and_output.313592082 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.1784844156
Short name T429
Test name
Test status
Simulation time 5913512353 ps
CPU time 216.19 seconds
Started Aug 21 01:33:46 PM UTC 24
Finished Aug 21 01:37:27 PM UTC 24
Peak memory 377052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178484
4156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload
.1784844156 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.113553312
Short name T400
Test name
Test status
Simulation time 543974251 ps
CPU time 22.3 seconds
Started Aug 21 01:33:24 PM UTC 24
Finished Aug 21 01:33:48 PM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113553312 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.113553312 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.1591513884
Short name T607
Test name
Test status
Simulation time 74380764973 ps
CPU time 1642.82 seconds
Started Aug 21 01:34:26 PM UTC 24
Finished Aug 21 02:02:08 PM UTC 24
Peak memory 754308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1591513884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 25.kmac_stress_all.1591513884 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.722573621
Short name T418
Test name
Test status
Simulation time 17917232 ps
CPU time 1.28 seconds
Started Aug 21 01:36:11 PM UTC 24
Finished Aug 21 01:36:14 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=722573621 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.72257
3621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_app.3209194159
Short name T430
Test name
Test status
Simulation time 16272302640 ps
CPU time 124.09 seconds
Started Aug 21 01:35:25 PM UTC 24
Finished Aug 21 01:37:32 PM UTC 24
Peak memory 270640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32091941
59 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3209194159
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.794942202
Short name T570
Test name
Test status
Simulation time 38896817616 ps
CPU time 1313.07 seconds
Started Aug 21 01:35:06 PM UTC 24
Finished Aug 21 01:57:15 PM UTC 24
Peak memory 268536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79494220
2 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_wr
ite.794942202 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1174278174
Short name T472
Test name
Test status
Simulation time 13325122545 ps
CPU time 484.02 seconds
Started Aug 21 01:35:35 PM UTC 24
Finished Aug 21 01:43:46 PM UTC 24
Peak memory 465256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11742781
74 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_ent
ropy_refresh.1174278174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_error.1777680466
Short name T438
Test name
Test status
Simulation time 4729050156 ps
CPU time 198.66 seconds
Started Aug 21 01:35:44 PM UTC 24
Finished Aug 21 01:39:06 PM UTC 24
Peak memory 313576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1777680466 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1777680466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.2890208644
Short name T417
Test name
Test status
Simulation time 879506059 ps
CPU time 12.79 seconds
Started Aug 21 01:35:56 PM UTC 24
Finished Aug 21 01:36:11 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2890208644 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2890208644 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.27764779
Short name T416
Test name
Test status
Simulation time 243867458 ps
CPU time 1.96 seconds
Started Aug 21 01:36:07 PM UTC 24
Finished Aug 21 01:36:10 PM UTC 24
Peak memory 231316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27764779 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.27764779 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.623064293
Short name T598
Test name
Test status
Simulation time 49885518201 ps
CPU time 1604.42 seconds
Started Aug 21 01:34:31 PM UTC 24
Finished Aug 21 02:01:33 PM UTC 24
Peak memory 1124632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62306
4293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.km
ac_long_msg_and_output.623064293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.286862892
Short name T451
Test name
Test status
Simulation time 4748676135 ps
CPU time 367.2 seconds
Started Aug 21 01:34:32 PM UTC 24
Finished Aug 21 01:40:44 PM UTC 24
Peak memory 371008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=286862
892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.
286862892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.279248180
Short name T411
Test name
Test status
Simulation time 1355618361 ps
CPU time 33.44 seconds
Started Aug 21 01:34:30 PM UTC 24
Finished Aug 21 01:35:05 PM UTC 24
Peak memory 235920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279248180 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.279248180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2471268059
Short name T544
Test name
Test status
Simulation time 387360607836 ps
CPU time 989.66 seconds
Started Aug 21 01:36:11 PM UTC 24
Finished Aug 21 01:52:54 PM UTC 24
Peak memory 725248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2471268059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 26.kmac_stress_all.2471268059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.335172035
Short name T427
Test name
Test status
Simulation time 46724083 ps
CPU time 1.22 seconds
Started Aug 21 01:36:47 PM UTC 24
Finished Aug 21 01:36:50 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335172035 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.33517
2035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_app.3758433400
Short name T432
Test name
Test status
Simulation time 4263302017 ps
CPU time 110.24 seconds
Started Aug 21 01:36:29 PM UTC 24
Finished Aug 21 01:38:21 PM UTC 24
Peak memory 315776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37584334
00 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3758433400
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.1572741736
Short name T455
Test name
Test status
Simulation time 11404830286 ps
CPU time 354.91 seconds
Started Aug 21 01:36:18 PM UTC 24
Finished Aug 21 01:42:18 PM UTC 24
Peak memory 241968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15727417
36 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_w
rite.1572741736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3727066107
Short name T459
Test name
Test status
Simulation time 46362041741 ps
CPU time 365.99 seconds
Started Aug 21 01:36:34 PM UTC 24
Finished Aug 21 01:42:45 PM UTC 24
Peak memory 481592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37270661
07 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_ent
ropy_refresh.3727066107 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_error.1299389213
Short name T464
Test name
Test status
Simulation time 96290311833 ps
CPU time 395.9 seconds
Started Aug 21 01:36:35 PM UTC 24
Finished Aug 21 01:43:17 PM UTC 24
Peak memory 473344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1299389213 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1299389213 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.1273546581
Short name T425
Test name
Test status
Simulation time 541553254 ps
CPU time 5.35 seconds
Started Aug 21 01:36:37 PM UTC 24
Finished Aug 21 01:36:44 PM UTC 24
Peak memory 227644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1273546581 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1273546581 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2266713305
Short name T92
Test name
Test status
Simulation time 197244908 ps
CPU time 2.33 seconds
Started Aug 21 01:36:43 PM UTC 24
Finished Aug 21 01:36:47 PM UTC 24
Peak memory 233824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2266713305 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2266713305 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3647596663
Short name T492
Test name
Test status
Simulation time 37954664280 ps
CPU time 579.52 seconds
Started Aug 21 01:36:13 PM UTC 24
Finished Aug 21 01:45:59 PM UTC 24
Peak memory 915800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36475
96663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.k
mac_long_msg_and_output.3647596663 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.2720976224
Short name T467
Test name
Test status
Simulation time 16759079746 ps
CPU time 430.5 seconds
Started Aug 21 01:36:15 PM UTC 24
Finished Aug 21 01:43:31 PM UTC 24
Peak memory 592172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=272097
6224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload
.2720976224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.4281997886
Short name T423
Test name
Test status
Simulation time 2857382606 ps
CPU time 22.44 seconds
Started Aug 21 01:36:12 PM UTC 24
Finished Aug 21 01:36:36 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281997886 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4281997886 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.1044456853
Short name T652
Test name
Test status
Simulation time 42198335273 ps
CPU time 1835.47 seconds
Started Aug 21 01:36:45 PM UTC 24
Finished Aug 21 02:07:42 PM UTC 24
Peak memory 731780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1044456853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_stress_all.1044456853 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2123336758
Short name T437
Test name
Test status
Simulation time 21844207 ps
CPU time 1.28 seconds
Started Aug 21 01:38:59 PM UTC 24
Finished Aug 21 01:39:02 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2123336758
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2123
336758 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_app.1820034981
Short name T461
Test name
Test status
Simulation time 40260945150 ps
CPU time 316.37 seconds
Started Aug 21 01:37:33 PM UTC 24
Finished Aug 21 01:42:55 PM UTC 24
Peak memory 436552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18200349
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1820034981
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.1831499294
Short name T589
Test name
Test status
Simulation time 396043193030 ps
CPU time 1314.8 seconds
Started Aug 21 01:37:28 PM UTC 24
Finished Aug 21 01:59:38 PM UTC 24
Peak memory 270656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18314992
94 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_w
rite.1831499294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.3109178335
Short name T440
Test name
Test status
Simulation time 2544519465 ps
CPU time 63.94 seconds
Started Aug 21 01:38:10 PM UTC 24
Finished Aug 21 01:39:16 PM UTC 24
Peak memory 248056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31091783
35 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_ent
ropy_refresh.3109178335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_error.456173034
Short name T453
Test name
Test status
Simulation time 2553156504 ps
CPU time 166.11 seconds
Started Aug 21 01:38:22 PM UTC 24
Finished Aug 21 01:41:11 PM UTC 24
Peak memory 295204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456173034 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.456173034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.3809642522
Short name T434
Test name
Test status
Simulation time 581537924 ps
CPU time 4.44 seconds
Started Aug 21 01:38:28 PM UTC 24
Finished Aug 21 01:38:34 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3809642522 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3809642522 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.251904929
Short name T435
Test name
Test status
Simulation time 241663671 ps
CPU time 2.03 seconds
Started Aug 21 01:38:34 PM UTC 24
Finished Aug 21 01:38:38 PM UTC 24
Peak memory 233852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251904929 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.251904929 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3681500192
Short name T490
Test name
Test status
Simulation time 14755631703 ps
CPU time 523.99 seconds
Started Aug 21 01:36:50 PM UTC 24
Finished Aug 21 01:45:41 PM UTC 24
Peak memory 942392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36815
00192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.k
mac_long_msg_and_output.3681500192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.98526882
Short name T477
Test name
Test status
Simulation time 24518564599 ps
CPU time 422.66 seconds
Started Aug 21 01:37:27 PM UTC 24
Finished Aug 21 01:44:35 PM UTC 24
Peak memory 549188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=985268
82 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.9
8526882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.1986468172
Short name T428
Test name
Test status
Simulation time 3720612337 ps
CPU time 34.95 seconds
Started Aug 21 01:36:49 PM UTC 24
Finished Aug 21 01:37:26 PM UTC 24
Peak memory 235884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1986468172 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1986468172 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.108645491
Short name T526
Test name
Test status
Simulation time 100510037132 ps
CPU time 720.66 seconds
Started Aug 21 01:38:38 PM UTC 24
Finished Aug 21 01:50:48 PM UTC 24
Peak memory 940280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=108645491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.kmac_stress_all.108645491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.3966415186
Short name T448
Test name
Test status
Simulation time 26562677 ps
CPU time 1.25 seconds
Started Aug 21 01:40:05 PM UTC 24
Finished Aug 21 01:40:08 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3966415186
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3966
415186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_app.2410730174
Short name T502
Test name
Test status
Simulation time 26896111410 ps
CPU time 448.35 seconds
Started Aug 21 01:39:26 PM UTC 24
Finished Aug 21 01:47:01 PM UTC 24
Peak memory 358736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24107301
74 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2410730174
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.2994257638
Short name T605
Test name
Test status
Simulation time 51828564537 ps
CPU time 1349.33 seconds
Started Aug 21 01:39:17 PM UTC 24
Finished Aug 21 02:02:03 PM UTC 24
Peak memory 264516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29942576
38 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_w
rite.2994257638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.250174446
Short name T462
Test name
Test status
Simulation time 24346928793 ps
CPU time 184.12 seconds
Started Aug 21 01:39:48 PM UTC 24
Finished Aug 21 01:42:56 PM UTC 24
Peak memory 291068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25017444
6 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entr
opy_refresh.250174446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2655951466
Short name T476
Test name
Test status
Simulation time 3219001164 ps
CPU time 262.54 seconds
Started Aug 21 01:39:51 PM UTC 24
Finished Aug 21 01:44:18 PM UTC 24
Peak memory 327944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2655951466 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2655951466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.1476339365
Short name T446
Test name
Test status
Simulation time 1597402421 ps
CPU time 8.71 seconds
Started Aug 21 01:39:54 PM UTC 24
Finished Aug 21 01:40:05 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1476339365 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1476339365 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.213631774
Short name T445
Test name
Test status
Simulation time 64160872 ps
CPU time 1.97 seconds
Started Aug 21 01:39:55 PM UTC 24
Finished Aug 21 01:39:59 PM UTC 24
Peak memory 231356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=213631774 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.213631774 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.1801146824
Short name T557
Test name
Test status
Simulation time 16744800329 ps
CPU time 934.94 seconds
Started Aug 21 01:39:08 PM UTC 24
Finished Aug 21 01:54:54 PM UTC 24
Peak memory 737520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18011
46824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.k
mac_long_msg_and_output.1801146824 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.842404433
Short name T478
Test name
Test status
Simulation time 10822027294 ps
CPU time 322.85 seconds
Started Aug 21 01:39:09 PM UTC 24
Finished Aug 21 01:44:36 PM UTC 24
Peak memory 364836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=842404
433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.
842404433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.253975727
Short name T450
Test name
Test status
Simulation time 14649049689 ps
CPU time 97.89 seconds
Started Aug 21 01:39:03 PM UTC 24
Finished Aug 21 01:40:43 PM UTC 24
Peak memory 235824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=253975727 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.253975727 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.3635794803
Short name T600
Test name
Test status
Simulation time 38113977191 ps
CPU time 1290.69 seconds
Started Aug 21 01:39:59 PM UTC 24
Finished Aug 21 02:01:47 PM UTC 24
Peak memory 1231112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3635794803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_stress_all.3635794803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.2871436435
Short name T192
Test name
Test status
Simulation time 29690849 ps
CPU time 1.23 seconds
Started Aug 21 12:52:55 PM UTC 24
Finished Aug 21 12:52:57 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871436435
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.28714
36435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_app.2239177510
Short name T197
Test name
Test status
Simulation time 30427786368 ps
CPU time 391.62 seconds
Started Aug 21 12:51:07 PM UTC 24
Finished Aug 21 12:57:44 PM UTC 24
Peak memory 479536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22391775
10 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2239177510 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.2940831932
Short name T189
Test name
Test status
Simulation time 3993465395 ps
CPU time 82.76 seconds
Started Aug 21 12:51:08 PM UTC 24
Finished Aug 21 12:52:33 PM UTC 24
Peak memory 250116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29408319
32 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kma
c_app_with_partial_data.2940831932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3746422170
Short name T140
Test name
Test status
Simulation time 90837858969 ps
CPU time 986.57 seconds
Started Aug 21 12:49:37 PM UTC 24
Finished Aug 21 01:06:15 PM UTC 24
Peak memory 264508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37464221
70 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_wr
ite.3746422170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.4273961613
Short name T190
Test name
Test status
Simulation time 132415475 ps
CPU time 3.62 seconds
Started Aug 21 12:52:33 PM UTC 24
Finished Aug 21 12:52:38 PM UTC 24
Peak memory 234820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4273961613 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.427
3961613 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.408564852
Short name T109
Test name
Test status
Simulation time 308799592 ps
CPU time 2.12 seconds
Started Aug 21 12:52:34 PM UTC 24
Finished Aug 21 12:52:38 PM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=408564852 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.40
8564852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3393540531
Short name T191
Test name
Test status
Simulation time 2461130174 ps
CPU time 15.48 seconds
Started Aug 21 12:52:36 PM UTC 24
Finished Aug 21 12:52:53 PM UTC 24
Peak memory 235880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393540531 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.339354053
1 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.197176924
Short name T88
Test name
Test status
Simulation time 2302871347 ps
CPU time 66.43 seconds
Started Aug 21 12:51:15 PM UTC 24
Finished Aug 21 12:52:24 PM UTC 24
Peak memory 264508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19717692
4 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entro
py_refresh.197176924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_error.3007221143
Short name T76
Test name
Test status
Simulation time 1417233042 ps
CPU time 54.72 seconds
Started Aug 21 12:52:26 PM UTC 24
Finished Aug 21 12:53:22 PM UTC 24
Peak memory 268560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007221143 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3007221143 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.2462432120
Short name T110
Test name
Test status
Simulation time 2915005692 ps
CPU time 12.04 seconds
Started Aug 21 12:52:32 PM UTC 24
Finished Aug 21 12:52:46 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2462432120 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.2462432120 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.2410304731
Short name T37
Test name
Test status
Simulation time 243514483 ps
CPU time 2 seconds
Started Aug 21 12:52:39 PM UTC 24
Finished Aug 21 12:52:43 PM UTC 24
Peak memory 231352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410304731 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2410304731 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1003947829
Short name T396
Test name
Test status
Simulation time 24721970237 ps
CPU time 2602.3 seconds
Started Aug 21 12:49:29 PM UTC 24
Finished Aug 21 01:33:20 PM UTC 24
Peak memory 1710336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10039
47829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.km
ac_long_msg_and_output.1003947829 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.3023500633
Short name T66
Test name
Test status
Simulation time 18288795875 ps
CPU time 454.2 seconds
Started Aug 21 12:52:26 PM UTC 24
Finished Aug 21 01:00:06 PM UTC 24
Peak memory 570052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023500633 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3023500633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.909599667
Short name T112
Test name
Test status
Simulation time 2397568505 ps
CPU time 44.41 seconds
Started Aug 21 12:52:47 PM UTC 24
Finished Aug 21 12:53:33 PM UTC 24
Peak memory 278024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=909599667 -a
ssert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.909599667 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.3864012722
Short name T28
Test name
Test status
Simulation time 13622442626 ps
CPU time 581.22 seconds
Started Aug 21 12:49:32 PM UTC 24
Finished Aug 21 12:59:21 PM UTC 24
Peak memory 590076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386401
2722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.
3864012722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.4291820542
Short name T186
Test name
Test status
Simulation time 174406652 ps
CPU time 6.28 seconds
Started Aug 21 12:49:28 PM UTC 24
Finished Aug 21 12:49:36 PM UTC 24
Peak memory 235752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291820542 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4291820542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.1015132665
Short name T378
Test name
Test status
Simulation time 85659768356 ps
CPU time 2263.16 seconds
Started Aug 21 12:52:39 PM UTC 24
Finished Aug 21 01:30:49 PM UTC 24
Peak memory 840396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1015132665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_stress_all.1015132665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.481579185
Short name T187
Test name
Test status
Simulation time 59822148 ps
CPU time 4.21 seconds
Started Aug 21 12:50:53 PM UTC 24
Finished Aug 21 12:50:58 PM UTC 24
Peak memory 229760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481579185 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.481579185 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3170055987
Short name T188
Test name
Test status
Simulation time 437058687 ps
CPU time 4.8 seconds
Started Aug 21 12:51:00 PM UTC 24
Finished Aug 21 12:51:06 PM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170055987 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3170055
987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.4087848110
Short name T327
Test name
Test status
Simulation time 72234130080 ps
CPU time 2043.37 seconds
Started Aug 21 12:49:46 PM UTC 24
Finished Aug 21 01:24:13 PM UTC 24
Peak memory 1169548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=4087848110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.kmac_test_vectors_sha3_224.4087848110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.2656899023
Short name T384
Test name
Test status
Simulation time 117112533593 ps
CPU time 2492.55 seconds
Started Aug 21 12:50:01 PM UTC 24
Finished Aug 21 01:32:03 PM UTC 24
Peak memory 2904220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=2656899023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2656899023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3381240187
Short name T301
Test name
Test status
Simulation time 32164576876 ps
CPU time 1788.75 seconds
Started Aug 21 12:50:12 PM UTC 24
Finished Aug 21 01:20:23 PM UTC 24
Peak memory 931988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=3381240187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3381240187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.2162099011
Short name T262
Test name
Test status
Simulation time 63584618054 ps
CPU time 1408.03 seconds
Started Aug 21 12:50:20 PM UTC 24
Finished Aug 21 01:14:04 PM UTC 24
Peak memory 1708184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=2162099011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2162099011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3484128987
Short name T575
Test name
Test status
Simulation time 838734056567 ps
CPU time 3968.88 seconds
Started Aug 21 12:50:34 PM UTC 24
Finished Aug 21 01:57:29 PM UTC 24
Peak memory 3719340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3484128987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3484128987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1142703938
Short name T181
Test name
Test status
Simulation time 83120620175 ps
CPU time 448.42 seconds
Started Aug 21 12:50:39 PM UTC 24
Finished Aug 21 12:58:14 PM UTC 24
Peak memory 366748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1142703938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1142703938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.1312087875
Short name T458
Test name
Test status
Simulation time 12320225 ps
CPU time 1.22 seconds
Started Aug 21 01:42:37 PM UTC 24
Finished Aug 21 01:42:40 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1312087875
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.1312
087875 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_app.915054389
Short name T485
Test name
Test status
Simulation time 14817917086 ps
CPU time 255.35 seconds
Started Aug 21 01:40:45 PM UTC 24
Finished Aug 21 01:45:05 PM UTC 24
Peak memory 317712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91505438
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.915054389 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.283270934
Short name T463
Test name
Test status
Simulation time 17605008352 ps
CPU time 149.73 seconds
Started Aug 21 01:40:44 PM UTC 24
Finished Aug 21 01:43:17 PM UTC 24
Peak memory 235564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28327093
4 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_wr
ite.283270934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2051963799
Short name T473
Test name
Test status
Simulation time 37546554332 ps
CPU time 153.62 seconds
Started Aug 21 01:41:11 PM UTC 24
Finished Aug 21 01:43:48 PM UTC 24
Peak memory 340180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20519637
99 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_ent
ropy_refresh.2051963799 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_error.1014330369
Short name T495
Test name
Test status
Simulation time 33226447426 ps
CPU time 302.5 seconds
Started Aug 21 01:41:12 PM UTC 24
Finished Aug 21 01:46:19 PM UTC 24
Peak memory 450872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014330369 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1014330369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.2173416698
Short name T457
Test name
Test status
Simulation time 1900224541 ps
CPU time 21.18 seconds
Started Aug 21 01:42:13 PM UTC 24
Finished Aug 21 01:42:36 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2173416698 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2173416698 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.719065353
Short name T460
Test name
Test status
Simulation time 1727354068 ps
CPU time 25.14 seconds
Started Aug 21 01:42:19 PM UTC 24
Finished Aug 21 01:42:47 PM UTC 24
Peak memory 245880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719065353 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.719065353 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2266625671
Short name T697
Test name
Test status
Simulation time 286898590433 ps
CPU time 2645.2 seconds
Started Aug 21 01:40:09 PM UTC 24
Finished Aug 21 02:24:45 PM UTC 24
Peak memory 2732408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22666
25671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.k
mac_long_msg_and_output.2266625671 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.2942935823
Short name T482
Test name
Test status
Simulation time 26470171373 ps
CPU time 252.92 seconds
Started Aug 21 01:40:38 PM UTC 24
Finished Aug 21 01:44:55 PM UTC 24
Peak memory 397648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=294293
5823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload
.2942935823 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.2486538648
Short name T449
Test name
Test status
Simulation time 1257093584 ps
CPU time 27.5 seconds
Started Aug 21 01:40:08 PM UTC 24
Finished Aug 21 01:40:37 PM UTC 24
Peak memory 233920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486538648 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2486538648 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3797262051
Short name T486
Test name
Test status
Simulation time 7033816657 ps
CPU time 150.3 seconds
Started Aug 21 01:42:35 PM UTC 24
Finished Aug 21 01:45:09 PM UTC 24
Peak memory 252220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3797262051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 30.kmac_stress_all.3797262051 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.2927122178
Short name T469
Test name
Test status
Simulation time 17904664 ps
CPU time 1.3 seconds
Started Aug 21 01:43:33 PM UTC 24
Finished Aug 21 01:43:36 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927122178
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2927
122178 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_app.2864942731
Short name T470
Test name
Test status
Simulation time 1434946585 ps
CPU time 40.38 seconds
Started Aug 21 01:42:58 PM UTC 24
Finished Aug 21 01:43:40 PM UTC 24
Peak memory 239872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28649427
31 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2864942731
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.4054451145
Short name T512
Test name
Test status
Simulation time 8366652553 ps
CPU time 336.11 seconds
Started Aug 21 01:42:55 PM UTC 24
Finished Aug 21 01:48:36 PM UTC 24
Peak memory 244032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40544511
45 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_w
rite.4054451145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.388995829
Short name T499
Test name
Test status
Simulation time 38667763543 ps
CPU time 204.1 seconds
Started Aug 21 01:43:18 PM UTC 24
Finished Aug 21 01:46:45 PM UTC 24
Peak memory 362696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38899582
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entr
opy_refresh.388995829 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_error.1419822303
Short name T516
Test name
Test status
Simulation time 9452754754 ps
CPU time 366.17 seconds
Started Aug 21 01:43:18 PM UTC 24
Finished Aug 21 01:49:29 PM UTC 24
Peak memory 376912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1419822303 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1419822303 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.2871415284
Short name T466
Test name
Test status
Simulation time 1052769047 ps
CPU time 8.32 seconds
Started Aug 21 01:43:19 PM UTC 24
Finished Aug 21 01:43:29 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871415284 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2871415284 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.587041260
Short name T468
Test name
Test status
Simulation time 116036170 ps
CPU time 2.03 seconds
Started Aug 21 01:43:29 PM UTC 24
Finished Aug 21 01:43:32 PM UTC 24
Peak memory 231864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=587041260 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.587041260 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.5393793
Short name T566
Test name
Test status
Simulation time 25033080066 ps
CPU time 817.03 seconds
Started Aug 21 01:42:46 PM UTC 24
Finished Aug 21 01:56:33 PM UTC 24
Peak memory 1177856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53937
93 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac
_long_msg_and_output.5393793 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.2711459038
Short name T506
Test name
Test status
Simulation time 49275322439 ps
CPU time 313.62 seconds
Started Aug 21 01:42:47 PM UTC 24
Finished Aug 21 01:48:06 PM UTC 24
Peak memory 487868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271145
9038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload
.2711459038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.2695273928
Short name T465
Test name
Test status
Simulation time 10375665095 ps
CPU time 35.48 seconds
Started Aug 21 01:42:40 PM UTC 24
Finished Aug 21 01:43:17 PM UTC 24
Peak memory 235844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695273928 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2695273928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.2482982497
Short name T702
Test name
Test status
Simulation time 238756524475 ps
CPU time 2743.32 seconds
Started Aug 21 01:43:32 PM UTC 24
Finished Aug 21 02:29:48 PM UTC 24
Peak memory 1546864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2482982497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 31.kmac_stress_all.2482982497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.559086207
Short name T481
Test name
Test status
Simulation time 24495157 ps
CPU time 1.28 seconds
Started Aug 21 01:44:41 PM UTC 24
Finished Aug 21 01:44:44 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=559086207 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.55908
6207 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_app.1558941056
Short name T505
Test name
Test status
Simulation time 3268575173 ps
CPU time 243.54 seconds
Started Aug 21 01:43:49 PM UTC 24
Finished Aug 21 01:47:56 PM UTC 24
Peak memory 299332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15589410
56 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1558941056
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.746829249
Short name T529
Test name
Test status
Simulation time 12184146969 ps
CPU time 431.84 seconds
Started Aug 21 01:43:47 PM UTC 24
Finished Aug 21 01:51:05 PM UTC 24
Peak memory 250180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74682924
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_wr
ite.746829249 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.3440209616
Short name T519
Test name
Test status
Simulation time 12988458683 ps
CPU time 331.11 seconds
Started Aug 21 01:44:05 PM UTC 24
Finished Aug 21 01:49:41 PM UTC 24
Peak memory 463232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34402096
16 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_ent
ropy_refresh.3440209616 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_error.974738425
Short name T493
Test name
Test status
Simulation time 9789670746 ps
CPU time 116.76 seconds
Started Aug 21 01:44:16 PM UTC 24
Finished Aug 21 01:46:15 PM UTC 24
Peak memory 311608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=974738425 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.974738425 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.451989027
Short name T480
Test name
Test status
Simulation time 15274966265 ps
CPU time 22.18 seconds
Started Aug 21 01:44:19 PM UTC 24
Finished Aug 21 01:44:43 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451989027 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.451989027 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.810536101
Short name T479
Test name
Test status
Simulation time 32162961 ps
CPU time 2.2 seconds
Started Aug 21 01:44:36 PM UTC 24
Finished Aug 21 01:44:40 PM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=810536101 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.810536101 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1635391218
Short name T712
Test name
Test status
Simulation time 195849701314 ps
CPU time 3743.29 seconds
Started Aug 21 01:43:40 PM UTC 24
Finished Aug 21 02:46:46 PM UTC 24
Peak memory 3795328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16353
91218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.k
mac_long_msg_and_output.1635391218 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.3302078906
Short name T483
Test name
Test status
Simulation time 789671478 ps
CPU time 73.22 seconds
Started Aug 21 01:43:43 PM UTC 24
Finished Aug 21 01:44:59 PM UTC 24
Peak memory 250048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330207
8906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload
.3302078906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.441085483
Short name T471
Test name
Test status
Simulation time 155251560 ps
CPU time 3.28 seconds
Started Aug 21 01:43:37 PM UTC 24
Finished Aug 21 01:43:42 PM UTC 24
Peak memory 234000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=441085483 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.441085483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.1563007085
Short name T627
Test name
Test status
Simulation time 117849547322 ps
CPU time 1188.18 seconds
Started Aug 21 01:44:37 PM UTC 24
Finished Aug 21 02:04:41 PM UTC 24
Peak memory 944768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1563007085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 32.kmac_stress_all.1563007085 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.1135808510
Short name T491
Test name
Test status
Simulation time 15648481 ps
CPU time 0.96 seconds
Started Aug 21 01:45:42 PM UTC 24
Finished Aug 21 01:45:44 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1135808510
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.1135
808510 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_app.3470945278
Short name T497
Test name
Test status
Simulation time 15702945559 ps
CPU time 89.92 seconds
Started Aug 21 01:45:01 PM UTC 24
Finished Aug 21 01:46:33 PM UTC 24
Peak memory 280892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34709452
78 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3470945278
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.4123400357
Short name T673
Test name
Test status
Simulation time 35552978711 ps
CPU time 1653.59 seconds
Started Aug 21 01:45:00 PM UTC 24
Finished Aug 21 02:12:54 PM UTC 24
Peak memory 274748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41234003
57 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_w
rite.4123400357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.1407776656
Short name T509
Test name
Test status
Simulation time 14189476224 ps
CPU time 204.15 seconds
Started Aug 21 01:45:06 PM UTC 24
Finished Aug 21 01:48:33 PM UTC 24
Peak memory 297216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14077766
56 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_ent
ropy_refresh.1407776656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_error.2020028950
Short name T538
Test name
Test status
Simulation time 51158070473 ps
CPU time 405.3 seconds
Started Aug 21 01:45:10 PM UTC 24
Finished Aug 21 01:52:01 PM UTC 24
Peak memory 485628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2020028950 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2020028950 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.1566374159
Short name T489
Test name
Test status
Simulation time 3339505873 ps
CPU time 13.34 seconds
Started Aug 21 01:45:22 PM UTC 24
Finished Aug 21 01:45:37 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1566374159 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1566374159 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3253999517
Short name T695
Test name
Test status
Simulation time 39166375904 ps
CPU time 2359.13 seconds
Started Aug 21 01:44:44 PM UTC 24
Finished Aug 21 02:24:32 PM UTC 24
Peak memory 1343740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32539
99517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.k
mac_long_msg_and_output.3253999517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.2404741771
Short name T503
Test name
Test status
Simulation time 34067034079 ps
CPU time 151.19 seconds
Started Aug 21 01:44:56 PM UTC 24
Finished Aug 21 01:47:29 PM UTC 24
Peak memory 356600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240474
1771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload
.2404741771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.878017505
Short name T484
Test name
Test status
Simulation time 1668677025 ps
CPU time 15.6 seconds
Started Aug 21 01:44:43 PM UTC 24
Finished Aug 21 01:45:00 PM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=878017505 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.878017505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.2053816864
Short name T638
Test name
Test status
Simulation time 86749742369 ps
CPU time 1192.96 seconds
Started Aug 21 01:45:37 PM UTC 24
Finished Aug 21 02:05:45 PM UTC 24
Peak memory 674448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2053816864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_stress_all.2053816864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3053776608
Short name T501
Test name
Test status
Simulation time 46784213 ps
CPU time 1.22 seconds
Started Aug 21 01:46:57 PM UTC 24
Finished Aug 21 01:47:00 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3053776608
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3053
776608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_app.2411918033
Short name T517
Test name
Test status
Simulation time 16088618698 ps
CPU time 189.6 seconds
Started Aug 21 01:46:17 PM UTC 24
Finished Aug 21 01:49:29 PM UTC 24
Peak memory 387424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24119180
33 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2411918033
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.2666734572
Short name T621
Test name
Test status
Simulation time 101605423293 ps
CPU time 1072.58 seconds
Started Aug 21 01:46:17 PM UTC 24
Finished Aug 21 02:04:22 PM UTC 24
Peak memory 264584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26667345
72 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_w
rite.2666734572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3111777921
Short name T508
Test name
Test status
Simulation time 35279800325 ps
CPU time 128.01 seconds
Started Aug 21 01:46:20 PM UTC 24
Finished Aug 21 01:48:31 PM UTC 24
Peak memory 284972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31117779
21 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_ent
ropy_refresh.3111777921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_error.2760433577
Short name T518
Test name
Test status
Simulation time 2542530536 ps
CPU time 187.51 seconds
Started Aug 21 01:46:22 PM UTC 24
Finished Aug 21 01:49:33 PM UTC 24
Peak memory 303492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2760433577 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2760433577 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.1101409657
Short name T498
Test name
Test status
Simulation time 1725032284 ps
CPU time 7.61 seconds
Started Aug 21 01:46:34 PM UTC 24
Finished Aug 21 01:46:43 PM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101409657 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1101409657 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.1361944044
Short name T500
Test name
Test status
Simulation time 847671621 ps
CPU time 10.44 seconds
Started Aug 21 01:46:44 PM UTC 24
Finished Aug 21 01:46:56 PM UTC 24
Peak memory 244268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1361944044 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1361944044 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1077714590
Short name T710
Test name
Test status
Simulation time 381930706187 ps
CPU time 3489.69 seconds
Started Aug 21 01:45:45 PM UTC 24
Finished Aug 21 02:44:34 PM UTC 24
Peak memory 3598620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10777
14590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.k
mac_long_msg_and_output.1077714590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.1196916827
Short name T537
Test name
Test status
Simulation time 41153345134 ps
CPU time 349.26 seconds
Started Aug 21 01:46:00 PM UTC 24
Finished Aug 21 01:51:55 PM UTC 24
Peak memory 471368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119691
6827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload
.1196916827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.3753997383
Short name T496
Test name
Test status
Simulation time 5552197303 ps
CPU time 37.41 seconds
Started Aug 21 01:45:42 PM UTC 24
Finished Aug 21 01:46:21 PM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753997383 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3753997383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.894185528
Short name T689
Test name
Test status
Simulation time 75308729093 ps
CPU time 1814.82 seconds
Started Aug 21 01:46:46 PM UTC 24
Finished Aug 21 02:17:22 PM UTC 24
Peak memory 727680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=894185528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.kmac_stress_all.894185528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.2005790879
Short name T513
Test name
Test status
Simulation time 17782728 ps
CPU time 1.25 seconds
Started Aug 21 01:48:36 PM UTC 24
Finished Aug 21 01:48:39 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2005790879
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2005
790879 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_app.3553855781
Short name T547
Test name
Test status
Simulation time 25765166455 ps
CPU time 325.44 seconds
Started Aug 21 01:47:43 PM UTC 24
Finished Aug 21 01:53:13 PM UTC 24
Peak memory 487724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35538557
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3553855781
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.1812809144
Short name T684
Test name
Test status
Simulation time 15935676939 ps
CPU time 1682.73 seconds
Started Aug 21 01:47:30 PM UTC 24
Finished Aug 21 02:15:53 PM UTC 24
Peak memory 256324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18128091
44 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_w
rite.1812809144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2030733390
Short name T536
Test name
Test status
Simulation time 4688308474 ps
CPU time 221.65 seconds
Started Aug 21 01:47:57 PM UTC 24
Finished Aug 21 01:51:43 PM UTC 24
Peak memory 291124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20307333
90 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_ent
ropy_refresh.2030733390 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_error.1373230487
Short name T531
Test name
Test status
Simulation time 7603907598 ps
CPU time 181.73 seconds
Started Aug 21 01:48:06 PM UTC 24
Finished Aug 21 01:51:12 PM UTC 24
Peak memory 284924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1373230487 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1373230487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.840301429
Short name T511
Test name
Test status
Simulation time 1860308558 ps
CPU time 7.88 seconds
Started Aug 21 01:48:26 PM UTC 24
Finished Aug 21 01:48:36 PM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840301429 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.840301429 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.2560894278
Short name T510
Test name
Test status
Simulation time 170924943 ps
CPU time 1.9 seconds
Started Aug 21 01:48:32 PM UTC 24
Finished Aug 21 01:48:35 PM UTC 24
Peak memory 231380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560894278 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2560894278 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2806834540
Short name T678
Test name
Test status
Simulation time 27512947919 ps
CPU time 1579.37 seconds
Started Aug 21 01:47:01 PM UTC 24
Finished Aug 21 02:13:41 PM UTC 24
Peak memory 989492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28068
34540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.k
mac_long_msg_and_output.2806834540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.2734601828
Short name T535
Test name
Test status
Simulation time 6686112065 ps
CPU time 262.13 seconds
Started Aug 21 01:47:02 PM UTC 24
Finished Aug 21 01:51:28 PM UTC 24
Peak memory 393468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=273460
1828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload
.2734601828 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.3177193457
Short name T504
Test name
Test status
Simulation time 1429107401 ps
CPU time 42 seconds
Started Aug 21 01:46:59 PM UTC 24
Finished Aug 21 01:47:42 PM UTC 24
Peak memory 231952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3177193457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3177193457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3353111716
Short name T553
Test name
Test status
Simulation time 12850874042 ps
CPU time 326.23 seconds
Started Aug 21 01:48:35 PM UTC 24
Finished Aug 21 01:54:06 PM UTC 24
Peak memory 383636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3353111716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.kmac_stress_all.3353111716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.2711270852
Short name T521
Test name
Test status
Simulation time 73719465 ps
CPU time 1.34 seconds
Started Aug 21 01:49:46 PM UTC 24
Finished Aug 21 01:49:48 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711270852
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2711
270852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2930567491
Short name T554
Test name
Test status
Simulation time 29082109595 ps
CPU time 299.64 seconds
Started Aug 21 01:49:22 PM UTC 24
Finished Aug 21 01:54:26 PM UTC 24
Peak memory 393528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29305674
91 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2930567491
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.302298161
Short name T669
Test name
Test status
Simulation time 48101271135 ps
CPU time 1291.77 seconds
Started Aug 21 01:49:21 PM UTC 24
Finished Aug 21 02:11:08 PM UTC 24
Peak memory 266484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30229816
1 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_wr
ite.302298161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2666016076
Short name T523
Test name
Test status
Simulation time 4995411326 ps
CPU time 21.95 seconds
Started Aug 21 01:49:30 PM UTC 24
Finished Aug 21 01:49:54 PM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26660160
76 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_ent
ropy_refresh.2666016076 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_error.3392939094
Short name T571
Test name
Test status
Simulation time 16473235633 ps
CPU time 459.93 seconds
Started Aug 21 01:49:30 PM UTC 24
Finished Aug 21 01:57:16 PM UTC 24
Peak memory 579824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3392939094 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3392939094 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.1337040766
Short name T520
Test name
Test status
Simulation time 737444449 ps
CPU time 10.31 seconds
Started Aug 21 01:49:33 PM UTC 24
Finished Aug 21 01:49:45 PM UTC 24
Peak memory 227532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1337040766 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1337040766 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.931211320
Short name T541
Test name
Test status
Simulation time 4434585748 ps
CPU time 244.05 seconds
Started Aug 21 01:48:37 PM UTC 24
Finished Aug 21 01:52:46 PM UTC 24
Peak memory 348388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=93121
1320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.km
ac_long_msg_and_output.931211320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.2812838447
Short name T524
Test name
Test status
Simulation time 4812991002 ps
CPU time 81.55 seconds
Started Aug 21 01:48:40 PM UTC 24
Finished Aug 21 01:50:06 PM UTC 24
Peak memory 260384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281283
8447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload
.2812838447 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.1196242890
Short name T522
Test name
Test status
Simulation time 2398337230 ps
CPU time 69.83 seconds
Started Aug 21 01:48:37 PM UTC 24
Finished Aug 21 01:49:50 PM UTC 24
Peak memory 234004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1196242890 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1196242890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.815748248
Short name T659
Test name
Test status
Simulation time 13259683076 ps
CPU time 1108.3 seconds
Started Aug 21 01:49:46 PM UTC 24
Finished Aug 21 02:08:28 PM UTC 24
Peak memory 564000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=815748248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.kmac_stress_all.815748248 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.1667623447
Short name T532
Test name
Test status
Simulation time 13803359 ps
CPU time 1.2 seconds
Started Aug 21 01:51:13 PM UTC 24
Finished Aug 21 01:51:15 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667623447
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1667
623447 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_app.165576349
Short name T534
Test name
Test status
Simulation time 2196126949 ps
CPU time 44.93 seconds
Started Aug 21 01:50:41 PM UTC 24
Finished Aug 21 01:51:28 PM UTC 24
Peak memory 248060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16557634
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.165576349 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1071795539
Short name T528
Test name
Test status
Simulation time 4118212851 ps
CPU time 56.9 seconds
Started Aug 21 01:50:06 PM UTC 24
Finished Aug 21 01:51:05 PM UTC 24
Peak memory 233976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10717955
39 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_w
rite.1071795539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3296483946
Short name T559
Test name
Test status
Simulation time 11219061512 ps
CPU time 252.22 seconds
Started Aug 21 01:50:48 PM UTC 24
Finished Aug 21 01:55:04 PM UTC 24
Peak memory 405812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32964839
46 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_ent
ropy_refresh.3296483946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_error.1237942040
Short name T561
Test name
Test status
Simulation time 10815319703 ps
CPU time 252.91 seconds
Started Aug 21 01:50:58 PM UTC 24
Finished Aug 21 01:55:15 PM UTC 24
Peak memory 332032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1237942040 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1237942040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.3876240568
Short name T533
Test name
Test status
Simulation time 1112608340 ps
CPU time 15.4 seconds
Started Aug 21 01:51:06 PM UTC 24
Finished Aug 21 01:51:22 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876240568 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3876240568 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3951571475
Short name T530
Test name
Test status
Simulation time 140625732 ps
CPU time 1.96 seconds
Started Aug 21 01:51:06 PM UTC 24
Finished Aug 21 01:51:09 PM UTC 24
Peak memory 231356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951571475 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3951571475 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.1592295308
Short name T707
Test name
Test status
Simulation time 44733960119 ps
CPU time 2748.89 seconds
Started Aug 21 01:49:51 PM UTC 24
Finished Aug 21 02:36:12 PM UTC 24
Peak memory 1511680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15922
95308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.k
mac_long_msg_and_output.1592295308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.3034258373
Short name T548
Test name
Test status
Simulation time 20708025560 ps
CPU time 221.07 seconds
Started Aug 21 01:49:55 PM UTC 24
Finished Aug 21 01:53:39 PM UTC 24
Peak memory 383228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303425
8373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload
.3034258373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.1049112601
Short name T527
Test name
Test status
Simulation time 1362730096 ps
CPU time 66.08 seconds
Started Aug 21 01:49:50 PM UTC 24
Finished Aug 21 01:50:58 PM UTC 24
Peak memory 235776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1049112601 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1049112601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.2920020706
Short name T701
Test name
Test status
Simulation time 142577850443 ps
CPU time 2103.56 seconds
Started Aug 21 01:51:10 PM UTC 24
Finished Aug 21 02:26:38 PM UTC 24
Peak memory 711280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2920020706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_stress_all.2920020706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.1116835643
Short name T543
Test name
Test status
Simulation time 16363208 ps
CPU time 1.32 seconds
Started Aug 21 01:52:46 PM UTC 24
Finished Aug 21 01:52:49 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116835643
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1116
835643 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_app.3058030362
Short name T565
Test name
Test status
Simulation time 13861658626 ps
CPU time 284.8 seconds
Started Aug 21 01:51:43 PM UTC 24
Finished Aug 21 01:56:32 PM UTC 24
Peak memory 456952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30580303
62 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3058030362
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.1761226668
Short name T545
Test name
Test status
Simulation time 13472115240 ps
CPU time 84.53 seconds
Started Aug 21 01:51:29 PM UTC 24
Finished Aug 21 01:52:56 PM UTC 24
Peak memory 250080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17612266
68 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_w
rite.1761226668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.4219122307
Short name T549
Test name
Test status
Simulation time 4876823348 ps
CPU time 115.74 seconds
Started Aug 21 01:51:56 PM UTC 24
Finished Aug 21 01:53:55 PM UTC 24
Peak memory 260416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42191223
07 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_ent
ropy_refresh.4219122307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_error.666831469
Short name T587
Test name
Test status
Simulation time 16146076091 ps
CPU time 445.07 seconds
Started Aug 21 01:52:03 PM UTC 24
Finished Aug 21 01:59:34 PM UTC 24
Peak memory 561404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=666831469 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.666831469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.4174809976
Short name T540
Test name
Test status
Simulation time 5102089875 ps
CPU time 18.99 seconds
Started Aug 21 01:52:25 PM UTC 24
Finished Aug 21 01:52:46 PM UTC 24
Peak memory 227652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174809976 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.4174809976 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.1034133935
Short name T60
Test name
Test status
Simulation time 78623692 ps
CPU time 1.94 seconds
Started Aug 21 01:52:45 PM UTC 24
Finished Aug 21 01:52:48 PM UTC 24
Peak memory 233364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034133935 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1034133935 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.943310185
Short name T706
Test name
Test status
Simulation time 277998400427 ps
CPU time 2639.84 seconds
Started Aug 21 01:51:23 PM UTC 24
Finished Aug 21 02:35:54 PM UTC 24
Peak memory 2640128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94331
0185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.km
ac_long_msg_and_output.943310185 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2325256320
Short name T542
Test name
Test status
Simulation time 729260744 ps
CPU time 77.16 seconds
Started Aug 21 01:51:29 PM UTC 24
Finished Aug 21 01:52:48 PM UTC 24
Peak memory 252168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=232525
6320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload
.2325256320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.3354904836
Short name T539
Test name
Test status
Simulation time 2900441579 ps
CPU time 86.68 seconds
Started Aug 21 01:51:16 PM UTC 24
Finished Aug 21 01:52:45 PM UTC 24
Peak memory 235800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354904836 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3354904836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.849016712
Short name T577
Test name
Test status
Simulation time 4490388083 ps
CPU time 315.69 seconds
Started Aug 21 01:52:46 PM UTC 24
Finished Aug 21 01:58:07 PM UTC 24
Peak memory 318160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=849016712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.kmac_stress_all.849016712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.3114843503
Short name T552
Test name
Test status
Simulation time 31266076 ps
CPU time 1.38 seconds
Started Aug 21 01:54:01 PM UTC 24
Finished Aug 21 01:54:04 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3114843503
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3114
843503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_app.2401524808
Short name T576
Test name
Test status
Simulation time 11810567046 ps
CPU time 289.06 seconds
Started Aug 21 01:52:57 PM UTC 24
Finished Aug 21 01:57:50 PM UTC 24
Peak memory 473396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24015248
08 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2401524808
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.4270013577
Short name T685
Test name
Test status
Simulation time 110324493995 ps
CPU time 1376.48 seconds
Started Aug 21 01:52:55 PM UTC 24
Finished Aug 21 02:16:09 PM UTC 24
Peak memory 268612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42700135
77 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_w
rite.4270013577 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.3741521530
Short name T581
Test name
Test status
Simulation time 6078419520 ps
CPU time 320.75 seconds
Started Aug 21 01:53:09 PM UTC 24
Finished Aug 21 01:58:34 PM UTC 24
Peak memory 342248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37415215
30 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_ent
ropy_refresh.3741521530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_error.1685649456
Short name T583
Test name
Test status
Simulation time 14420821929 ps
CPU time 347.27 seconds
Started Aug 21 01:53:14 PM UTC 24
Finished Aug 21 01:59:06 PM UTC 24
Peak memory 530752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685649456 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1685649456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.3450194097
Short name T551
Test name
Test status
Simulation time 1569772976 ps
CPU time 19.22 seconds
Started Aug 21 01:53:40 PM UTC 24
Finished Aug 21 01:54:01 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3450194097 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3450194097 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.3982901169
Short name T550
Test name
Test status
Simulation time 39014504 ps
CPU time 1.99 seconds
Started Aug 21 01:53:55 PM UTC 24
Finished Aug 21 01:53:58 PM UTC 24
Peak memory 233420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982901169 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3982901169 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.4046228780
Short name T700
Test name
Test status
Simulation time 81901775645 ps
CPU time 1995.68 seconds
Started Aug 21 01:52:50 PM UTC 24
Finished Aug 21 02:26:28 PM UTC 24
Peak memory 2384228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40462
28780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.k
mac_long_msg_and_output.4046228780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.979682558
Short name T564
Test name
Test status
Simulation time 97416339740 ps
CPU time 188.7 seconds
Started Aug 21 01:52:50 PM UTC 24
Finished Aug 21 01:56:02 PM UTC 24
Peak memory 381156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979682
558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.
979682558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.3009812455
Short name T546
Test name
Test status
Simulation time 2246821244 ps
CPU time 17.42 seconds
Started Aug 21 01:52:49 PM UTC 24
Finished Aug 21 01:53:08 PM UTC 24
Peak memory 233940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009812455 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3009812455 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.3524597924
Short name T693
Test name
Test status
Simulation time 42633737066 ps
CPU time 1578.86 seconds
Started Aug 21 01:53:59 PM UTC 24
Finished Aug 21 02:20:37 PM UTC 24
Peak memory 1526016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3524597924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_stress_all.3524597924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.212226735
Short name T202
Test name
Test status
Simulation time 49242281 ps
CPU time 1.23 seconds
Started Aug 21 12:59:05 PM UTC 24
Finished Aug 21 12:59:08 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212226735 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.212226
735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_app.1392675933
Short name T203
Test name
Test status
Simulation time 8431714773 ps
CPU time 238.87 seconds
Started Aug 21 12:55:13 PM UTC 24
Finished Aug 21 12:59:18 PM UTC 24
Peak memory 368956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13926759
33 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1392675933 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3906073099
Short name T201
Test name
Test status
Simulation time 8852150387 ps
CPU time 222.53 seconds
Started Aug 21 12:55:17 PM UTC 24
Finished Aug 21 12:59:04 PM UTC 24
Peak memory 287032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39060730
99 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kma
c_app_with_partial_data.3906073099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.1613517167
Short name T144
Test name
Test status
Simulation time 126882287868 ps
CPU time 1436.72 seconds
Started Aug 21 12:53:23 PM UTC 24
Finished Aug 21 01:17:37 PM UTC 24
Peak memory 270592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16135171
67 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_wr
ite.1613517167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.4241305252
Short name T198
Test name
Test status
Simulation time 147176521 ps
CPU time 6.15 seconds
Started Aug 21 12:57:45 PM UTC 24
Finished Aug 21 12:57:53 PM UTC 24
Peak memory 235360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241305252 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.424
1305252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3716619176
Short name T111
Test name
Test status
Simulation time 25171847 ps
CPU time 1.14 seconds
Started Aug 21 12:57:53 PM UTC 24
Finished Aug 21 12:57:56 PM UTC 24
Peak memory 224320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3716619176 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3
716619176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.2995400749
Short name T200
Test name
Test status
Simulation time 1441480486 ps
CPU time 19.81 seconds
Started Aug 21 12:57:56 PM UTC 24
Finished Aug 21 12:58:18 PM UTC 24
Peak memory 235712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2995400749 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.299540074
9 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3711548759
Short name T80
Test name
Test status
Simulation time 20633948550 ps
CPU time 308.48 seconds
Started Aug 21 12:56:20 PM UTC 24
Finished Aug 21 01:01:33 PM UTC 24
Peak memory 381180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37115487
59 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entr
opy_refresh.3711548759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_error.4277704762
Short name T19
Test name
Test status
Simulation time 25168044709 ps
CPU time 396.96 seconds
Started Aug 21 12:57:07 PM UTC 24
Finished Aug 21 01:03:51 PM UTC 24
Peak memory 508288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4277704762 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.4277704762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.2904588786
Short name T199
Test name
Test status
Simulation time 2055567316 ps
CPU time 15.36 seconds
Started Aug 21 12:57:45 PM UTC 24
Finished Aug 21 12:58:02 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2904588786 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2904588786 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.81457349
Short name T87
Test name
Test status
Simulation time 41021240 ps
CPU time 2.08 seconds
Started Aug 21 12:58:04 PM UTC 24
Finished Aug 21 12:58:07 PM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81457349 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.81457349 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2526067760
Short name T360
Test name
Test status
Simulation time 37888271686 ps
CPU time 2039.8 seconds
Started Aug 21 12:53:14 PM UTC 24
Finished Aug 21 01:27:37 PM UTC 24
Peak memory 1354040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25260
67760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.km
ac_long_msg_and_output.2526067760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.1141470130
Short name T67
Test name
Test status
Simulation time 12387597409 ps
CPU time 244.42 seconds
Started Aug 21 12:56:25 PM UTC 24
Finished Aug 21 01:00:34 PM UTC 24
Peak memory 373484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141470130 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1141470130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.3441714772
Short name T113
Test name
Test status
Simulation time 31048750503 ps
CPU time 173.97 seconds
Started Aug 21 12:58:19 PM UTC 24
Finished Aug 21 01:01:16 PM UTC 24
Peak memory 319044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441714772 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3441714772
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.3337660835
Short name T22
Test name
Test status
Simulation time 16405596754 ps
CPU time 263.52 seconds
Started Aug 21 12:53:16 PM UTC 24
Finished Aug 21 12:57:44 PM UTC 24
Peak memory 432436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=333766
0835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.
3337660835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.3279081634
Short name T180
Test name
Test status
Simulation time 6012786505 ps
CPU time 44.29 seconds
Started Aug 21 12:52:59 PM UTC 24
Finished Aug 21 12:53:45 PM UTC 24
Peak memory 233916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3279081634 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3279081634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.790352354
Short name T456
Test name
Test status
Simulation time 276560502713 ps
CPU time 2636.08 seconds
Started Aug 21 12:58:08 PM UTC 24
Finished Aug 21 01:42:34 PM UTC 24
Peak memory 1319560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=790352354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.kmac_stress_all.790352354 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all_with_rand_reset.976707565
Short name T69
Test name
Test status
Simulation time 3928374970 ps
CPU time 186.51 seconds
Started Aug 21 12:58:16 PM UTC 24
Finished Aug 21 01:01:26 PM UTC 24
Peak memory 269136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/
lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=976707565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.976707565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.4043153098
Short name T194
Test name
Test status
Simulation time 193964485 ps
CPU time 3.96 seconds
Started Aug 21 12:54:59 PM UTC 24
Finished Aug 21 12:55:05 PM UTC 24
Peak memory 229820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4043153098 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.4043153098 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.2833247005
Short name T195
Test name
Test status
Simulation time 129084256 ps
CPU time 4.62 seconds
Started Aug 21 12:55:06 PM UTC 24
Finished Aug 21 12:55:12 PM UTC 24
Peak memory 229832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2833247005 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.2833247
005 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3891105533
Short name T488
Test name
Test status
Simulation time 376486560069 ps
CPU time 3086.15 seconds
Started Aug 21 12:53:34 PM UTC 24
Finished Aug 21 01:45:36 PM UTC 24
Peak memory 3113176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=3891105533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3891105533 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.4039050972
Short name T193
Test name
Test status
Simulation time 7562523468 ps
CPU time 68.67 seconds
Started Aug 21 12:53:46 PM UTC 24
Finished Aug 21 12:54:58 PM UTC 24
Peak memory 256176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=4039050972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.kmac_test_vectors_sha3_256.4039050972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2127761386
Short name T341
Test name
Test status
Simulation time 257079924045 ps
CPU time 1854.66 seconds
Started Aug 21 12:54:04 PM UTC 24
Finished Aug 21 01:25:20 PM UTC 24
Peak memory 2310360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=2127761386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2127761386 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.1328863350
Short name T264
Test name
Test status
Simulation time 34711271296 ps
CPU time 1200.1 seconds
Started Aug 21 12:54:07 PM UTC 24
Finished Aug 21 01:14:22 PM UTC 24
Peak memory 706720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_v
ariant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/si
m.tcl +ntb_random_seed=1328863350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1328863350 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.873305230
Short name T515
Test name
Test status
Simulation time 365391834542 ps
CPU time 3254.47 seconds
Started Aug 21 12:54:30 PM UTC 24
Finished Aug 21 01:49:21 PM UTC 24
Peak memory 3594468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=873305230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 4.kmac_test_vectors_shake_128.873305230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2451787964
Short name T475
Test name
Test status
Simulation time 173712587872 ps
CPU time 2935.09 seconds
Started Aug 21 12:54:46 PM UTC 24
Finished Aug 21 01:44:15 PM UTC 24
Peak memory 3008684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_
variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2451787964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2451787964 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.3848838414
Short name T562
Test name
Test status
Simulation time 18578951 ps
CPU time 1.33 seconds
Started Aug 21 01:55:17 PM UTC 24
Finished Aug 21 01:55:20 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848838414
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3848
838414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_app.3156363002
Short name T613
Test name
Test status
Simulation time 17921119564 ps
CPU time 458.95 seconds
Started Aug 21 01:54:51 PM UTC 24
Finished Aug 21 02:02:36 PM UTC 24
Peak memory 561408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31563630
02 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3156363002
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1735317434
Short name T567
Test name
Test status
Simulation time 1070892940 ps
CPU time 123.55 seconds
Started Aug 21 01:54:49 PM UTC 24
Finished Aug 21 01:56:55 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17353174
34 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_w
rite.1735317434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3706619043
Short name T569
Test name
Test status
Simulation time 4566444690 ps
CPU time 128.95 seconds
Started Aug 21 01:54:55 PM UTC 24
Finished Aug 21 01:57:06 PM UTC 24
Peak memory 274692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37066190
43 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_ent
ropy_refresh.3706619043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_error.324436351
Short name T595
Test name
Test status
Simulation time 7759534698 ps
CPU time 314.04 seconds
Started Aug 21 01:55:00 PM UTC 24
Finished Aug 21 02:00:19 PM UTC 24
Peak memory 344372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324436351 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.324436351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2532462578
Short name T560
Test name
Test status
Simulation time 899836820 ps
CPU time 6.5 seconds
Started Aug 21 01:55:05 PM UTC 24
Finished Aug 21 01:55:13 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2532462578 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2532462578 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.288994490
Short name T683
Test name
Test status
Simulation time 62209185949 ps
CPU time 1278.25 seconds
Started Aug 21 01:54:08 PM UTC 24
Finished Aug 21 02:15:41 PM UTC 24
Peak memory 1626448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28899
4490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.km
ac_long_msg_and_output.288994490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.725643024
Short name T582
Test name
Test status
Simulation time 101763235135 ps
CPU time 263.74 seconds
Started Aug 21 01:54:28 PM UTC 24
Finished Aug 21 01:58:55 PM UTC 24
Peak memory 397632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=725643
024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.
725643024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.1427552566
Short name T556
Test name
Test status
Simulation time 5538771930 ps
CPU time 43.48 seconds
Started Aug 21 01:54:04 PM UTC 24
Finished Aug 21 01:54:50 PM UTC 24
Peak memory 235844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1427552566 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1427552566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.2548751098
Short name T584
Test name
Test status
Simulation time 64240889898 ps
CPU time 228.26 seconds
Started Aug 21 01:55:16 PM UTC 24
Finished Aug 21 01:59:08 PM UTC 24
Peak memory 344792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2548751098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_stress_all.2548751098 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.3501842857
Short name T572
Test name
Test status
Simulation time 20750528 ps
CPU time 1.27 seconds
Started Aug 21 01:57:16 PM UTC 24
Finished Aug 21 01:57:18 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3501842857
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3501
842857 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_app.2651297190
Short name T586
Test name
Test status
Simulation time 12224476749 ps
CPU time 197.18 seconds
Started Aug 21 01:56:08 PM UTC 24
Finished Aug 21 01:59:28 PM UTC 24
Peak memory 291064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26512971
90 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2651297190
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.1227723786
Short name T579
Test name
Test status
Simulation time 1449002904 ps
CPU time 136.83 seconds
Started Aug 21 01:56:02 PM UTC 24
Finished Aug 21 01:58:22 PM UTC 24
Peak memory 235776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12277237
86 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_w
rite.1227723786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.1429011921
Short name T599
Test name
Test status
Simulation time 22358309804 ps
CPU time 306.18 seconds
Started Aug 21 01:56:33 PM UTC 24
Finished Aug 21 02:01:44 PM UTC 24
Peak memory 446780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14290119
21 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_ent
ropy_refresh.1429011921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_error.4259128339
Short name T606
Test name
Test status
Simulation time 20251264614 ps
CPU time 328.26 seconds
Started Aug 21 01:56:34 PM UTC 24
Finished Aug 21 02:02:07 PM UTC 24
Peak memory 450884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259128339 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.4259128339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.1263936573
Short name T568
Test name
Test status
Simulation time 3147300751 ps
CPU time 4.13 seconds
Started Aug 21 01:56:56 PM UTC 24
Finished Aug 21 01:57:01 PM UTC 24
Peak memory 227716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1263936573 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1263936573 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.2056622215
Short name T574
Test name
Test status
Simulation time 1873111069 ps
CPU time 21.62 seconds
Started Aug 21 01:57:02 PM UTC 24
Finished Aug 21 01:57:25 PM UTC 24
Peak memory 262468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056622215 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2056622215 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.2221454915
Short name T708
Test name
Test status
Simulation time 436606567900 ps
CPU time 2663.32 seconds
Started Aug 21 01:55:21 PM UTC 24
Finished Aug 21 02:40:14 PM UTC 24
Peak memory 2843000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22214
54915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.k
mac_long_msg_and_output.2221454915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.1362880924
Short name T629
Test name
Test status
Simulation time 67528579975 ps
CPU time 541.01 seconds
Started Aug 21 01:55:49 PM UTC 24
Finished Aug 21 02:04:58 PM UTC 24
Peak memory 618784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136288
0924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload
.1362880924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2217626906
Short name T563
Test name
Test status
Simulation time 1862688173 ps
CPU time 25.79 seconds
Started Aug 21 01:55:21 PM UTC 24
Finished Aug 21 01:55:48 PM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2217626906 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2217626906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.3642076845
Short name T609
Test name
Test status
Simulation time 6538756198 ps
CPU time 309.43 seconds
Started Aug 21 01:57:07 PM UTC 24
Finished Aug 21 02:02:21 PM UTC 24
Peak memory 407812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3642076845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_stress_all.3642076845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1743865481
Short name T580
Test name
Test status
Simulation time 21456200 ps
CPU time 1.26 seconds
Started Aug 21 01:58:29 PM UTC 24
Finished Aug 21 01:58:31 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743865481
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1743
865481 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_app.2334584363
Short name T628
Test name
Test status
Simulation time 43215317945 ps
CPU time 440.19 seconds
Started Aug 21 01:57:26 PM UTC 24
Finished Aug 21 02:04:54 PM UTC 24
Peak memory 518444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23345843
63 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2334584363
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.2004440202
Short name T686
Test name
Test status
Simulation time 31507468470 ps
CPU time 1132.88 seconds
Started Aug 21 01:57:25 PM UTC 24
Finished Aug 21 02:16:33 PM UTC 24
Peak memory 252168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20044402
02 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_w
rite.2004440202 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.2894405459
Short name T612
Test name
Test status
Simulation time 51768015824 ps
CPU time 299.28 seconds
Started Aug 21 01:57:30 PM UTC 24
Finished Aug 21 02:02:33 PM UTC 24
Peak memory 430400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28944054
59 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_ent
ropy_refresh.2894405459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_error.3441122188
Short name T588
Test name
Test status
Simulation time 1096780362 ps
CPU time 102.06 seconds
Started Aug 21 01:57:51 PM UTC 24
Finished Aug 21 01:59:35 PM UTC 24
Peak memory 268548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441122188 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3441122188 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.993573158
Short name T578
Test name
Test status
Simulation time 178017711 ps
CPU time 3.11 seconds
Started Aug 21 01:58:08 PM UTC 24
Finished Aug 21 01:58:13 PM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=993573158 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.993573158 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.3199754699
Short name T64
Test name
Test status
Simulation time 180541316 ps
CPU time 14.46 seconds
Started Aug 21 01:58:13 PM UTC 24
Finished Aug 21 01:58:29 PM UTC 24
Peak memory 250192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3199754699 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3199754699 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.844382824
Short name T711
Test name
Test status
Simulation time 24187427344 ps
CPU time 2839.67 seconds
Started Aug 21 01:57:19 PM UTC 24
Finished Aug 21 02:45:12 PM UTC 24
Peak memory 1700156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84438
2824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.km
ac_long_msg_and_output.844382824 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.3211035334
Short name T625
Test name
Test status
Simulation time 56361254990 ps
CPU time 425.29 seconds
Started Aug 21 01:57:22 PM UTC 24
Finished Aug 21 02:04:34 PM UTC 24
Peak memory 366992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=321103
5334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload
.3211035334 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.515632988
Short name T573
Test name
Test status
Simulation time 278949940 ps
CPU time 5.27 seconds
Started Aug 21 01:57:18 PM UTC 24
Finished Aug 21 01:57:24 PM UTC 24
Peak memory 234856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=515632988 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.515632988 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.3549364972
Short name T709
Test name
Test status
Simulation time 69286860103 ps
CPU time 2633.58 seconds
Started Aug 21 01:58:23 PM UTC 24
Finished Aug 21 02:42:47 PM UTC 24
Peak memory 1618696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3549364972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_stress_all.3549364972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.2945602578
Short name T591
Test name
Test status
Simulation time 14267680 ps
CPU time 1.21 seconds
Started Aug 21 01:59:40 PM UTC 24
Finished Aug 21 01:59:42 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2945602578
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2945
602578 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_app.922756746
Short name T602
Test name
Test status
Simulation time 11970306034 ps
CPU time 159.43 seconds
Started Aug 21 01:59:10 PM UTC 24
Finished Aug 21 02:01:52 PM UTC 24
Peak memory 284900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=92275674
6 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.922756746 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.2732404542
Short name T668
Test name
Test status
Simulation time 32776273937 ps
CPU time 701.08 seconds
Started Aug 21 01:59:06 PM UTC 24
Finished Aug 21 02:10:57 PM UTC 24
Peak memory 254216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27324045
42 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_w
rite.2732404542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2839080489
Short name T619
Test name
Test status
Simulation time 42853311576 ps
CPU time 285.63 seconds
Started Aug 21 01:59:19 PM UTC 24
Finished Aug 21 02:04:08 PM UTC 24
Peak memory 325920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28390804
89 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_ent
ropy_refresh.2839080489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_error.1667308530
Short name T594
Test name
Test status
Simulation time 1244284253 ps
CPU time 34.1 seconds
Started Aug 21 01:59:30 PM UTC 24
Finished Aug 21 02:00:06 PM UTC 24
Peak memory 276720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667308530 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1667308530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.4235147257
Short name T592
Test name
Test status
Simulation time 1872760066 ps
CPU time 8.18 seconds
Started Aug 21 01:59:35 PM UTC 24
Finished Aug 21 01:59:44 PM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235147257 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.4235147257 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.2385811030
Short name T590
Test name
Test status
Simulation time 45976138 ps
CPU time 2.15 seconds
Started Aug 21 01:59:36 PM UTC 24
Finished Aug 21 01:59:39 PM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385811030 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2385811030 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.255728603
Short name T704
Test name
Test status
Simulation time 53452297650 ps
CPU time 2103.05 seconds
Started Aug 21 01:58:35 PM UTC 24
Finished Aug 21 02:34:02 PM UTC 24
Peak memory 2578824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25572
8603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.km
ac_long_msg_and_output.255728603 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.1675122047
Short name T637
Test name
Test status
Simulation time 32642511601 ps
CPU time 388.41 seconds
Started Aug 21 01:58:56 PM UTC 24
Finished Aug 21 02:05:30 PM UTC 24
Peak memory 579812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167512
2047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload
.1675122047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.377550528
Short name T593
Test name
Test status
Simulation time 17399504151 ps
CPU time 88.17 seconds
Started Aug 21 01:58:32 PM UTC 24
Finished Aug 21 02:00:03 PM UTC 24
Peak memory 235836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=377550528 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.377550528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.702696969
Short name T692
Test name
Test status
Simulation time 75736809955 ps
CPU time 1176.95 seconds
Started Aug 21 01:59:39 PM UTC 24
Finished Aug 21 02:19:30 PM UTC 24
Peak memory 1268100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=702696969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.kmac_stress_all.702696969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.1068772178
Short name T603
Test name
Test status
Simulation time 53940109 ps
CPU time 1.26 seconds
Started Aug 21 02:01:51 PM UTC 24
Finished Aug 21 02:01:53 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1068772178
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1068
772178 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_app.111641719
Short name T651
Test name
Test status
Simulation time 40769197528 ps
CPU time 435.34 seconds
Started Aug 21 02:00:20 PM UTC 24
Finished Aug 21 02:07:41 PM UTC 24
Peak memory 473460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11164171
9 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.111641719 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.845663376
Short name T645
Test name
Test status
Simulation time 42209755114 ps
CPU time 412.28 seconds
Started Aug 21 02:00:07 PM UTC 24
Finished Aug 21 02:07:06 PM UTC 24
Peak memory 252228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84566337
6 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_wr
ite.845663376 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1637647427
Short name T658
Test name
Test status
Simulation time 28865643964 ps
CPU time 461.78 seconds
Started Aug 21 02:00:38 PM UTC 24
Finished Aug 21 02:08:26 PM UTC 24
Peak memory 504116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16376474
27 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_ent
ropy_refresh.1637647427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_error.107274565
Short name T633
Test name
Test status
Simulation time 2503568553 ps
CPU time 249.22 seconds
Started Aug 21 02:00:55 PM UTC 24
Finished Aug 21 02:05:09 PM UTC 24
Peak memory 315768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107274565 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.107274565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.1970103422
Short name T601
Test name
Test status
Simulation time 2266682396 ps
CPU time 13.87 seconds
Started Aug 21 02:01:34 PM UTC 24
Finished Aug 21 02:01:49 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970103422 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1970103422 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.2701169911
Short name T604
Test name
Test status
Simulation time 623990604 ps
CPU time 12.79 seconds
Started Aug 21 02:01:44 PM UTC 24
Finished Aug 21 02:01:59 PM UTC 24
Peak memory 235720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701169911 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2701169911 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1803632897
Short name T713
Test name
Test status
Simulation time 26113290214 ps
CPU time 2858.85 seconds
Started Aug 21 01:59:45 PM UTC 24
Finished Aug 21 02:47:57 PM UTC 24
Peak memory 1730936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18036
32897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.k
mac_long_msg_and_output.1803632897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.2625502837
Short name T650
Test name
Test status
Simulation time 26383078176 ps
CPU time 444.73 seconds
Started Aug 21 02:00:06 PM UTC 24
Finished Aug 21 02:07:37 PM UTC 24
Peak memory 581888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262550
2837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload
.2625502837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.594782981
Short name T596
Test name
Test status
Simulation time 2952922329 ps
CPU time 52.35 seconds
Started Aug 21 01:59:43 PM UTC 24
Finished Aug 21 02:00:37 PM UTC 24
Peak memory 235776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594782981 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.594782981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.2677923302
Short name T696
Test name
Test status
Simulation time 75047383664 ps
CPU time 1351.45 seconds
Started Aug 21 02:01:47 PM UTC 24
Finished Aug 21 02:24:36 PM UTC 24
Peak memory 641728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2677923302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 44.kmac_stress_all.2677923302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.3926101697
Short name T614
Test name
Test status
Simulation time 28904694 ps
CPU time 1.29 seconds
Started Aug 21 02:02:35 PM UTC 24
Finished Aug 21 02:02:38 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3926101697
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3926
101697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_app.1400528867
Short name T610
Test name
Test status
Simulation time 1619162719 ps
CPU time 15.91 seconds
Started Aug 21 02:02:08 PM UTC 24
Finished Aug 21 02:02:25 PM UTC 24
Peak memory 246008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14005288
67 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1400528867
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2502992560
Short name T698
Test name
Test status
Simulation time 59617256931 ps
CPU time 1395.8 seconds
Started Aug 21 02:02:04 PM UTC 24
Finished Aug 21 02:25:37 PM UTC 24
Peak memory 272640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25029925
60 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_w
rite.2502992560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1052611915
Short name T647
Test name
Test status
Simulation time 32954160631 ps
CPU time 299.26 seconds
Started Aug 21 02:02:09 PM UTC 24
Finished Aug 21 02:07:13 PM UTC 24
Peak memory 336168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10526119
15 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_ent
ropy_refresh.1052611915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_error.3595133804
Short name T661
Test name
Test status
Simulation time 22597231196 ps
CPU time 419.21 seconds
Started Aug 21 02:02:20 PM UTC 24
Finished Aug 21 02:09:25 PM UTC 24
Peak memory 381160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3595133804 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3595133804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.3582928265
Short name T615
Test name
Test status
Simulation time 12239394664 ps
CPU time 28.2 seconds
Started Aug 21 02:02:22 PM UTC 24
Finished Aug 21 02:02:52 PM UTC 24
Peak memory 227664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3582928265 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3582928265 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.1117569300
Short name T611
Test name
Test status
Simulation time 423355921 ps
CPU time 1.93 seconds
Started Aug 21 02:02:26 PM UTC 24
Finished Aug 21 02:02:29 PM UTC 24
Peak memory 233364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117569300 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1117569300 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.2784651575
Short name T680
Test name
Test status
Simulation time 40303976691 ps
CPU time 784.78 seconds
Started Aug 21 02:01:54 PM UTC 24
Finished Aug 21 02:15:09 PM UTC 24
Peak memory 1169652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27846
51575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.k
mac_long_msg_and_output.2784651575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.85547824
Short name T642
Test name
Test status
Simulation time 11066207440 ps
CPU time 277.4 seconds
Started Aug 21 02:02:00 PM UTC 24
Finished Aug 21 02:06:42 PM UTC 24
Peak memory 313652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=855478
24 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.8
5547824 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2867082721
Short name T618
Test name
Test status
Simulation time 10262067351 ps
CPU time 127.27 seconds
Started Aug 21 02:01:53 PM UTC 24
Finished Aug 21 02:04:03 PM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867082721 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2867082721 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.910821515
Short name T681
Test name
Test status
Simulation time 12333345966 ps
CPU time 770.18 seconds
Started Aug 21 02:02:30 PM UTC 24
Finished Aug 21 02:15:31 PM UTC 24
Peak memory 332032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=910821515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.kmac_stress_all.910821515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.2590031834
Short name T626
Test name
Test status
Simulation time 13522982 ps
CPU time 1.23 seconds
Started Aug 21 02:04:32 PM UTC 24
Finished Aug 21 02:04:34 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590031834
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2590
031834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_app.786348266
Short name T663
Test name
Test status
Simulation time 48904923356 ps
CPU time 394.89 seconds
Started Aug 21 02:03:27 PM UTC 24
Finished Aug 21 02:10:09 PM UTC 24
Peak memory 477432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78634826
6 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.786348266 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.564998808
Short name T623
Test name
Test status
Simulation time 3767353455 ps
CPU time 61.25 seconds
Started Aug 21 02:03:27 PM UTC 24
Finished Aug 21 02:04:31 PM UTC 24
Peak memory 235760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56499880
8 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_wr
ite.564998808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.51611859
Short name T648
Test name
Test status
Simulation time 6819526163 ps
CPU time 190.48 seconds
Started Aug 21 02:04:03 PM UTC 24
Finished Aug 21 02:07:17 PM UTC 24
Peak memory 336164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51611859
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entro
py_refresh.51611859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_error.2772455256
Short name T670
Test name
Test status
Simulation time 47597893088 ps
CPU time 459.37 seconds
Started Aug 21 02:04:09 PM UTC 24
Finished Aug 21 02:11:55 PM UTC 24
Peak memory 629060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2772455256 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2772455256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.762009090
Short name T624
Test name
Test status
Simulation time 2376958644 ps
CPU time 11.07 seconds
Started Aug 21 02:04:19 PM UTC 24
Finished Aug 21 02:04:32 PM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=762009090 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.762009090 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.24113189
Short name T622
Test name
Test status
Simulation time 108517869 ps
CPU time 1.99 seconds
Started Aug 21 02:04:23 PM UTC 24
Finished Aug 21 02:04:26 PM UTC 24
Peak memory 231352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24113189 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.24113189 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2376713336
Short name T715
Test name
Test status
Simulation time 237229102992 ps
CPU time 2899.09 seconds
Started Aug 21 02:02:39 PM UTC 24
Finished Aug 21 02:51:32 PM UTC 24
Peak memory 1644916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23767
13336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.k
mac_long_msg_and_output.2376713336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.2790057693
Short name T641
Test name
Test status
Simulation time 38888635336 ps
CPU time 221.55 seconds
Started Aug 21 02:02:53 PM UTC 24
Finished Aug 21 02:06:38 PM UTC 24
Peak memory 436532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279005
7693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload
.2790057693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2819524276
Short name T616
Test name
Test status
Simulation time 2061733989 ps
CPU time 47.11 seconds
Started Aug 21 02:02:37 PM UTC 24
Finished Aug 21 02:03:26 PM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819524276 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2819524276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1805464469
Short name T630
Test name
Test status
Simulation time 1476252899 ps
CPU time 36.77 seconds
Started Aug 21 02:04:27 PM UTC 24
Finished Aug 21 02:05:05 PM UTC 24
Peak memory 235696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1805464469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 46.kmac_stress_all.1805464469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.3358798202
Short name T635
Test name
Test status
Simulation time 43805607 ps
CPU time 0.91 seconds
Started Aug 21 02:05:15 PM UTC 24
Finished Aug 21 02:05:18 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3358798202
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3358
798202 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_app.2974592325
Short name T639
Test name
Test status
Simulation time 6298533038 ps
CPU time 49.33 seconds
Started Aug 21 02:04:54 PM UTC 24
Finished Aug 21 02:05:46 PM UTC 24
Peak memory 254204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29745923
25 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2974592325
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.1778115493
Short name T705
Test name
Test status
Simulation time 59130781089 ps
CPU time 1749.14 seconds
Started Aug 21 02:04:42 PM UTC 24
Finished Aug 21 02:34:13 PM UTC 24
Peak memory 256324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17781154
93 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_w
rite.1778115493 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1381244559
Short name T631
Test name
Test status
Simulation time 198053110 ps
CPU time 5.33 seconds
Started Aug 21 02:04:59 PM UTC 24
Finished Aug 21 02:05:07 PM UTC 24
Peak memory 235112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13812445
59 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_ent
ropy_refresh.1381244559 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_error.4082857839
Short name T671
Test name
Test status
Simulation time 65096168218 ps
CPU time 414.29 seconds
Started Aug 21 02:05:06 PM UTC 24
Finished Aug 21 02:12:06 PM UTC 24
Peak memory 569660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4082857839 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.4082857839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2963024933
Short name T636
Test name
Test status
Simulation time 8229871286 ps
CPU time 8.33 seconds
Started Aug 21 02:05:07 PM UTC 24
Finished Aug 21 02:05:18 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963024933 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2963024933 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.2342257927
Short name T634
Test name
Test status
Simulation time 100327056 ps
CPU time 1.88 seconds
Started Aug 21 02:05:09 PM UTC 24
Finished Aug 21 02:05:14 PM UTC 24
Peak memory 231376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342257927 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2342257927 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.974208071
Short name T672
Test name
Test status
Simulation time 16014538108 ps
CPU time 479.19 seconds
Started Aug 21 02:04:35 PM UTC 24
Finished Aug 21 02:12:41 PM UTC 24
Peak memory 479472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97420
8071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.km
ac_long_msg_and_output.974208071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.1964399254
Short name T664
Test name
Test status
Simulation time 11581824699 ps
CPU time 343.44 seconds
Started Aug 21 02:04:35 PM UTC 24
Finished Aug 21 02:10:24 PM UTC 24
Peak memory 452888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=196439
9254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload
.1964399254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.2162134170
Short name T632
Test name
Test status
Simulation time 4841416614 ps
CPU time 34.08 seconds
Started Aug 21 02:04:33 PM UTC 24
Finished Aug 21 02:05:08 PM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2162134170 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2162134170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.1751183262
Short name T646
Test name
Test status
Simulation time 16534319 ps
CPU time 1.24 seconds
Started Aug 21 02:07:07 PM UTC 24
Finished Aug 21 02:07:10 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1751183262
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1751
183262 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_app.3711898274
Short name T644
Test name
Test status
Simulation time 5680937447 ps
CPU time 59.86 seconds
Started Aug 21 02:05:46 PM UTC 24
Finished Aug 21 02:06:48 PM UTC 24
Peak memory 274676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37118982
74 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3711898274
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.3423248496
Short name T674
Test name
Test status
Simulation time 6551501924 ps
CPU time 442.29 seconds
Started Aug 21 02:05:46 PM UTC 24
Finished Aug 21 02:13:14 PM UTC 24
Peak memory 252220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34232484
96 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_w
rite.3423248496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1164156839
Short name T649
Test name
Test status
Simulation time 13124987055 ps
CPU time 63.28 seconds
Started Aug 21 02:06:15 PM UTC 24
Finished Aug 21 02:07:20 PM UTC 24
Peak memory 278848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11641568
39 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_ent
ropy_refresh.1164156839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1358863394
Short name T662
Test name
Test status
Simulation time 22593382159 ps
CPU time 169.56 seconds
Started Aug 21 02:06:39 PM UTC 24
Finished Aug 21 02:09:32 PM UTC 24
Peak memory 393532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1358863394 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1358863394 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.3080582036
Short name T643
Test name
Test status
Simulation time 229984939 ps
CPU time 2.05 seconds
Started Aug 21 02:06:43 PM UTC 24
Finished Aug 21 02:06:46 PM UTC 24
Peak memory 227368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080582036 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3080582036 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.1645568204
Short name T653
Test name
Test status
Simulation time 709848569 ps
CPU time 60.6 seconds
Started Aug 21 02:06:47 PM UTC 24
Finished Aug 21 02:07:49 PM UTC 24
Peak memory 262400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645568204 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1645568204 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.795644262
Short name T716
Test name
Test status
Simulation time 99360472572 ps
CPU time 2873.33 seconds
Started Aug 21 02:05:19 PM UTC 24
Finished Aug 21 02:53:46 PM UTC 24
Peak memory 1667396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79564
4262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.km
ac_long_msg_and_output.795644262 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.2638217622
Short name T682
Test name
Test status
Simulation time 44359683774 ps
CPU time 598.33 seconds
Started Aug 21 02:05:31 PM UTC 24
Finished Aug 21 02:15:37 PM UTC 24
Peak memory 676068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263821
7622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload
.2638217622 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.362685986
Short name T640
Test name
Test status
Simulation time 1974699593 ps
CPU time 53.67 seconds
Started Aug 21 02:05:19 PM UTC 24
Finished Aug 21 02:06:15 PM UTC 24
Peak memory 235740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362685986 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.362685986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.3335966914
Short name T687
Test name
Test status
Simulation time 36791423098 ps
CPU time 589.82 seconds
Started Aug 21 02:06:49 PM UTC 24
Finished Aug 21 02:16:46 PM UTC 24
Peak memory 764612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=3335966914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 48.kmac_stress_all.3335966914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.4196661164
Short name T657
Test name
Test status
Simulation time 32894598 ps
CPU time 1.29 seconds
Started Aug 21 02:08:18 PM UTC 24
Finished Aug 21 02:08:20 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4196661164
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4196
661164 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_app.2155616481
Short name T677
Test name
Test status
Simulation time 4834692406 ps
CPU time 351.3 seconds
Started Aug 21 02:07:38 PM UTC 24
Finished Aug 21 02:13:36 PM UTC 24
Peak memory 340348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21556164
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2155616481
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3699653812
Short name T688
Test name
Test status
Simulation time 13797381629 ps
CPU time 584.64 seconds
Started Aug 21 02:07:21 PM UTC 24
Finished Aug 21 02:17:14 PM UTC 24
Peak memory 252196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36996538
12 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_w
rite.3699653812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.4172039469
Short name T660
Test name
Test status
Simulation time 1786256511 ps
CPU time 64.08 seconds
Started Aug 21 02:07:42 PM UTC 24
Finished Aug 21 02:08:48 PM UTC 24
Peak memory 264460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41720394
69 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_ent
ropy_refresh.4172039469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3835638139
Short name T676
Test name
Test status
Simulation time 23544404412 ps
CPU time 336.89 seconds
Started Aug 21 02:07:43 PM UTC 24
Finished Aug 21 02:13:25 PM UTC 24
Peak memory 514388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835638139 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3835638139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.1095289629
Short name T654
Test name
Test status
Simulation time 119427693 ps
CPU time 2.11 seconds
Started Aug 21 02:07:50 PM UTC 24
Finished Aug 21 02:07:53 PM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1095289629 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.1095289629 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.1097605686
Short name T655
Test name
Test status
Simulation time 193584573 ps
CPU time 2.2 seconds
Started Aug 21 02:07:54 PM UTC 24
Finished Aug 21 02:07:57 PM UTC 24
Peak memory 233948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097605686 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1097605686 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3905194902
Short name T694
Test name
Test status
Simulation time 138866384374 ps
CPU time 869.01 seconds
Started Aug 21 02:07:14 PM UTC 24
Finished Aug 21 02:21:54 PM UTC 24
Peak memory 1184056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39051
94902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.k
mac_long_msg_and_output.3905194902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2248541229
Short name T666
Test name
Test status
Simulation time 11636357307 ps
CPU time 195.85 seconds
Started Aug 21 02:07:18 PM UTC 24
Finished Aug 21 02:10:37 PM UTC 24
Peak memory 379136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=224854
1229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload
.2248541229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.1864049993
Short name T656
Test name
Test status
Simulation time 6661377029 ps
CPU time 63.73 seconds
Started Aug 21 02:07:11 PM UTC 24
Finished Aug 21 02:08:17 PM UTC 24
Peak memory 231980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864049993 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1864049993 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.865597102
Short name T665
Test name
Test status
Simulation time 5377129242 ps
CPU time 150.87 seconds
Started Aug 21 02:07:58 PM UTC 24
Finished Aug 21 02:10:31 PM UTC 24
Peak memory 316048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=865597102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.kmac_stress_all.865597102 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3924053572
Short name T130
Test name
Test status
Simulation time 35962485 ps
CPU time 1.18 seconds
Started Aug 21 01:01:34 PM UTC 24
Finished Aug 21 01:01:37 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924053572
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.39240
53572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_app.3940481871
Short name T129
Test name
Test status
Simulation time 9672748686 ps
CPU time 75.68 seconds
Started Aug 21 01:00:07 PM UTC 24
Finished Aug 21 01:01:26 PM UTC 24
Peak memory 272768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39404818
71 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3940481871 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1827966700
Short name T214
Test name
Test status
Simulation time 6313837950 ps
CPU time 282.99 seconds
Started Aug 21 01:00:08 PM UTC 24
Finished Aug 21 01:04:56 PM UTC 24
Peak memory 299252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18279667
00 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kma
c_app_with_partial_data.1827966700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.3910081475
Short name T369
Test name
Test status
Simulation time 28000992960 ps
CPU time 1759.23 seconds
Started Aug 21 12:59:27 PM UTC 24
Finished Aug 21 01:29:09 PM UTC 24
Peak memory 256324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39100814
75 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_wr
ite.3910081475 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1896142199
Short name T205
Test name
Test status
Simulation time 815210287 ps
CPU time 44 seconds
Started Aug 21 01:01:18 PM UTC 24
Finished Aug 21 01:02:04 PM UTC 24
Peak memory 235212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1896142199 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.189
6142199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1343142871
Short name T128
Test name
Test status
Simulation time 513563464 ps
CPU time 1.88 seconds
Started Aug 21 01:01:23 PM UTC 24
Finished Aug 21 01:01:26 PM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1343142871 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1
343142871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.219887033
Short name T162
Test name
Test status
Simulation time 1670685760 ps
CPU time 25.87 seconds
Started Aug 21 01:01:27 PM UTC 24
Finished Aug 21 01:01:54 PM UTC 24
Peak memory 229836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=219887033 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.219887033
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2607210681
Short name T83
Test name
Test status
Simulation time 1022434167 ps
CPU time 60.17 seconds
Started Aug 21 01:00:35 PM UTC 24
Finished Aug 21 01:01:37 PM UTC 24
Peak memory 246008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26072106
81 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entr
opy_refresh.2607210681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.4083585930
Short name T127
Test name
Test status
Simulation time 9479922683 ps
CPU time 15.92 seconds
Started Aug 21 01:01:04 PM UTC 24
Finished Aug 21 01:01:21 PM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083585930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.4083585930 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.78405564
Short name T38
Test name
Test status
Simulation time 782533172 ps
CPU time 14.89 seconds
Started Aug 21 01:01:27 PM UTC 24
Finished Aug 21 01:01:43 PM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78405564 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.78405564 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.2673241104
Short name T212
Test name
Test status
Simulation time 15056549029 ps
CPU time 289.34 seconds
Started Aug 21 12:59:18 PM UTC 24
Finished Aug 21 01:04:12 PM UTC 24
Peak memory 393464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26732
41104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.km
ac_long_msg_and_output.2673241104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.509629566
Short name T226
Test name
Test status
Simulation time 56412646693 ps
CPU time 448.1 seconds
Started Aug 21 01:00:52 PM UTC 24
Finished Aug 21 01:08:27 PM UTC 24
Peak memory 524924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509629566 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.509629566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.4088271734
Short name T126
Test name
Test status
Simulation time 1331889095 ps
CPU time 99.38 seconds
Started Aug 21 12:59:21 PM UTC 24
Finished Aug 21 01:01:03 PM UTC 24
Peak memory 270520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=408827
1734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.
4088271734 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.2269039958
Short name T204
Test name
Test status
Simulation time 466962836 ps
CPU time 15.79 seconds
Started Aug 21 12:59:09 PM UTC 24
Finished Aug 21 12:59:26 PM UTC 24
Peak memory 235732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269039958 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2269039958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.4166854392
Short name T210
Test name
Test status
Simulation time 19629245 ps
CPU time 1.32 seconds
Started Aug 21 01:03:58 PM UTC 24
Finished Aug 21 01:04:00 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4166854392
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.41668
54392 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_app.1162630437
Short name T213
Test name
Test status
Simulation time 21937189454 ps
CPU time 148.19 seconds
Started Aug 21 01:02:05 PM UTC 24
Finished Aug 21 01:04:37 PM UTC 24
Peak memory 268604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11626304
37 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1162630437 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.599795258
Short name T234
Test name
Test status
Simulation time 92759819396 ps
CPU time 458.62 seconds
Started Aug 21 01:02:33 PM UTC 24
Finished Aug 21 01:10:18 PM UTC 24
Peak memory 534844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59979525
8 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac
_app_with_partial_data.599795258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.742549540
Short name T355
Test name
Test status
Simulation time 12785650881 ps
CPU time 1482.18 seconds
Started Aug 21 01:01:55 PM UTC 24
Finished Aug 21 01:26:56 PM UTC 24
Peak memory 256240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74254954
0 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_wri
te.742549540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.2336472375
Short name T81
Test name
Test status
Simulation time 89334883 ps
CPU time 1.73 seconds
Started Aug 21 01:03:39 PM UTC 24
Finished Aug 21 01:03:43 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2336472375 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.233
6472375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3176292666
Short name T208
Test name
Test status
Simulation time 119248700 ps
CPU time 1.71 seconds
Started Aug 21 01:03:43 PM UTC 24
Finished Aug 21 01:03:46 PM UTC 24
Peak memory 227540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3176292666 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3
176292666 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3691932261
Short name T209
Test name
Test status
Simulation time 2070283610 ps
CPU time 12.5 seconds
Started Aug 21 01:03:44 PM UTC 24
Finished Aug 21 01:03:57 PM UTC 24
Peak memory 235556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691932261 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.369193226
1 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2856809664
Short name T84
Test name
Test status
Simulation time 308110116006 ps
CPU time 455.17 seconds
Started Aug 21 01:02:40 PM UTC 24
Finished Aug 21 01:10:21 PM UTC 24
Peak memory 565632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28568096
64 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entr
opy_refresh.2856809664 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_error.3566727232
Short name T255
Test name
Test status
Simulation time 20003313175 ps
CPU time 643.45 seconds
Started Aug 21 01:02:50 PM UTC 24
Finished Aug 21 01:13:43 PM UTC 24
Peak memory 616720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566727232 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3566727232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1060978465
Short name T207
Test name
Test status
Simulation time 634139531 ps
CPU time 9.58 seconds
Started Aug 21 01:03:30 PM UTC 24
Finished Aug 21 01:03:42 PM UTC 24
Peak memory 227512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1060978465 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1060978465 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.1937574062
Short name T39
Test name
Test status
Simulation time 259332318 ps
CPU time 2.41 seconds
Started Aug 21 01:03:47 PM UTC 24
Finished Aug 21 01:03:50 PM UTC 24
Peak memory 231764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937574062 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1937574062 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.3154633244
Short name T251
Test name
Test status
Simulation time 36074357040 ps
CPU time 662.32 seconds
Started Aug 21 01:01:38 PM UTC 24
Finished Aug 21 01:12:50 PM UTC 24
Peak memory 596284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31546
33244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.km
ac_long_msg_and_output.3154633244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.903994170
Short name T225
Test name
Test status
Simulation time 18839364390 ps
CPU time 328.49 seconds
Started Aug 21 01:02:42 PM UTC 24
Finished Aug 21 01:08:15 PM UTC 24
Peak memory 316168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903994170 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.903994170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.3936296428
Short name T233
Test name
Test status
Simulation time 20460558861 ps
CPU time 495.98 seconds
Started Aug 21 01:01:44 PM UTC 24
Finished Aug 21 01:10:08 PM UTC 24
Peak memory 504064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=393629
6428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.
3936296428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.2793380766
Short name T182
Test name
Test status
Simulation time 6867902816 ps
CPU time 108.77 seconds
Started Aug 21 01:01:37 PM UTC 24
Finished Aug 21 01:03:29 PM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2793380766 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2793380766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.2621422889
Short name T70
Test name
Test status
Simulation time 4936249839 ps
CPU time 167.23 seconds
Started Aug 21 01:03:51 PM UTC 24
Finished Aug 21 01:06:41 PM UTC 24
Peak memory 283288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=2621422889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.kmac_stress_all.2621422889 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.1344342956
Short name T219
Test name
Test status
Simulation time 15482212 ps
CPU time 1.26 seconds
Started Aug 21 01:06:42 PM UTC 24
Finished Aug 21 01:06:45 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1344342956
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.13443
42956 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_app.846250056
Short name T231
Test name
Test status
Simulation time 17651502876 ps
CPU time 307.25 seconds
Started Aug 21 01:04:46 PM UTC 24
Finished Aug 21 01:09:58 PM UTC 24
Peak memory 315644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84625005
6 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.846250056 +en
able_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2592465636
Short name T221
Test name
Test status
Simulation time 3422242727 ps
CPU time 111.82 seconds
Started Aug 21 01:04:57 PM UTC 24
Finished Aug 21 01:06:51 PM UTC 24
Peak memory 280888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25924656
36 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kma
c_app_with_partial_data.2592465636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.859170225
Short name T308
Test name
Test status
Simulation time 9446645700 ps
CPU time 982.08 seconds
Started Aug 21 01:04:37 PM UTC 24
Finished Aug 21 01:21:13 PM UTC 24
Peak memory 252148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=85917022
5 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_wri
te.859170225 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2696054237
Short name T220
Test name
Test status
Simulation time 994992857 ps
CPU time 25 seconds
Started Aug 21 01:06:18 PM UTC 24
Finished Aug 21 01:06:45 PM UTC 24
Peak memory 235264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2696054237 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.269
6054237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.1364612837
Short name T217
Test name
Test status
Simulation time 30549472 ps
CPU time 1.33 seconds
Started Aug 21 01:06:28 PM UTC 24
Finished Aug 21 01:06:30 PM UTC 24
Peak memory 224320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1364612837 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1
364612837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.400438751
Short name T223
Test name
Test status
Simulation time 23910709074 ps
CPU time 60.32 seconds
Started Aug 21 01:06:29 PM UTC 24
Finished Aug 21 01:07:31 PM UTC 24
Peak memory 235844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400438751 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.400438751
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.2623297427
Short name T177
Test name
Test status
Simulation time 62617969633 ps
CPU time 280.08 seconds
Started Aug 21 01:04:58 PM UTC 24
Finished Aug 21 01:09:43 PM UTC 24
Peak memory 327968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26232974
27 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entr
opy_refresh.2623297427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_error.4169815227
Short name T153
Test name
Test status
Simulation time 65892163826 ps
CPU time 344.68 seconds
Started Aug 21 01:06:16 PM UTC 24
Finished Aug 21 01:12:06 PM UTC 24
Peak memory 491836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169815227 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4169815227 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.4241620093
Short name T216
Test name
Test status
Simulation time 663642153 ps
CPU time 8.03 seconds
Started Aug 21 01:06:18 PM UTC 24
Finished Aug 21 01:06:28 PM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241620093 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4241620093 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.369263053
Short name T218
Test name
Test status
Simulation time 45343593 ps
CPU time 2.68 seconds
Started Aug 21 01:06:31 PM UTC 24
Finished Aug 21 01:06:35 PM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=369263053 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.369263053 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1410604787
Short name T675
Test name
Test status
Simulation time 179512987501 ps
CPU time 4108.9 seconds
Started Aug 21 01:04:07 PM UTC 24
Finished Aug 21 02:13:20 PM UTC 24
Peak memory 4159892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14106
04787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.km
ac_long_msg_and_output.1410604787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.2922759254
Short name T215
Test name
Test status
Simulation time 2033787743 ps
CPU time 54.95 seconds
Started Aug 21 01:04:13 PM UTC 24
Finished Aug 21 01:05:10 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292275
9254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.
2922759254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.2897978830
Short name T211
Test name
Test status
Simulation time 95766311 ps
CPU time 4.14 seconds
Started Aug 21 01:04:01 PM UTC 24
Finished Aug 21 01:04:07 PM UTC 24
Peak memory 235760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2897978830 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2897978830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.1473060171
Short name T222
Test name
Test status
Simulation time 668756854 ps
CPU time 35.11 seconds
Started Aug 21 01:06:36 PM UTC 24
Finished Aug 21 01:07:13 PM UTC 24
Peak memory 252552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1473060171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.kmac_stress_all.1473060171 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.2760017498
Short name T230
Test name
Test status
Simulation time 23352392 ps
CPU time 1.26 seconds
Started Aug 21 01:09:43 PM UTC 24
Finished Aug 21 01:09:46 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2760017498
-assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.27600
17498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_app.3984018472
Short name T250
Test name
Test status
Simulation time 11731081819 ps
CPU time 319.82 seconds
Started Aug 21 01:07:13 PM UTC 24
Finished Aug 21 01:12:39 PM UTC 24
Peak memory 346364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39840184
72 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.3984018472 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.4279902754
Short name T253
Test name
Test status
Simulation time 5070895845 ps
CPU time 320.42 seconds
Started Aug 21 01:07:32 PM UTC 24
Finished Aug 21 01:12:57 PM UTC 24
Peak memory 332100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42799027
54 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kma
c_app_with_partial_data.4279902754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.3449142427
Short name T143
Test name
Test status
Simulation time 5868066872 ps
CPU time 347.52 seconds
Started Aug 21 01:07:02 PM UTC 24
Finished Aug 21 01:12:55 PM UTC 24
Peak memory 252212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34491424
27 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_wr
ite.3449142427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.10575817
Short name T229
Test name
Test status
Simulation time 501581004 ps
CPU time 45.75 seconds
Started Aug 21 01:08:27 PM UTC 24
Finished Aug 21 01:09:14 PM UTC 24
Peak memory 235664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10575817 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.10575
817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3796662723
Short name T228
Test name
Test status
Simulation time 134033643 ps
CPU time 1.5 seconds
Started Aug 21 01:08:39 PM UTC 24
Finished Aug 21 01:08:42 PM UTC 24
Peak memory 224320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3796662723 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3
796662723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.4200822764
Short name T235
Test name
Test status
Simulation time 97296415400 ps
CPU time 112.53 seconds
Started Aug 21 01:08:42 PM UTC 24
Finished Aug 21 01:10:37 PM UTC 24
Peak memory 235756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4200822764 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.420082276
4 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.453257983
Short name T89
Test name
Test status
Simulation time 6199963713 ps
CPU time 22.64 seconds
Started Aug 21 01:07:33 PM UTC 24
Finished Aug 21 01:07:58 PM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45325798
3 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entro
py_refresh.453257983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_error.2112214252
Short name T276
Test name
Test status
Simulation time 30242243116 ps
CPU time 441.07 seconds
Started Aug 21 01:07:59 PM UTC 24
Finished Aug 21 01:15:26 PM UTC 24
Peak memory 571828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2112214252 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2112214252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.3518838274
Short name T227
Test name
Test status
Simulation time 6951091286 ps
CPU time 21.33 seconds
Started Aug 21 01:08:16 PM UTC 24
Finished Aug 21 01:08:39 PM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518838274 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3518838274 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.3471949353
Short name T95
Test name
Test status
Simulation time 79071083 ps
CPU time 2.03 seconds
Started Aug 21 01:09:15 PM UTC 24
Finished Aug 21 01:09:19 PM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3471949353 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3471949353 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.434970771
Short name T487
Test name
Test status
Simulation time 221484189690 ps
CPU time 2287.38 seconds
Started Aug 21 01:06:46 PM UTC 24
Finished Aug 21 01:45:21 PM UTC 24
Peak memory 2478464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43497
0771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kma
c_long_msg_and_output.434970771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.1644892706
Short name T163
Test name
Test status
Simulation time 9898175415 ps
CPU time 196.44 seconds
Started Aug 21 01:07:47 PM UTC 24
Finished Aug 21 01:11:07 PM UTC 24
Peak memory 334464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1644892706 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1644892706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.1598563594
Short name T242
Test name
Test status
Simulation time 12178758579 ps
CPU time 266.04 seconds
Started Aug 21 01:06:52 PM UTC 24
Finished Aug 21 01:11:22 PM UTC 24
Peak memory 317752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=159856
3594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.
1598563594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2165163831
Short name T224
Test name
Test status
Simulation time 12558852416 ps
CPU time 44.94 seconds
Started Aug 21 01:06:45 PM UTC 24
Finished Aug 21 01:07:32 PM UTC 24
Peak memory 234068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165163831 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2165163831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.1306788788
Short name T315
Test name
Test status
Simulation time 150414964787 ps
CPU time 778.46 seconds
Started Aug 21 01:09:19 PM UTC 24
Finished Aug 21 01:22:29 PM UTC 24
Peak memory 416072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir
=/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10
000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim
.tcl +ntb_random_seed=1306788788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.kmac_stress_all.1306788788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.941086307
Short name T239
Test name
Test status
Simulation time 37093010 ps
CPU time 1.16 seconds
Started Aug 21 01:11:08 PM UTC 24
Finished Aug 21 01:11:10 PM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941086307 -
assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.941086
307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_app.1156889668
Short name T280
Test name
Test status
Simulation time 36184911179 ps
CPU time 338.36 seconds
Started Aug 21 01:10:01 PM UTC 24
Finished Aug 21 01:15:45 PM UTC 24
Peak memory 432448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11568896
68 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1156889668 +
enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.3494544421
Short name T263
Test name
Test status
Simulation time 8122448559 ps
CPU time 233.68 seconds
Started Aug 21 01:10:09 PM UTC 24
Finished Aug 21 01:14:07 PM UTC 24
Peak memory 379192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34945444
21 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kma
c_app_with_partial_data.3494544421 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.243277700
Short name T145
Test name
Test status
Simulation time 50341375547 ps
CPU time 654.53 seconds
Started Aug 21 01:09:59 PM UTC 24
Finished Aug 21 01:21:02 PM UTC 24
Peak memory 252204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24327770
0 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_wri
te.243277700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.956025833
Short name T240
Test name
Test status
Simulation time 795213063 ps
CPU time 30.74 seconds
Started Aug 21 01:10:38 PM UTC 24
Finished Aug 21 01:11:11 PM UTC 24
Peak memory 245168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=956025833 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.9560
25833 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.1327477433
Short name T237
Test name
Test status
Simulation time 135413379 ps
CPU time 1.7 seconds
Started Aug 21 01:10:52 PM UTC 24
Finished Aug 21 01:10:55 PM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1327477433 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1
327477433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.570754609
Short name T243
Test name
Test status
Simulation time 1999173009 ps
CPU time 33.45 seconds
Started Aug 21 01:10:54 PM UTC 24
Finished Aug 21 01:11:29 PM UTC 24
Peak memory 231832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=570754609 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.570754609
+enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2979447832
Short name T244
Test name
Test status
Simulation time 1899299776 ps
CPU time 83.52 seconds
Started Aug 21 01:10:19 PM UTC 24
Finished Aug 21 01:11:44 PM UTC 24
Peak memory 252100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29794478
32 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entr
opy_refresh.2979447832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_error.1870836257
Short name T152
Test name
Test status
Simulation time 2444949743 ps
CPU time 43.35 seconds
Started Aug 21 01:10:22 PM UTC 24
Finished Aug 21 01:11:07 PM UTC 24
Peak memory 264476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1870836257 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1870836257 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.585093513
Short name T236
Test name
Test status
Simulation time 6357346376 ps
CPU time 18.57 seconds
Started Aug 21 01:10:31 PM UTC 24
Finished Aug 21 01:10:51 PM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585093513 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.585093513 +enable_masking=1 +s
w_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.2671091181
Short name T238
Test name
Test status
Simulation time 135900806 ps
CPU time 1.92 seconds
Started Aug 21 01:10:56 PM UTC 24
Finished Aug 21 01:10:59 PM UTC 24
Peak memory 231372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2671091181 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2671091181 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.2384303588
Short name T413
Test name
Test status
Simulation time 28776641036 ps
CPU time 1536.38 seconds
Started Aug 21 01:09:47 PM UTC 24
Finished Aug 21 01:35:43 PM UTC 24
Peak memory 1007864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23843
03588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.km
ac_long_msg_and_output.2384303588 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.548020361
Short name T277
Test name
Test status
Simulation time 9514983884 ps
CPU time 303.61 seconds
Started Aug 21 01:10:21 PM UTC 24
Finished Aug 21 01:15:29 PM UTC 24
Peak memory 410320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=548020361 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.548020361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.844662701
Short name T248
Test name
Test status
Simulation time 18431458084 ps
CPU time 152.08 seconds
Started Aug 21 01:09:48 PM UTC 24
Finished Aug 21 01:12:24 PM UTC 24
Peak memory 321856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844662
701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.8
44662701 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.2468794236
Short name T232
Test name
Test status
Simulation time 3026928325 ps
CPU time 14.28 seconds
Started Aug 21 01:09:44 PM UTC 24
Finished Aug 21 01:10:00 PM UTC 24
Peak memory 231924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2468794236 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2468794236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all_with_rand_reset.2165189891
Short name T77
Test name
Test status
Simulation time 17789681971 ps
CPU time 139.25 seconds
Started Aug 21 01:11:08 PM UTC 24
Finished Aug 21 01:13:30 PM UTC 24
Peak memory 281332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10
000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/
lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165189891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.2165189891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest
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