Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14724284	1			T1	453		T2	1009		T3	93
all_values[1]	14724284	1			T1	453		T2	1009		T3	93
all_values[2]	14724284	1			T1	453		T2	1009		T3	93

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

546826

1

T2

18

T3

194

T28

12

auto[1]

43626026

1

T1

1359

T2

3009

T3

85

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43956735

1

T1

1188

T2

2694

T3

267

auto[1]

216117

1

T1

171

T2

333

T3

12

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	172932	1			T3	6		T11	1		T45	6
all_values[0]	auto[0]	auto[1]	1408	1			T3	2		T45	6		T13	6
all_values[0]	auto[1]	auto[0]	14479313	1			T1	396		T2	898		T3	83
all_values[0]	auto[1]	auto[1]	70631	1			T1	57		T2	111		T3	2
all_values[1]	auto[0]	auto[0]	190565	1			T2	2		T3	89		T28	5
all_values[1]	auto[0]	auto[1]	1012	1			T2	1		T3	4		T28	1
all_values[1]	auto[1]	auto[0]	14461680	1			T1	396		T2	896		T28	71
all_values[1]	auto[1]	auto[1]	71027	1			T1	57		T2	110		T28	4
all_values[2]	auto[0]	auto[0]	179808	1			T2	11		T3	89		T28	5
all_values[2]	auto[0]	auto[1]	1101	1			T2	4		T3	4		T28	1
all_values[2]	auto[1]	auto[0]	14472437	1			T1	396		T2	887		T28	71
all_values[2]	auto[1]	auto[1]	70938	1			T1	57		T2	107		T28	4