Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14724284	1			T1	453		T2	1009		T3	93
all_pins[1]	14724284	1			T1	453		T2	1009		T3	93
all_pins[2]	14724284	1			T1	453		T2	1009		T3	93

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43750935	1			T1	1302		T2	2916		T3	277
values[0x1]	421917	1			T1	57		T2	111		T3	2
transitions[0x0=>0x1]	419643	1			T1	57		T2	111		T3	2
transitions[0x1=>0x0]	419670	1			T1	57		T2	111		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14653653	1			T1	396		T2	898		T3	91
all_pins[0]	values[0x1]	70631	1			T1	57		T2	111		T3	2
all_pins[0]	transitions[0x0=>0x1]	70619	1			T1	57		T2	111		T3	2
all_pins[0]	transitions[0x1=>0x0]	5568	1			T18	30		T14	40		T47	27
all_pins[1]	values[0x0]	14718704	1			T1	453		T2	1009		T3	93
all_pins[1]	values[0x1]	5580	1			T18	30		T14	40		T47	27
all_pins[1]	transitions[0x0=>0x1]	5364	1			T18	30		T47	27		T94	1
all_pins[1]	transitions[0x1=>0x0]	345490	1			T18	191		T14	18133		T29	12769
all_pins[2]	values[0x0]	14378578	1			T1	453		T2	1009		T3	93
all_pins[2]	values[0x1]	345706	1			T18	191		T14	18173		T29	12769
all_pins[2]	transitions[0x0=>0x1]	343660	1			T18	190		T14	18054		T29	12694
all_pins[2]	transitions[0x1=>0x0]	68612	1			T1	57		T2	111		T3	2