Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T138 7 T140 7 T170 4
all_values[1] 287 1 T138 7 T140 7 T170 4
all_values[2] 287 1 T138 7 T140 7 T170 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T138 14 T140 13 T170 7
auto[1] 389 1 T138 7 T140 8 T170 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 383 1 T138 8 T140 7 T170 4
auto[1] 478 1 T138 13 T140 14 T170 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 492 1 T138 10 T140 9 T170 5
auto[1] 369 1 T138 11 T140 12 T170 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 64 1 T138 3 T140 2 T171 1
all_values[0] auto[0] auto[0] auto[1] 26 1 T168 1 T172 3 T173 2
all_values[0] auto[0] auto[1] auto[0] 41 1 T138 1 T170 2 T171 1
all_values[0] auto[0] auto[1] auto[1] 30 1 T140 1 T168 2 T174 1
all_values[0] auto[1] auto[0] auto[1] 73 1 T140 2 T170 2 T168 1
all_values[0] auto[1] auto[1] auto[1] 53 1 T138 3 T140 2 T168 3
all_values[1] auto[0] auto[0] auto[0] 81 1 T140 1 T170 1 T168 3
all_values[1] auto[0] auto[1] auto[0] 80 1 T138 2 T140 1 T170 1
all_values[1] auto[1] auto[0] auto[1] 73 1 T138 4 T140 4 T170 1
all_values[1] auto[1] auto[1] auto[1] 53 1 T138 1 T140 1 T170 1
all_values[2] auto[0] auto[0] auto[0] 68 1 T138 2 T168 2 T171 1
all_values[2] auto[0] auto[0] auto[1] 24 1 T138 2 T140 1 T168 1
all_values[2] auto[0] auto[1] auto[0] 49 1 T140 3 T168 2 T171 1
all_values[2] auto[0] auto[1] auto[1] 29 1 T170 1 T173 2 T175 1
all_values[2] auto[1] auto[0] auto[1] 63 1 T138 3 T140 3 T170 3
all_values[2] auto[1] auto[1] auto[1] 54 1 T168 1 T171 2 T176 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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