Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15874307	1			T1	3623		T2	999		T3	154
all_values[1]	15874307	1			T1	3623		T2	999		T3	154
all_values[2]	15874307	1			T1	3623		T2	999		T3	154

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

519569

1

T1

212

T2

43

T3

7

auto[1]

47103352

1

T1

10657

T2

2954

T3

455

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47410059

1

T1

10779

T2

2673

T3

450

auto[1]

212862

1

T1

90

T2

324

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	176414	1			T1	210		T3	5		T41	3
all_values[0]	auto[0]	auto[1]	1320	1			T1	2		T3	2		T41	4
all_values[0]	auto[1]	auto[0]	15626939	1			T1	3383		T2	891		T3	145
all_values[0]	auto[1]	auto[1]	69634	1			T1	28		T2	108		T3	2
all_values[1]	auto[0]	auto[0]	196510	1			T2	25		T10	1		T4	3
all_values[1]	auto[0]	auto[1]	1056	1			T2	11		T46	2		T81	4
all_values[1]	auto[1]	auto[0]	15606843	1			T1	3593		T2	866		T3	150
all_values[1]	auto[1]	auto[1]	69898	1			T1	30		T2	97		T3	4
all_values[2]	auto[0]	auto[0]	143257	1			T2	4		T41	3		T29	18
all_values[2]	auto[0]	auto[1]	1012	1			T2	3		T41	4		T29	3
all_values[2]	auto[1]	auto[0]	15660096	1			T1	3593		T2	887		T3	150
all_values[2]	auto[1]	auto[1]	69942	1			T1	30		T2	105		T3	4