Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15874307	1			T1	3623		T2	999		T3	154
all_pins[1]	15874307	1			T1	3623		T2	999		T3	154
all_pins[2]	15874307	1			T1	3623		T2	999		T3	154

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47259459	1			T1	10841		T2	2889		T3	460
values[0x1]	363462	1			T1	28		T2	108		T3	2
transitions[0x0=>0x1]	361536	1			T1	28		T2	108		T3	2
transitions[0x1=>0x0]	361566	1			T1	28		T2	108		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15804673	1			T1	3595		T2	891		T3	152
all_pins[0]	values[0x1]	69634	1			T1	28		T2	108		T3	2
all_pins[0]	transitions[0x0=>0x1]	69625	1			T1	28		T2	108		T3	2
all_pins[0]	transitions[0x1=>0x0]	5261	1			T9	1		T12	23		T31	9
all_pins[1]	values[0x0]	15869037	1			T1	3623		T2	999		T3	154
all_pins[1]	values[0x1]	5270	1			T9	1		T12	23		T31	9
all_pins[1]	transitions[0x0=>0x1]	5064	1			T12	23		T31	8		T77	1
all_pins[1]	transitions[0x1=>0x0]	288352	1			T9	1400		T31	147		T32	97
all_pins[2]	values[0x0]	15585749	1			T1	3623		T2	999		T3	154
all_pins[2]	values[0x1]	288558	1			T9	1401		T31	148		T32	97
all_pins[2]	transitions[0x0=>0x1]	286847	1			T9	1393		T31	148		T32	95
all_pins[2]	transitions[0x1=>0x0]	67953	1			T1	28		T2	108		T3	2