Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	598	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5367	1			T1	6		T49	1		T9	2
len_601_800	12453	1			T1	8		T49	1		T9	4
len_401_600	8039	1			T1	1		T9	1		T11	15
len_201_400	4011	1			T1	1		T11	6		T12	10
len_65_200	6373	1			T1	1		T29	61		T50	110
len_min_for_xof_require_squeeze	66	1			T28	1		T186	1		T187	1
len_keccak_block_sizes[72]	72	1			T50	1		T142	2		T32	1
len_keccak_block_sizes[104]	63	1			T29	1		T50	2		T186	1
len_keccak_block_sizes[136]	46	1			T29	2		T50	3		T188	9
len_keccak_block_sizes[144]	28	1			T29	1		T189	5		T190	1
len_keccak_block_sizes[168]	40	1			T50	1		T142	1		T191	1
len_datapath_width	1019	1			T2	73		T3	3		T29	7
len_2_63	14031	1			T1	2		T41	145		T29	59
len_1	61	1			T50	1		T192	1		T193	4