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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.24 97.91 92.62 99.89 76.76 95.59 99.05 97.88


Total test records in report: 881
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T760 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3272592458 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:02 AM UTC 24 42529074 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2407473394 Aug 25 07:51:38 AM UTC 24 Aug 25 07:52:03 AM UTC 24 6823626626 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1369281488 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:03 AM UTC 24 87088030 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1661337537 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:04 AM UTC 24 37627922 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3458545960 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:04 AM UTC 24 113994406 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3465399376 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:04 AM UTC 24 39337918 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.999193139 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:14 AM UTC 24 142470593 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.160613295 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:04 AM UTC 24 81990226 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4039240638 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:04 AM UTC 24 61337858 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3079444839 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:04 AM UTC 24 50407081 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3194865891 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:04 AM UTC 24 44023362 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4247369839 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 31501514 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2082816025 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 217339721 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1475028052 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 67878177 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2540694383 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:05 AM UTC 24 287055012 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.38927629 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 94717404 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1467593447 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 47329256 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4226504570 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 293859235 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3165234165 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:05 AM UTC 24 84561974 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2172204011 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:06 AM UTC 24 56633872 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2348009253 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:06 AM UTC 24 77189467 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.167272971 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:14 AM UTC 24 91732655 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.812200810 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:06 AM UTC 24 215895798 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.514312875 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:06 AM UTC 24 138391552 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2735678686 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:06 AM UTC 24 99187902 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.4047554552 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:06 AM UTC 24 108988075 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1087861502 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:06 AM UTC 24 439554940 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3050655007 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:06 AM UTC 24 55809671 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3017892728 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:07 AM UTC 24 60386002 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3772530794 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:07 AM UTC 24 88968111 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3553999148 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:07 AM UTC 24 122841425 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2753804636 Aug 25 07:52:04 AM UTC 24 Aug 25 07:52:07 AM UTC 24 44412988 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1765599434 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:07 AM UTC 24 554564975 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4291632844 Aug 25 07:52:02 AM UTC 24 Aug 25 07:52:07 AM UTC 24 60125158 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3660581358 Aug 25 07:52:04 AM UTC 24 Aug 25 07:52:07 AM UTC 24 32498640 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2400886675 Aug 25 07:51:59 AM UTC 24 Aug 25 07:52:07 AM UTC 24 753214180 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.266640210 Aug 25 07:52:04 AM UTC 24 Aug 25 07:52:07 AM UTC 24 45061617 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2034606935 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:07 AM UTC 24 16541769 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1841159161 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:08 AM UTC 24 161959121 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.907644026 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:08 AM UTC 24 443187187 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2211526792 Aug 25 07:52:04 AM UTC 24 Aug 25 07:52:08 AM UTC 24 60517210 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2433900302 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:08 AM UTC 24 41827947 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2956672753 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:08 AM UTC 24 44636614 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.204420767 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:09 AM UTC 24 194189352 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.704765516 Aug 25 07:52:06 AM UTC 24 Aug 25 07:52:09 AM UTC 24 12043608 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3538149339 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:09 AM UTC 24 16089091 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2831646227 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:09 AM UTC 24 74761405 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.596406759 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:10 AM UTC 24 22084553 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1299721353 Aug 25 07:52:01 AM UTC 24 Aug 25 07:52:10 AM UTC 24 775523741 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1833782431 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:10 AM UTC 24 44930244 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4061722286 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:10 AM UTC 24 186863144 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3971958720 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:10 AM UTC 24 85707606 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1755333531 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:10 AM UTC 24 426026131 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1223301428 Aug 25 07:52:04 AM UTC 24 Aug 25 07:52:11 AM UTC 24 484244812 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3574303849 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:11 AM UTC 24 190301557 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2496270357 Aug 25 07:52:05 AM UTC 24 Aug 25 07:52:11 AM UTC 24 122614255 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.392833439 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:11 AM UTC 24 288072217 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3535206612 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:14 AM UTC 24 40085119 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3771467605 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:11 AM UTC 24 48013983 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2702286068 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:14 AM UTC 24 150276200 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3205281395 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:12 AM UTC 24 112638218 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3945534316 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:12 AM UTC 24 48219692 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1870738850 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:12 AM UTC 24 23553756 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3380400043 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:12 AM UTC 24 31448432 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1630996214 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:12 AM UTC 24 70434489 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1796577320 Aug 25 07:52:07 AM UTC 24 Aug 25 07:52:12 AM UTC 24 98644349 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.644379288 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:15 AM UTC 24 585838751 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.620343574 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:12 AM UTC 24 106158916 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2680710938 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:12 AM UTC 24 54561568 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1343302298 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:13 AM UTC 24 35892377 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2966397435 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:13 AM UTC 24 57553352 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1466559220 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:13 AM UTC 24 26913658 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3125664593 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:13 AM UTC 24 74188352 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3599314140 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:13 AM UTC 24 77107288 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3306633963 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:13 AM UTC 24 327644564 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2502625020 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:13 AM UTC 24 20153653 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.361438482 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:14 AM UTC 24 117466626 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4100936637 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:13 AM UTC 24 296587156 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4207194414 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:14 AM UTC 24 386673800 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2701804807 Aug 25 07:52:08 AM UTC 24 Aug 25 07:52:14 AM UTC 24 120336688 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2817433635 Aug 25 07:52:11 AM UTC 24 Aug 25 07:52:14 AM UTC 24 170194361 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3077737922 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:14 AM UTC 24 136008893 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.4087807897 Aug 25 07:52:09 AM UTC 24 Aug 25 07:52:14 AM UTC 24 249970847 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2777251554 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:15 AM UTC 24 160303178 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3679767086 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:15 AM UTC 24 32536722 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2530095780 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:15 AM UTC 24 75810780 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.752374325 Aug 25 07:52:11 AM UTC 24 Aug 25 07:52:15 AM UTC 24 70790312 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3193658507 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:15 AM UTC 24 414363976 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.247628466 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 27038390 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.442615391 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 19758788 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1890480726 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 13863286 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2055782450 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 26253955 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1506117560 Aug 25 07:52:11 AM UTC 24 Aug 25 07:52:16 AM UTC 24 263480782 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3010311375 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 44690988 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3158047149 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:16 AM UTC 24 34123372 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2637279995 Aug 25 07:52:11 AM UTC 24 Aug 25 07:52:17 AM UTC 24 365253148 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3850215232 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:17 AM UTC 24 446780341 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1824411562 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:17 AM UTC 24 126057663 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1735694839 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 19321210 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.728251486 Aug 25 07:52:14 AM UTC 24 Aug 25 07:52:17 AM UTC 24 35968594 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1217877630 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 179899920 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2288986241 Aug 25 07:52:14 AM UTC 24 Aug 25 07:52:17 AM UTC 24 23991472 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.467431801 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 28383329 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.720407129 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 13076990 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.1621068931 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 30646088 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2107906761 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 17832429 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2927910721 Aug 25 07:52:12 AM UTC 24 Aug 25 07:52:17 AM UTC 24 592111093 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1565431717 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 13979432 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3113296276 Aug 25 07:52:15 AM UTC 24 Aug 25 07:52:17 AM UTC 24 20308054 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.645679728 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:18 AM UTC 24 226482944 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.454408981 Aug 25 07:52:10 AM UTC 24 Aug 25 07:52:18 AM UTC 24 179723079 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4061026891 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:18 AM UTC 24 251602445 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.106703240 Aug 25 07:51:43 AM UTC 24 Aug 25 07:52:19 AM UTC 24 28815317478 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1459968064 Aug 25 07:52:16 AM UTC 24 Aug 25 07:52:19 AM UTC 24 35092577 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.4163292431 Aug 25 07:52:16 AM UTC 24 Aug 25 07:52:19 AM UTC 24 53305147 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2658648508 Aug 25 07:52:16 AM UTC 24 Aug 25 07:52:19 AM UTC 24 11821432 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1539983718 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 26623620 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.937993139 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 16375963 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3016096851 Aug 25 07:52:13 AM UTC 24 Aug 25 07:52:19 AM UTC 24 832575692 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.12771429 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 13400318 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.385036108 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 20832242 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1135263360 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 63585152 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4064401606 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 24916017 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.73640140 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 89481614 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.522659937 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 116407978 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1871159234 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 13428737 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1565851685 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 31835199 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1020629415 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 16255159 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2874082219 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:19 AM UTC 24 29610142 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.577512489 Aug 25 07:52:17 AM UTC 24 Aug 25 07:52:20 AM UTC 24 180739582 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.843357145 Aug 25 07:51:46 AM UTC 24 Aug 25 07:52:28 AM UTC 24 14455294535 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1504409073
Short name T1
Test name
Test status
Simulation time 7225253393 ps
CPU time 84.02 seconds
Started Aug 25 12:47:34 PM UTC 24
Finished Aug 25 12:49:00 PM UTC 24
Peak memory 278976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504409073 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1504409073 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1693921431
Short name T12
Test name
Test status
Simulation time 4085797191 ps
CPU time 278.18 seconds
Started Aug 25 12:49:17 PM UTC 24
Finished Aug 25 12:53:59 PM UTC 24
Peak memory 301420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693921431 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1693921431 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3187551961
Short name T127
Test name
Test status
Simulation time 484440180 ps
CPU time 4.74 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 225484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187551961 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3187551961 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1160124226
Short name T15
Test name
Test status
Simulation time 9321415893 ps
CPU time 71.69 seconds
Started Aug 25 12:50:16 PM UTC 24
Finished Aug 25 12:51:30 PM UTC 24
Peak memory 278036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160124226 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1160124226 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.3608148797
Short name T31
Test name
Test status
Simulation time 7644640653 ps
CPU time 224.93 seconds
Started Aug 25 12:50:16 PM UTC 24
Finished Aug 25 12:54:06 PM UTC 24
Peak memory 297792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3608148797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r
and_reset.3608148797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.3844407848
Short name T7
Test name
Test status
Simulation time 1679542602 ps
CPU time 19.74 seconds
Started Aug 25 12:49:48 PM UTC 24
Finished Aug 25 12:50:09 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844407848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3844407848 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.679524911
Short name T16
Test name
Test status
Simulation time 95704949 ps
CPU time 2.16 seconds
Started Aug 25 12:53:43 PM UTC 24
Finished Aug 25 12:53:47 PM UTC 24
Peak memory 234000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679524911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.679524911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_error.1949042456
Short name T25
Test name
Test status
Simulation time 13878837589 ps
CPU time 672.24 seconds
Started Aug 25 01:01:05 PM UTC 24
Finished Aug 25 01:12:28 PM UTC 24
Peak memory 598328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949042456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1949042456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3212485284
Short name T100
Test name
Test status
Simulation time 45795176 ps
CPU time 2.12 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212485284 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3212485284 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.4271563634
Short name T4
Test name
Test status
Simulation time 27954882854 ps
CPU time 36.36 seconds
Started Aug 25 12:50:11 PM UTC 24
Finished Aug 25 12:50:48 PM UTC 24
Peak memory 235816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271563634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.4271563634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.4227555808
Short name T66
Test name
Test status
Simulation time 48250745 ps
CPU time 2.52 seconds
Started Aug 25 01:01:39 PM UTC 24
Finished Aug 25 01:01:42 PM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227555808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4227555808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.4192099290
Short name T75
Test name
Test status
Simulation time 44175010 ps
CPU time 1.98 seconds
Started Aug 25 12:53:06 PM UTC 24
Finished Aug 25 12:53:09 PM UTC 24
Peak memory 227452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192099290 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.4192099290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.411826830
Short name T130
Test name
Test status
Simulation time 29127732 ps
CPU time 1.24 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:37 AM UTC 24
Peak memory 224704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411826830 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.411826830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.1744520688
Short name T54
Test name
Test status
Simulation time 893044179 ps
CPU time 35.3 seconds
Started Aug 25 01:15:59 PM UTC 24
Finished Aug 25 01:16:37 PM UTC 24
Peak memory 254396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744520688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1744520688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.3166307262
Short name T96
Test name
Test status
Simulation time 66528767 ps
CPU time 1.9 seconds
Started Aug 25 01:10:34 PM UTC 24
Finished Aug 25 01:10:37 PM UTC 24
Peak memory 233348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166307262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3166307262 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.3807239523
Short name T50
Test name
Test status
Simulation time 15767642603 ps
CPU time 152.64 seconds
Started Aug 25 12:50:30 PM UTC 24
Finished Aug 25 12:53:05 PM UTC 24
Peak memory 237880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807239523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3807239523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2352440097
Short name T258
Test name
Test status
Simulation time 33445181 ps
CPU time 1.82 seconds
Started Aug 25 01:07:53 PM UTC 24
Finished Aug 25 01:07:55 PM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352440097 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2352440097 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.1462010707
Short name T59
Test name
Test status
Simulation time 96701353 ps
CPU time 1.79 seconds
Started Aug 25 01:17:08 PM UTC 24
Finished Aug 25 01:17:11 PM UTC 24
Peak memory 231360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462010707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1462010707 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.806583253
Short name T154
Test name
Test status
Simulation time 25332250831 ps
CPU time 1467.25 seconds
Started Aug 25 12:53:47 PM UTC 24
Finished Aug 25 01:18:35 PM UTC 24
Peak memory 516732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806583253 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.806583253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.4051877056
Short name T170
Test name
Test status
Simulation time 2446147477 ps
CPU time 4.04 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:51 AM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051877056 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.4051877056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1006708043
Short name T101
Test name
Test status
Simulation time 235816709 ps
CPU time 3.55 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006708043 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.1006
708043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.811755975
Short name T144
Test name
Test status
Simulation time 119542144 ps
CPU time 2 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811755975 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.811755975 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2003317904
Short name T10
Test name
Test status
Simulation time 44475706 ps
CPU time 2.68 seconds
Started Aug 25 12:50:11 PM UTC 24
Finished Aug 25 12:50:14 PM UTC 24
Peak memory 233808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003317904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2003317904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.4235261618
Short name T64
Test name
Test status
Simulation time 142916773 ps
CPU time 2.71 seconds
Started Aug 25 01:13:05 PM UTC 24
Finished Aug 25 01:13:09 PM UTC 24
Peak memory 233864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235261618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.4235261618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.2173334580
Short name T44
Test name
Test status
Simulation time 265390812 ps
CPU time 1.28 seconds
Started Aug 25 12:50:26 PM UTC 24
Finished Aug 25 12:50:29 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173334580 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2173334580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.3295960300
Short name T9
Test name
Test status
Simulation time 436339298 ps
CPU time 40.78 seconds
Started Aug 25 12:52:09 PM UTC 24
Finished Aug 25 12:52:52 PM UTC 24
Peak memory 236168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295960300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3295960300 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.2223946396
Short name T41
Test name
Test status
Simulation time 7094909355 ps
CPU time 94.35 seconds
Started Aug 25 12:47:35 PM UTC 24
Finished Aug 25 12:49:12 PM UTC 24
Peak memory 235184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223946396 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2223946396 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1467593447
Short name T774
Test name
Test status
Simulation time 47329256 ps
CPU time 1.25 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 224444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467593447 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1467593447 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.86098108
Short name T89
Test name
Test status
Simulation time 13286069061 ps
CPU time 408.89 seconds
Started Aug 25 01:14:38 PM UTC 24
Finished Aug 25 01:21:34 PM UTC 24
Peak memory 450880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86098108 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.86098108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.1516643919
Short name T111
Test name
Test status
Simulation time 42510092 ps
CPU time 1.53 seconds
Started Aug 25 01:21:53 PM UTC 24
Finished Aug 25 01:21:55 PM UTC 24
Peak memory 224252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516643919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1516643919 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3574303849
Short name T178
Test name
Test status
Simulation time 190301557 ps
CPU time 3.93 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:11 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574303849 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3574303849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2199886407
Short name T314
Test name
Test status
Simulation time 5209505869 ps
CPU time 167.24 seconds
Started Aug 25 01:12:51 PM UTC 24
Finished Aug 25 01:15:41 PM UTC 24
Peak memory 313640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199886407 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2199886407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_app.3738304355
Short name T108
Test name
Test status
Simulation time 7043412145 ps
CPU time 88.71 seconds
Started Aug 25 12:56:55 PM UTC 24
Finished Aug 25 12:58:26 PM UTC 24
Peak memory 272748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738304355 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3738304355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.1573451932
Short name T342
Test name
Test status
Simulation time 5741285695 ps
CPU time 603.22 seconds
Started Aug 25 01:08:11 PM UTC 24
Finished Aug 25 01:18:23 PM UTC 24
Peak memory 383252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573451932 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1573451932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.1757919841
Short name T88
Test name
Test status
Simulation time 6871815077 ps
CPU time 220 seconds
Started Aug 25 01:15:18 PM UTC 24
Finished Aug 25 01:19:01 PM UTC 24
Peak memory 336124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757919841 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1757919841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3194865891
Short name T167
Test name
Test status
Simulation time 44023362 ps
CPU time 1.16 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194865891 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3194865891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1223301428
Short name T175
Test name
Test status
Simulation time 484244812 ps
CPU time 5.45 seconds
Started Aug 25 07:52:04 AM UTC 24
Finished Aug 25 07:52:11 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223301428 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1223301428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3790417062
Short name T105
Test name
Test status
Simulation time 211904127 ps
CPU time 3.29 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 230064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790417062 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3790
417062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.1647293795
Short name T730
Test name
Test status
Simulation time 119482374 ps
CPU time 5.89 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 225484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647293795 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1647293795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.4012046859
Short name T755
Test name
Test status
Simulation time 1941337746 ps
CPU time 15.39 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:54 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012046859 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.4012046859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1232085329
Short name T131
Test name
Test status
Simulation time 47307834 ps
CPU time 1.54 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:38 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232085329 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1232085329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2952381968
Short name T134
Test name
Test status
Simulation time 51305010 ps
CPU time 2.4 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 227608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2952381968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_
rw_with_rand_reset.2952381968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.1629280556
Short name T181
Test name
Test status
Simulation time 20257676 ps
CPU time 1.49 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:37 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629280556 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1629280556 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.3472869115
Short name T143
Test name
Test status
Simulation time 162054403 ps
CPU time 2.24 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:38 AM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472869115 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.3472869115 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.1784309120
Short name T720
Test name
Test status
Simulation time 16951730 ps
CPU time 1.07 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:37 AM UTC 24
Peak memory 224980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784309120 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1784309120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3371008234
Short name T723
Test name
Test status
Simulation time 25614806 ps
CPU time 2.02 seconds
Started Aug 25 07:51:37 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371008234 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.3371008234 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2582278105
Short name T98
Test name
Test status
Simulation time 101020420 ps
CPU time 1.62 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:37 AM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582278105 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2582278105 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.732316614
Short name T99
Test name
Test status
Simulation time 54204734 ps
CPU time 3 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:39 AM UTC 24
Peak memory 230136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732316614 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.73231
6614 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2758520821
Short name T133
Test name
Test status
Simulation time 493305273 ps
CPU time 5.28 seconds
Started Aug 25 07:51:34 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758520821 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2758520821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.4228078798
Short name T737
Test name
Test status
Simulation time 221933063 ps
CPU time 8.12 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228078798 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.4228078798 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2407473394
Short name T761
Test name
Test status
Simulation time 6823626626 ps
CPU time 23.36 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:52:03 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407473394 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2407473394 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.3250449607
Short name T722
Test name
Test status
Simulation time 18114331 ps
CPU time 1.35 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250449607 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3250449607 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3475104014
Short name T136
Test name
Test status
Simulation time 65346499 ps
CPU time 2.82 seconds
Started Aug 25 07:51:39 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3475104014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_
rw_with_rand_reset.3475104014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2769641486
Short name T182
Test name
Test status
Simulation time 30878597 ps
CPU time 1.45 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:41 AM UTC 24
Peak memory 223136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769641486 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2769641486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.787306834
Short name T132
Test name
Test status
Simulation time 51905032 ps
CPU time 1.06 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:40 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787306834 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.787306834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1006070574
Short name T721
Test name
Test status
Simulation time 17885926 ps
CPU time 1.05 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:40 AM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006070574 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1006070574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3252347104
Short name T724
Test name
Test status
Simulation time 27282484 ps
CPU time 2.15 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252347104 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3252347104 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2015725542
Short name T135
Test name
Test status
Simulation time 127722662 ps
CPU time 3.2 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015725542 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2015725542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2421956355
Short name T129
Test name
Test status
Simulation time 471706029 ps
CPU time 6.1 seconds
Started Aug 25 07:51:38 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 224820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421956355 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2421956355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.4291632844
Short name T789
Test name
Test status
Simulation time 60125158 ps
CPU time 3.37 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4291632844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem
_rw_with_rand_reset.4291632844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1475028052
Short name T772
Test name
Test status
Simulation time 67878177 ps
CPU time 1.42 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475028052 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1475028052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3165234165
Short name T776
Test name
Test status
Simulation time 84561974 ps
CPU time 2.03 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165234165 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3165234165 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4247369839
Short name T770
Test name
Test status
Simulation time 31501514 ps
CPU time 1.51 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 224220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247369839 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.4247369839 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.4226504570
Short name T775
Test name
Test status
Simulation time 293859235 ps
CPU time 2.14 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 225848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226504570 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.422
6504570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.3772530794
Short name T785
Test name
Test status
Simulation time 88968111 ps
CPU time 3.33 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772530794 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3772530794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.4047554552
Short name T180
Test name
Test status
Simulation time 108988075 ps
CPU time 2.85 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047554552 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.4047554552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.266640210
Short name T791
Test name
Test status
Simulation time 45061617 ps
CPU time 2.44 seconds
Started Aug 25 07:52:04 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 229652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=266640210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_
rw_with_rand_reset.266640210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2348009253
Short name T778
Test name
Test status
Simulation time 77189467 ps
CPU time 1.74 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 224288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348009253 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2348009253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3017892728
Short name T784
Test name
Test status
Simulation time 60386002 ps
CPU time 2.6 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017892728 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3017892728 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2172204011
Short name T777
Test name
Test status
Simulation time 56633872 ps
CPU time 1.96 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172204011 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.2172204011 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1765599434
Short name T788
Test name
Test status
Simulation time 554564975 ps
CPU time 3.08 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765599434 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.176
5599434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3553999148
Short name T786
Test name
Test status
Simulation time 122841425 ps
CPU time 2.89 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 225376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553999148 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3553999148 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3050655007
Short name T172
Test name
Test status
Simulation time 55809671 ps
CPU time 2.53 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050655007 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3050655007 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2433900302
Short name T796
Test name
Test status
Simulation time 41827947 ps
CPU time 1.74 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:08 AM UTC 24
Peak memory 226616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2433900302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem
_rw_with_rand_reset.2433900302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1841159161
Short name T793
Test name
Test status
Simulation time 161959121 ps
CPU time 1.34 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:08 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841159161 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1841159161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2034606935
Short name T792
Test name
Test status
Simulation time 16541769 ps
CPU time 1.18 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034606935 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2034606935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.204420767
Short name T798
Test name
Test status
Simulation time 194189352 ps
CPU time 2.16 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:09 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204420767 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.204420767 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2753804636
Short name T787
Test name
Test status
Simulation time 44412988 ps
CPU time 1.83 seconds
Started Aug 25 07:52:04 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753804636 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2753804636 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3660581358
Short name T790
Test name
Test status
Simulation time 32498640 ps
CPU time 2.21 seconds
Started Aug 25 07:52:04 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 225584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660581358 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.366
0581358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2211526792
Short name T795
Test name
Test status
Simulation time 60517210 ps
CPU time 2.92 seconds
Started Aug 25 07:52:04 AM UTC 24
Finished Aug 25 07:52:08 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211526792 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2211526792 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.392833439
Short name T808
Test name
Test status
Simulation time 288072217 ps
CPU time 2.44 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:11 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=392833439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_
rw_with_rand_reset.392833439 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3538149339
Short name T800
Test name
Test status
Simulation time 16089091 ps
CPU time 1.65 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:09 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538149339 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3538149339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.704765516
Short name T799
Test name
Test status
Simulation time 12043608 ps
CPU time 1.15 seconds
Started Aug 25 07:52:06 AM UTC 24
Finished Aug 25 07:52:09 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704765516 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.704765516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1755333531
Short name T806
Test name
Test status
Simulation time 426026131 ps
CPU time 2.56 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755333531 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1755333531 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2956672753
Short name T797
Test name
Test status
Simulation time 44636614 ps
CPU time 1.79 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:08 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956672753 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.2956672753 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4061722286
Short name T804
Test name
Test status
Simulation time 186863144 ps
CPU time 3.87 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061722286 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.406
1722286 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2496270357
Short name T807
Test name
Test status
Simulation time 122614255 ps
CPU time 4.01 seconds
Started Aug 25 07:52:05 AM UTC 24
Finished Aug 25 07:52:11 AM UTC 24
Peak memory 225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496270357 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2496270357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1630996214
Short name T816
Test name
Test status
Simulation time 70434489 ps
CPU time 3.52 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 231832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1630996214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem
_rw_with_rand_reset.1630996214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1833782431
Short name T803
Test name
Test status
Simulation time 44930244 ps
CPU time 1.26 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 224504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833782431 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1833782431 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.596406759
Short name T802
Test name
Test status
Simulation time 22084553 ps
CPU time 1.17 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596406759 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.596406759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3971958720
Short name T805
Test name
Test status
Simulation time 85707606 ps
CPU time 1.92 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 224344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971958720 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3971958720 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2831646227
Short name T801
Test name
Test status
Simulation time 74761405 ps
CPU time 1.38 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:09 AM UTC 24
Peak memory 224220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831646227 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2831646227 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1796577320
Short name T817
Test name
Test status
Simulation time 98644349 ps
CPU time 3.82 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796577320 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.179
6577320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.999193139
Short name T766
Test name
Test status
Simulation time 142470593 ps
CPU time 5.66 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999193139 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.999193139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3205281395
Short name T812
Test name
Test status
Simulation time 112638218 ps
CPU time 3.19 seconds
Started Aug 25 07:52:07 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205281395 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3205281395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.361438482
Short name T828
Test name
Test status
Simulation time 117466626 ps
CPU time 3.87 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=361438482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_
rw_with_rand_reset.361438482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1870738850
Short name T814
Test name
Test status
Simulation time 23553756 ps
CPU time 1.45 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 224444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870738850 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1870738850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3771467605
Short name T810
Test name
Test status
Simulation time 48013983 ps
CPU time 1.13 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:11 AM UTC 24
Peak memory 224964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771467605 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3771467605 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2680710938
Short name T820
Test name
Test status
Simulation time 54561568 ps
CPU time 2.23 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680710938 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.2680710938 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3945534316
Short name T813
Test name
Test status
Simulation time 48219692 ps
CPU time 1.77 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945534316 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3945534316 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2701804807
Short name T831
Test name
Test status
Simulation time 120336688 ps
CPU time 3.83 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701804807 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.270
1804807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3125664593
Short name T824
Test name
Test status
Simulation time 74188352 ps
CPU time 2.88 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125664593 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3125664593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.4207194414
Short name T830
Test name
Test status
Simulation time 386673800 ps
CPU time 3.6 seconds
Started Aug 25 07:52:08 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207194414 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.4207194414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.167272971
Short name T779
Test name
Test status
Simulation time 91732655 ps
CPU time 2.38 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=167272971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_
rw_with_rand_reset.167272971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.620343574
Short name T819
Test name
Test status
Simulation time 106158916 ps
CPU time 1.39 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620343574 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.620343574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3380400043
Short name T815
Test name
Test status
Simulation time 31448432 ps
CPU time 1.12 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:12 AM UTC 24
Peak memory 224288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380400043 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3380400043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3599314140
Short name T825
Test name
Test status
Simulation time 77107288 ps
CPU time 2.11 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599314140 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.3599314140 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2966397435
Short name T822
Test name
Test status
Simulation time 57553352 ps
CPU time 1.91 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966397435 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.2966397435 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1466559220
Short name T823
Test name
Test status
Simulation time 26913658 ps
CPU time 1.94 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466559220 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.146
6559220 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3306633963
Short name T826
Test name
Test status
Simulation time 327644564 ps
CPU time 2.12 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306633963 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3306633963 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.4087807897
Short name T834
Test name
Test status
Simulation time 249970847 ps
CPU time 3.62 seconds
Started Aug 25 07:52:09 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 225316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087807897 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4087807897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1506117560
Short name T844
Test name
Test status
Simulation time 263480782 ps
CPU time 3.25 seconds
Started Aug 25 07:52:11 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1506117560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem
_rw_with_rand_reset.1506117560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.2502625020
Short name T827
Test name
Test status
Simulation time 20153653 ps
CPU time 1.34 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 224560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502625020 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.2502625020 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1343302298
Short name T821
Test name
Test status
Simulation time 35892377 ps
CPU time 0.83 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343302298 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1343302298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2637279995
Short name T847
Test name
Test status
Simulation time 365253148 ps
CPU time 3.92 seconds
Started Aug 25 07:52:11 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637279995 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2637279995 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4100936637
Short name T829
Test name
Test status
Simulation time 296587156 ps
CPU time 1.9 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:13 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100936637 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.4100936637 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3077737922
Short name T833
Test name
Test status
Simulation time 136008893 ps
CPU time 2.81 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 230136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077737922 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.307
7737922 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.454408981
Short name T862
Test name
Test status
Simulation time 179723079 ps
CPU time 5.94 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:18 AM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454408981 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.454408981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.2777251554
Short name T835
Test name
Test status
Simulation time 160303178 ps
CPU time 2.79 seconds
Started Aug 25 07:52:10 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777251554 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2777251554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2530095780
Short name T837
Test name
Test status
Simulation time 75810780 ps
CPU time 1.7 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 228604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2530095780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem
_rw_with_rand_reset.2530095780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.2702286068
Short name T811
Test name
Test status
Simulation time 150276200 ps
CPU time 1.41 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702286068 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2702286068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.3535206612
Short name T809
Test name
Test status
Simulation time 40085119 ps
CPU time 1.17 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 224444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535206612 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3535206612 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3193658507
Short name T839
Test name
Test status
Simulation time 414363976 ps
CPU time 2.13 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 225464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193658507 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3193658507 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2817433635
Short name T832
Test name
Test status
Simulation time 170194361 ps
CPU time 1.46 seconds
Started Aug 25 07:52:11 AM UTC 24
Finished Aug 25 07:52:14 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817433635 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2817433635 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.752374325
Short name T838
Test name
Test status
Simulation time 70790312 ps
CPU time 2.19 seconds
Started Aug 25 07:52:11 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 225516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752374325 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.7523
74325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.644379288
Short name T818
Test name
Test status
Simulation time 585838751 ps
CPU time 2.53 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644379288 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.644379288 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2927910721
Short name T858
Test name
Test status
Simulation time 592111093 ps
CPU time 4.17 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927910721 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2927910721 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4061026891
Short name T863
Test name
Test status
Simulation time 251602445 ps
CPU time 3.59 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:18 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4061026891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem
_rw_with_rand_reset.4061026891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.442615391
Short name T841
Test name
Test status
Simulation time 19758788 ps
CPU time 1.44 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442615391 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.442615391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.247628466
Short name T840
Test name
Test status
Simulation time 27038390 ps
CPU time 1.19 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247628466 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.247628466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.645679728
Short name T861
Test name
Test status
Simulation time 226482944 ps
CPU time 3.18 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:18 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645679728 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.645679728 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3679767086
Short name T836
Test name
Test status
Simulation time 32536722 ps
CPU time 1.65 seconds
Started Aug 25 07:52:12 AM UTC 24
Finished Aug 25 07:52:15 AM UTC 24
Peak memory 224220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679767086 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3679767086 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1824411562
Short name T849
Test name
Test status
Simulation time 126057663 ps
CPU time 2.63 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 225512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824411562 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.182
4411562 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3850215232
Short name T848
Test name
Test status
Simulation time 446780341 ps
CPU time 2.27 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850215232 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3850215232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3016096851
Short name T179
Test name
Test status
Simulation time 832575692 ps
CPU time 4.78 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 225104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016096851 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3016096851 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1401510680
Short name T738
Test name
Test status
Simulation time 2398325593 ps
CPU time 6.94 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:48 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401510680 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1401510680 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.282607256
Short name T758
Test name
Test status
Simulation time 296302503 ps
CPU time 16.74 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:58 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282607256 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.282607256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1389977707
Short name T726
Test name
Test status
Simulation time 80096061 ps
CPU time 1.56 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:43 AM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389977707 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1389977707 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2036561467
Short name T157
Test name
Test status
Simulation time 174092948 ps
CPU time 3.3 seconds
Started Aug 25 07:51:41 AM UTC 24
Finished Aug 25 07:51:46 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2036561467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_
rw_with_rand_reset.2036561467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3923705911
Short name T727
Test name
Test status
Simulation time 18002099 ps
CPU time 1.46 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:43 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923705911 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3923705911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.1567815501
Short name T163
Test name
Test status
Simulation time 48877194 ps
CPU time 1.04 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567815501 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1567815501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.4144125375
Short name T145
Test name
Test status
Simulation time 76397077 ps
CPU time 2.1 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:43 AM UTC 24
Peak memory 225596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144125375 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.4144125375 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2581666709
Short name T725
Test name
Test status
Simulation time 34663983 ps
CPU time 1.11 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581666709 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2581666709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3087292
Short name T729
Test name
Test status
Simulation time 52245701 ps
CPU time 2.43 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 225496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087292 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3087292 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3791037238
Short name T183
Test name
Test status
Simulation time 19700622 ps
CPU time 1.48 seconds
Started Aug 25 07:51:39 AM UTC 24
Finished Aug 25 07:51:42 AM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791037238 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.3791037238 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.4192894302
Short name T141
Test name
Test status
Simulation time 62171989 ps
CPU time 3.01 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192894302 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.4192894302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2068851304
Short name T128
Test name
Test status
Simulation time 221501829 ps
CPU time 2.7 seconds
Started Aug 25 07:51:40 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068851304 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2068851304 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2055782450
Short name T843
Test name
Test status
Simulation time 26253955 ps
CPU time 1.28 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055782450 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2055782450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3158047149
Short name T846
Test name
Test status
Simulation time 34123372 ps
CPU time 1.19 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158047149 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3158047149 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3010311375
Short name T845
Test name
Test status
Simulation time 44690988 ps
CPU time 1.09 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010311375 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3010311375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1890480726
Short name T842
Test name
Test status
Simulation time 13863286 ps
CPU time 0.9 seconds
Started Aug 25 07:52:13 AM UTC 24
Finished Aug 25 07:52:16 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890480726 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1890480726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.728251486
Short name T851
Test name
Test status
Simulation time 35968594 ps
CPU time 1.17 seconds
Started Aug 25 07:52:14 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728251486 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.728251486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2288986241
Short name T853
Test name
Test status
Simulation time 23991472 ps
CPU time 1.08 seconds
Started Aug 25 07:52:14 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288986241 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2288986241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1217877630
Short name T852
Test name
Test status
Simulation time 179899920 ps
CPU time 1.21 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217877630 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1217877630 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.467431801
Short name T854
Test name
Test status
Simulation time 28383329 ps
CPU time 1.09 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467431801 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.467431801 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.1621068931
Short name T856
Test name
Test status
Simulation time 30646088 ps
CPU time 1.17 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621068931 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1621068931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2107906761
Short name T857
Test name
Test status
Simulation time 17832429 ps
CPU time 1.12 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107906761 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2107906761 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2699817706
Short name T753
Test name
Test status
Simulation time 141724714 ps
CPU time 9.51 seconds
Started Aug 25 07:51:43 AM UTC 24
Finished Aug 25 07:51:54 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699817706 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2699817706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.106703240
Short name T864
Test name
Test status
Simulation time 28815317478 ps
CPU time 34.36 seconds
Started Aug 25 07:51:43 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106703240 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.106703240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1042331176
Short name T732
Test name
Test status
Simulation time 48963140 ps
CPU time 1.52 seconds
Started Aug 25 07:51:42 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042331176 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1042331176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2903593567
Short name T740
Test name
Test status
Simulation time 361878349 ps
CPU time 3.78 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 231436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2903593567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_
rw_with_rand_reset.2903593567 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.4032285401
Short name T156
Test name
Test status
Simulation time 184807647 ps
CPU time 1.68 seconds
Started Aug 25 07:51:43 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032285401 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.4032285401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.1555396806
Short name T159
Test name
Test status
Simulation time 95190026 ps
CPU time 0.91 seconds
Started Aug 25 07:51:42 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 224400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555396806 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1555396806 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3465150618
Short name T146
Test name
Test status
Simulation time 68681007 ps
CPU time 1.87 seconds
Started Aug 25 07:51:42 AM UTC 24
Finished Aug 25 07:51:45 AM UTC 24
Peak memory 224480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465150618 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3465150618 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1484318630
Short name T728
Test name
Test status
Simulation time 13655255 ps
CPU time 1.14 seconds
Started Aug 25 07:51:41 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484318630 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1484318630 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4051712284
Short name T733
Test name
Test status
Simulation time 51047138 ps
CPU time 2.25 seconds
Started Aug 25 07:51:43 AM UTC 24
Finished Aug 25 07:51:46 AM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051712284 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.4051712284 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.69882378
Short name T155
Test name
Test status
Simulation time 38110155 ps
CPU time 1.83 seconds
Started Aug 25 07:51:41 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69882378 -assert nopostproc +
UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.69882378 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3214853508
Short name T103
Test name
Test status
Simulation time 36004515 ps
CPU time 1.74 seconds
Started Aug 25 07:51:41 AM UTC 24
Finished Aug 25 07:51:44 AM UTC 24
Peak memory 228588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214853508 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3214
853508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.146064392
Short name T736
Test name
Test status
Simulation time 1972946408 ps
CPU time 3.8 seconds
Started Aug 25 07:51:42 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146064392 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.146064392 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1977775527
Short name T173
Test name
Test status
Simulation time 1667918294 ps
CPU time 6.77 seconds
Started Aug 25 07:51:42 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977775527 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1977775527 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1565431717
Short name T859
Test name
Test status
Simulation time 13979432 ps
CPU time 1.1 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565431717 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1565431717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.1735694839
Short name T850
Test name
Test status
Simulation time 19321210 ps
CPU time 0.99 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735694839 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1735694839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.720407129
Short name T855
Test name
Test status
Simulation time 13076990 ps
CPU time 1.07 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720407129 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.720407129 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3113296276
Short name T860
Test name
Test status
Simulation time 20308054 ps
CPU time 1.2 seconds
Started Aug 25 07:52:15 AM UTC 24
Finished Aug 25 07:52:17 AM UTC 24
Peak memory 224920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113296276 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3113296276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.4163292431
Short name T866
Test name
Test status
Simulation time 53305147 ps
CPU time 1.25 seconds
Started Aug 25 07:52:16 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163292431 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.4163292431 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1459968064
Short name T865
Test name
Test status
Simulation time 35092577 ps
CPU time 1.2 seconds
Started Aug 25 07:52:16 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459968064 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1459968064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2658648508
Short name T867
Test name
Test status
Simulation time 11821432 ps
CPU time 1.18 seconds
Started Aug 25 07:52:16 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658648508 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2658648508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.937993139
Short name T869
Test name
Test status
Simulation time 16375963 ps
CPU time 1.19 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937993139 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.937993139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1539983718
Short name T868
Test name
Test status
Simulation time 26623620 ps
CPU time 1.13 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539983718 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1539983718 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.12771429
Short name T870
Test name
Test status
Simulation time 13400318 ps
CPU time 1.28 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12771429 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.12771429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.596080426
Short name T757
Test name
Test status
Simulation time 1348949883 ps
CPU time 10.83 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:58 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596080426 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.596080426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.843357145
Short name T881
Test name
Test status
Simulation time 14455294535 ps
CPU time 40.47 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:52:28 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843357145 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.843357145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.213231696
Short name T735
Test name
Test status
Simulation time 35230009 ps
CPU time 1.41 seconds
Started Aug 25 07:51:45 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213231696 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.213231696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2179722668
Short name T741
Test name
Test status
Simulation time 71779274 ps
CPU time 2.35 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2179722668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_
rw_with_rand_reset.2179722668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.3510687592
Short name T158
Test name
Test status
Simulation time 24643008 ps
CPU time 1.47 seconds
Started Aug 25 07:51:45 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510687592 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3510687592 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.3828590488
Short name T164
Test name
Test status
Simulation time 104574469 ps
CPU time 1.08 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828590488 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3828590488 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.3752604015
Short name T147
Test name
Test status
Simulation time 212461530 ps
CPU time 1.61 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 224536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752604015 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.3752604015 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.1014301066
Short name T734
Test name
Test status
Simulation time 51111288 ps
CPU time 0.95 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:46 AM UTC 24
Peak memory 223720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014301066 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1014301066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3229333269
Short name T743
Test name
Test status
Simulation time 168057539 ps
CPU time 3.19 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 225472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229333269 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3229333269 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3099699983
Short name T102
Test name
Test status
Simulation time 203817839 ps
CPU time 2.1 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:47 AM UTC 24
Peak memory 226044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099699983 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.3099699983 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3970302585
Short name T125
Test name
Test status
Simulation time 179747869 ps
CPU time 3.25 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 230144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970302585 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.3970
302585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.755245035
Short name T742
Test name
Test status
Simulation time 184624076 ps
CPU time 4.49 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755245035 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.755245035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.820856646
Short name T160
Test name
Test status
Simulation time 158648263 ps
CPU time 4.42 seconds
Started Aug 25 07:51:44 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820856646 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.820856646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.385036108
Short name T871
Test name
Test status
Simulation time 20832242 ps
CPU time 1.11 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385036108 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.385036108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4064401606
Short name T873
Test name
Test status
Simulation time 24916017 ps
CPU time 1.07 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064401606 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4064401606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.1565851685
Short name T877
Test name
Test status
Simulation time 31835199 ps
CPU time 1.24 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565851685 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1565851685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1020629415
Short name T878
Test name
Test status
Simulation time 16255159 ps
CPU time 1.23 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020629415 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1020629415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.1871159234
Short name T876
Test name
Test status
Simulation time 13428737 ps
CPU time 1.12 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 225140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871159234 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1871159234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.73640140
Short name T874
Test name
Test status
Simulation time 89481614 ps
CPU time 1.12 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73640140 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.73640140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.1135263360
Short name T872
Test name
Test status
Simulation time 63585152 ps
CPU time 1.03 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135263360 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1135263360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.2874082219
Short name T879
Test name
Test status
Simulation time 29610142 ps
CPU time 1.09 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874082219 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2874082219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.522659937
Short name T875
Test name
Test status
Simulation time 116407978 ps
CPU time 1 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:19 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522659937 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.522659937 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.577512489
Short name T880
Test name
Test status
Simulation time 180739582 ps
CPU time 1.19 seconds
Started Aug 25 07:52:17 AM UTC 24
Finished Aug 25 07:52:20 AM UTC 24
Peak memory 224220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577512489 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.577512489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1219684857
Short name T745
Test name
Test status
Simulation time 43768950 ps
CPU time 2.33 seconds
Started Aug 25 07:51:47 AM UTC 24
Finished Aug 25 07:51:51 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1219684857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_
rw_with_rand_reset.1219684857 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.427435339
Short name T739
Test name
Test status
Simulation time 32853864 ps
CPU time 1.6 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 224504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427435339 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.427435339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.3184257539
Short name T165
Test name
Test status
Simulation time 23448229 ps
CPU time 1.32 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184257539 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3184257539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.618968592
Short name T749
Test name
Test status
Simulation time 159849780 ps
CPU time 3.12 seconds
Started Aug 25 07:51:47 AM UTC 24
Finished Aug 25 07:51:52 AM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618968592 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.618968592 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.224856006
Short name T104
Test name
Test status
Simulation time 21952383 ps
CPU time 1.71 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:49 AM UTC 24
Peak memory 224568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224856006 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.224856006 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1931013551
Short name T126
Test name
Test status
Simulation time 194270769 ps
CPU time 2.58 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931013551 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.1931
013551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3242077897
Short name T747
Test name
Test status
Simulation time 184313804 ps
CPU time 3.94 seconds
Started Aug 25 07:51:46 AM UTC 24
Finished Aug 25 07:51:51 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242077897 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3242077897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.693603589
Short name T754
Test name
Test status
Simulation time 169690274 ps
CPU time 3.99 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:54 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=693603589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_r
w_with_rand_reset.693603589 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.879341437
Short name T748
Test name
Test status
Simulation time 41573191 ps
CPU time 1.45 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:51 AM UTC 24
Peak memory 224504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879341437 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.879341437 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3479987309
Short name T166
Test name
Test status
Simulation time 18639426 ps
CPU time 1.13 seconds
Started Aug 25 07:51:48 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479987309 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3479987309 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3203676106
Short name T752
Test name
Test status
Simulation time 37430550 ps
CPU time 3.03 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:53 AM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203676106 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.3203676106 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2789765028
Short name T744
Test name
Test status
Simulation time 104078178 ps
CPU time 1.78 seconds
Started Aug 25 07:51:47 AM UTC 24
Finished Aug 25 07:51:50 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789765028 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2789765028 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2080919813
Short name T746
Test name
Test status
Simulation time 266894250 ps
CPU time 2.62 seconds
Started Aug 25 07:51:47 AM UTC 24
Finished Aug 25 07:51:51 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080919813 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.2080
919813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.2945965
Short name T750
Test name
Test status
Simulation time 162419094 ps
CPU time 3.63 seconds
Started Aug 25 07:51:48 AM UTC 24
Finished Aug 25 07:51:52 AM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945965 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/km
ac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2945965 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.941552298
Short name T176
Test name
Test status
Simulation time 806660278 ps
CPU time 6.86 seconds
Started Aug 25 07:51:48 AM UTC 24
Finished Aug 25 07:51:56 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941552298 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.941552298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1369281488
Short name T762
Test name
Test status
Simulation time 87088030 ps
CPU time 3.01 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:03 AM UTC 24
Peak memory 231896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1369281488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_
rw_with_rand_reset.1369281488 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3272592458
Short name T760
Test name
Test status
Simulation time 42529074 ps
CPU time 1.55 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:02 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272592458 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3272592458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.4204331443
Short name T168
Test name
Test status
Simulation time 12690618 ps
CPU time 1.03 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:01 AM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204331443 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.4204331443 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3458545960
Short name T764
Test name
Test status
Simulation time 113994406 ps
CPU time 3.47 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 225536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458545960 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3458545960 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.601825976
Short name T731
Test name
Test status
Simulation time 29923293 ps
CPU time 1.67 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:52 AM UTC 24
Peak memory 224564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601825976 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.601825976 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2284937943
Short name T756
Test name
Test status
Simulation time 116057949 ps
CPU time 3.96 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:54 AM UTC 24
Peak memory 225572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284937943 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.2284
937943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3352654511
Short name T751
Test name
Test status
Simulation time 30460048 ps
CPU time 2.33 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:53 AM UTC 24
Peak memory 225744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352654511 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3352654511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1669170179
Short name T171
Test name
Test status
Simulation time 148566567 ps
CPU time 6.17 seconds
Started Aug 25 07:51:49 AM UTC 24
Finished Aug 25 07:51:56 AM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669170179 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1669170179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2735678686
Short name T782
Test name
Test status
Simulation time 99187902 ps
CPU time 3.67 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 231612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2735678686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_
rw_with_rand_reset.2735678686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.3465399376
Short name T765
Test name
Test status
Simulation time 39337918 ps
CPU time 1.43 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465399376 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3465399376 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1661337537
Short name T763
Test name
Test status
Simulation time 37627922 ps
CPU time 1.16 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661337537 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1661337537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1087861502
Short name T783
Test name
Test status
Simulation time 439554940 ps
CPU time 3.88 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087861502 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.1087861502 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3506230256
Short name T759
Test name
Test status
Simulation time 63178743 ps
CPU time 1.49 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:02 AM UTC 24
Peak memory 224216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506230256 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3506230256 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2540694383
Short name T106
Test name
Test status
Simulation time 287055012 ps
CPU time 4.3 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540694383 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.2540
694383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4039240638
Short name T768
Test name
Test status
Simulation time 61337858 ps
CPU time 3.23 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039240638 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.4039240638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2400886675
Short name T174
Test name
Test status
Simulation time 753214180 ps
CPU time 6.55 seconds
Started Aug 25 07:51:59 AM UTC 24
Finished Aug 25 07:52:07 AM UTC 24
Peak memory 225752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400886675 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.2400886675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.514312875
Short name T781
Test name
Test status
Simulation time 138391552 ps
CPU time 2.93 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=514312875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_r
w_with_rand_reset.514312875 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2082816025
Short name T771
Test name
Test status
Simulation time 217339721 ps
CPU time 1.86 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082816025 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2082816025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3079444839
Short name T769
Test name
Test status
Simulation time 50407081 ps
CPU time 1.23 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079444839 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3079444839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.38927629
Short name T773
Test name
Test status
Simulation time 94717404 ps
CPU time 2.07 seconds
Started Aug 25 07:52:02 AM UTC 24
Finished Aug 25 07:52:05 AM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38927629 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.38927629 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.160613295
Short name T767
Test name
Test status
Simulation time 81990226 ps
CPU time 1.31 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:04 AM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160613295 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.160613295 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.812200810
Short name T780
Test name
Test status
Simulation time 215895798 ps
CPU time 2.99 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:06 AM UTC 24
Peak memory 230072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812200810 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.81220
0810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.907644026
Short name T794
Test name
Test status
Simulation time 443187187 ps
CPU time 5.06 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:08 AM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907644026 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.907644026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1299721353
Short name T177
Test name
Test status
Simulation time 775523741 ps
CPU time 6.63 seconds
Started Aug 25 07:52:01 AM UTC 24
Finished Aug 25 07:52:10 AM UTC 24
Peak memory 225508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299721353 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1299721353 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_app.1904655236
Short name T11
Test name
Test status
Simulation time 6279989661 ps
CPU time 264.46 seconds
Started Aug 25 12:49:13 PM UTC 24
Finished Aug 25 12:53:42 PM UTC 24
Peak memory 352568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904655236 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1904655236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.589144813
Short name T352
Test name
Test status
Simulation time 375731112141 ps
CPU time 1880.59 seconds
Started Aug 25 12:47:35 PM UTC 24
Finished Aug 25 01:19:22 PM UTC 24
Peak memory 268528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589144813 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.589144813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3999212126
Short name T42
Test name
Test status
Simulation time 169744611 ps
CPU time 1.32 seconds
Started Aug 25 12:50:07 PM UTC 24
Finished Aug 25 12:50:10 PM UTC 24
Peak memory 227316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999212126 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3999212126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.63218060
Short name T43
Test name
Test status
Simulation time 14553793 ps
CPU time 1.24 seconds
Started Aug 25 12:50:08 PM UTC 24
Finished Aug 25 12:50:11 PM UTC 24
Peak memory 224852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63218060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +
UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.63218060 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2516448288
Short name T28
Test name
Test status
Simulation time 12986020502 ps
CPU time 544.39 seconds
Started Aug 25 12:49:18 PM UTC 24
Finished Aug 25 12:58:30 PM UTC 24
Peak memory 489720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516448288 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2516448288 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_error.2138810224
Short name T52
Test name
Test status
Simulation time 42787495205 ps
CPU time 558.13 seconds
Started Aug 25 12:49:40 PM UTC 24
Finished Aug 25 12:59:06 PM UTC 24
Peak memory 544992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138810224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2138810224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.4262549000
Short name T184
Test name
Test status
Simulation time 18614478210 ps
CPU time 514.51 seconds
Started Aug 25 12:47:34 PM UTC 24
Finished Aug 25 12:56:17 PM UTC 24
Peak memory 649516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262549000 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.4262549000 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2401514046
Short name T48
Test name
Test status
Simulation time 8507004418 ps
CPU time 386.19 seconds
Started Aug 25 12:49:21 PM UTC 24
Finished Aug 25 12:55:54 PM UTC 24
Peak memory 414412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401514046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2401514046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.1047668491
Short name T29
Test name
Test status
Simulation time 11113585008 ps
CPU time 99.42 seconds
Started Aug 25 12:47:34 PM UTC 24
Finished Aug 25 12:49:16 PM UTC 24
Peak memory 235856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047668491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1047668491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.2840283553
Short name T635
Test name
Test status
Simulation time 252998794718 ps
CPU time 3793.98 seconds
Started Aug 25 12:50:12 PM UTC 24
Finished Aug 25 01:54:17 PM UTC 24
Peak memory 1614664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840283553 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2840283553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.1763022435
Short name T3
Test name
Test status
Simulation time 334227782 ps
CPU time 6.14 seconds
Started Aug 25 12:49:04 PM UTC 24
Finished Aug 25 12:49:11 PM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763022435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.1763022435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.3723529299
Short name T30
Test name
Test status
Simulation time 176173353 ps
CPU time 4.46 seconds
Started Aug 25 12:49:12 PM UTC 24
Finished Aug 25 12:49:17 PM UTC 24
Peak memory 235892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723529299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3723529299 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3636799215
Short name T568
Test name
Test status
Simulation time 60830377053 ps
CPU time 3498.32 seconds
Started Aug 25 12:47:43 PM UTC 24
Finished Aug 25 01:46:47 PM UTC 24
Peak memory 2986028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636799215 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3636799215 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1588298237
Short name T466
Test name
Test status
Simulation time 321336312877 ps
CPU time 2670.42 seconds
Started Aug 25 12:48:22 PM UTC 24
Finished Aug 25 01:33:29 PM UTC 24
Peak memory 2373784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588298237 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1588298237 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3312242075
Short name T2
Test name
Test status
Simulation time 3818701029 ps
CPU time 33.49 seconds
Started Aug 25 12:48:28 PM UTC 24
Finished Aug 25 12:49:03 PM UTC 24
Peak memory 233860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312242075 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3312242075 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3433786231
Short name T188
Test name
Test status
Simulation time 78782114943 ps
CPU time 808.98 seconds
Started Aug 25 12:49:01 PM UTC 24
Finished Aug 25 01:02:41 PM UTC 24
Peak memory 284916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433786231 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3433786231 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.2929618488
Short name T598
Test name
Test status
Simulation time 87181691061 ps
CPU time 3635.13 seconds
Started Aug 25 12:49:01 PM UTC 24
Finished Aug 25 01:50:28 PM UTC 24
Peak memory 2926848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929618488 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.2929618488 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.4234805399
Short name T76
Test name
Test status
Simulation time 52527512 ps
CPU time 1.36 seconds
Started Aug 25 12:54:01 PM UTC 24
Finished Aug 25 12:54:03 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234805399 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.4234805399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_app.1167844514
Short name T107
Test name
Test status
Simulation time 4268862431 ps
CPU time 372.94 seconds
Started Aug 25 12:52:01 PM UTC 24
Finished Aug 25 12:58:21 PM UTC 24
Peak memory 323912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167844514 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1167844514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.4018045441
Short name T49
Test name
Test status
Simulation time 91806023 ps
CPU time 9.47 seconds
Started Aug 25 12:52:06 PM UTC 24
Finished Aug 25 12:52:17 PM UTC 24
Peak memory 235000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018045441 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.4018045441 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.2142739166
Short name T148
Test name
Test status
Simulation time 22796627219 ps
CPU time 637.39 seconds
Started Aug 25 12:50:48 PM UTC 24
Finished Aug 25 01:01:35 PM UTC 24
Peak memory 252112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142739166 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2142739166 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2921198579
Short name T20
Test name
Test status
Simulation time 478302497 ps
CPU time 45.63 seconds
Started Aug 25 12:53:09 PM UTC 24
Finished Aug 25 12:53:56 PM UTC 24
Peak memory 234740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921198579 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2921198579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.2146846125
Short name T5
Test name
Test status
Simulation time 2599928372 ps
CPU time 83.45 seconds
Started Aug 25 12:53:10 PM UTC 24
Finished Aug 25 12:54:36 PM UTC 24
Peak memory 233932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146846125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2146846125 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.1608539699
Short name T13
Test name
Test status
Simulation time 4921542064 ps
CPU time 188.91 seconds
Started Aug 25 12:52:08 PM UTC 24
Finished Aug 25 12:55:20 PM UTC 24
Peak memory 321940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608539699 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1608539699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_error.1849058346
Short name T17
Test name
Test status
Simulation time 13761179713 ps
CPU time 547.33 seconds
Started Aug 25 12:52:18 PM UTC 24
Finished Aug 25 01:01:34 PM UTC 24
Peak memory 522616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849058346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1849058346 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.2836539809
Short name T8
Test name
Test status
Simulation time 1193780390 ps
CPU time 14.26 seconds
Started Aug 25 12:52:53 PM UTC 24
Finished Aug 25 12:53:08 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836539809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2836539809 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.45099225
Short name T693
Test name
Test status
Simulation time 83977227875 ps
CPU time 5112.74 seconds
Started Aug 25 12:50:41 PM UTC 24
Finished Aug 25 02:17:01 PM UTC 24
Peak memory 3920272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45099225 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.45099225 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.1625694686
Short name T38
Test name
Test status
Simulation time 2642041589 ps
CPU time 61.2 seconds
Started Aug 25 12:54:01 PM UTC 24
Finished Aug 25 12:55:04 PM UTC 24
Peak memory 277968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625694686 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1625694686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.1155505523
Short name T27
Test name
Test status
Simulation time 79700367809 ps
CPU time 425.67 seconds
Started Aug 25 12:50:46 PM UTC 24
Finished Aug 25 12:57:59 PM UTC 24
Peak memory 467312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155505523 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1155505523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.1631305018
Short name T32
Test name
Test status
Simulation time 11825344306 ps
CPU time 101.46 seconds
Started Aug 25 12:53:57 PM UTC 24
Finished Aug 25 12:55:42 PM UTC 24
Peak memory 267028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1631305018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r
and_reset.1631305018 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2961218429
Short name T46
Test name
Test status
Simulation time 93272541 ps
CPU time 4.96 seconds
Started Aug 25 12:51:54 PM UTC 24
Finished Aug 25 12:52:00 PM UTC 24
Peak memory 235688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961218429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2961218429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3820665135
Short name T81
Test name
Test status
Simulation time 386788014 ps
CPU time 3.26 seconds
Started Aug 25 12:52:01 PM UTC 24
Finished Aug 25 12:52:06 PM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820665135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3820665135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.2689689674
Short name T47
Test name
Test status
Simulation time 12917586416 ps
CPU time 73.77 seconds
Started Aug 25 12:50:50 PM UTC 24
Finished Aug 25 12:52:05 PM UTC 24
Peak memory 262316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689689674 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.2689689674 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2162382331
Short name T634
Test name
Test status
Simulation time 966061614454 ps
CPU time 3750.88 seconds
Started Aug 25 12:50:54 PM UTC 24
Finished Aug 25 01:54:15 PM UTC 24
Peak memory 3008660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162382331 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2162382331 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.237930538
Short name T45
Test name
Test status
Simulation time 1077070641 ps
CPU time 36.99 seconds
Started Aug 25 12:51:21 PM UTC 24
Finished Aug 25 12:52:00 PM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237930538 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.237930538 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.3023945253
Short name T401
Test name
Test status
Simulation time 191639052756 ps
CPU time 2003.31 seconds
Started Aug 25 12:51:27 PM UTC 24
Finished Aug 25 01:25:18 PM UTC 24
Peak memory 1679512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023945253 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3023945253 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.653258722
Short name T58
Test name
Test status
Simulation time 7018286124 ps
CPU time 226.91 seconds
Started Aug 25 12:51:32 PM UTC 24
Finished Aug 25 12:55:23 PM UTC 24
Peak memory 291052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653258722 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.653258722 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1312408379
Short name T110
Test name
Test status
Simulation time 5562723433 ps
CPU time 206.07 seconds
Started Aug 25 12:51:33 PM UTC 24
Finished Aug 25 12:55:03 PM UTC 24
Peak memory 362676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312408379 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1312408379 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.626021546
Short name T260
Test name
Test status
Simulation time 27656966 ps
CPU time 1.24 seconds
Started Aug 25 01:08:02 PM UTC 24
Finished Aug 25 01:08:05 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626021546 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.626021546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_app.1610610294
Short name T308
Test name
Test status
Simulation time 64591078573 ps
CPU time 461.43 seconds
Started Aug 25 01:07:27 PM UTC 24
Finished Aug 25 01:15:15 PM UTC 24
Peak memory 491836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610610294 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1610610294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.423945605
Short name T371
Test name
Test status
Simulation time 53752111431 ps
CPU time 840.08 seconds
Started Aug 25 01:07:27 PM UTC 24
Finished Aug 25 01:21:40 PM UTC 24
Peak memory 254192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423945605 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.423945605 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1763343654
Short name T257
Test name
Test status
Simulation time 270462915 ps
CPU time 3.6 seconds
Started Aug 25 01:07:47 PM UTC 24
Finished Aug 25 01:07:52 PM UTC 24
Peak memory 231620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763343654 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1763343654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3572533173
Short name T83
Test name
Test status
Simulation time 5350513712 ps
CPU time 97.8 seconds
Started Aug 25 01:07:32 PM UTC 24
Finished Aug 25 01:09:12 PM UTC 24
Peak memory 293164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572533173 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3572533173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_error.2934601036
Short name T289
Test name
Test status
Simulation time 34761814940 ps
CPU time 311.7 seconds
Started Aug 25 01:07:41 PM UTC 24
Finished Aug 25 01:12:58 PM UTC 24
Peak memory 418100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934601036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2934601036 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.3207647669
Short name T259
Test name
Test status
Simulation time 23122211591 ps
CPU time 15.5 seconds
Started Aug 25 01:07:42 PM UTC 24
Finished Aug 25 01:07:59 PM UTC 24
Peak memory 227640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207647669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.3207647669 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.677243084
Short name T67
Test name
Test status
Simulation time 63063914 ps
CPU time 1.83 seconds
Started Aug 25 01:07:57 PM UTC 24
Finished Aug 25 01:08:00 PM UTC 24
Peak memory 231308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677243084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.677243084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2752937537
Short name T540
Test name
Test status
Simulation time 14471742481 ps
CPU time 2158.68 seconds
Started Aug 25 01:07:17 PM UTC 24
Finished Aug 25 01:43:45 PM UTC 24
Peak memory 1085660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752937537 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2752937537 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.497132485
Short name T323
Test name
Test status
Simulation time 9458007921 ps
CPU time 551.41 seconds
Started Aug 25 01:07:24 PM UTC 24
Finished Aug 25 01:16:43 PM UTC 24
Peak memory 362800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497132485 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.497132485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.350944698
Short name T254
Test name
Test status
Simulation time 667533435 ps
CPU time 8.02 seconds
Started Aug 25 01:07:17 PM UTC 24
Finished Aug 25 01:07:26 PM UTC 24
Peak memory 235416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350944698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.350944698 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.3373387476
Short name T267
Test name
Test status
Simulation time 15641691 ps
CPU time 1.28 seconds
Started Aug 25 01:09:21 PM UTC 24
Finished Aug 25 01:09:24 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373387476 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3373387476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_app.636543414
Short name T312
Test name
Test status
Simulation time 38755607707 ps
CPU time 424.78 seconds
Started Aug 25 01:08:23 PM UTC 24
Finished Aug 25 01:15:34 PM UTC 24
Peak memory 434416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636543414 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.636543414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.79425931
Short name T152
Test name
Test status
Simulation time 6357011815 ps
CPU time 426.49 seconds
Started Aug 25 01:08:11 PM UTC 24
Finished Aug 25 01:15:25 PM UTC 24
Peak memory 242116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79425931 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.79425931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.1821331386
Short name T268
Test name
Test status
Simulation time 1436323870 ps
CPU time 29.08 seconds
Started Aug 25 01:09:05 PM UTC 24
Finished Aug 25 01:09:35 PM UTC 24
Peak memory 243908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821331386 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1821331386 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.1636020782
Short name T270
Test name
Test status
Simulation time 830069230 ps
CPU time 26.65 seconds
Started Aug 25 01:09:13 PM UTC 24
Finished Aug 25 01:09:41 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636020782 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1636020782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.4075017174
Short name T84
Test name
Test status
Simulation time 39968259692 ps
CPU time 221.18 seconds
Started Aug 25 01:08:23 PM UTC 24
Finished Aug 25 01:12:08 PM UTC 24
Peak memory 284984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075017174 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4075017174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_error.1720490980
Short name T161
Test name
Test status
Simulation time 2550550859 ps
CPU time 65.33 seconds
Started Aug 25 01:08:24 PM UTC 24
Finished Aug 25 01:09:31 PM UTC 24
Peak memory 262516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720490980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1720490980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.3777658824
Short name T266
Test name
Test status
Simulation time 7561447456 ps
CPU time 13.83 seconds
Started Aug 25 01:09:01 PM UTC 24
Finished Aug 25 01:09:16 PM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777658824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3777658824 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.1486504267
Short name T261
Test name
Test status
Simulation time 120901374 ps
CPU time 2.25 seconds
Started Aug 25 01:09:17 PM UTC 24
Finished Aug 25 01:09:21 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486504267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1486504267 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.2043910666
Short name T381
Test name
Test status
Simulation time 14633988122 ps
CPU time 897.98 seconds
Started Aug 25 01:08:05 PM UTC 24
Finished Aug 25 01:23:16 PM UTC 24
Peak memory 612660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043910666 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.2043910666 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.3462621011
Short name T263
Test name
Test status
Simulation time 553819346 ps
CPU time 17.39 seconds
Started Aug 25 01:08:03 PM UTC 24
Finished Aug 25 01:08:22 PM UTC 24
Peak memory 235732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462621011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3462621011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.4129700804
Short name T515
Test name
Test status
Simulation time 43862884071 ps
CPU time 1816.59 seconds
Started Aug 25 01:09:17 PM UTC 24
Finished Aug 25 01:39:58 PM UTC 24
Peak memory 1512264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129700804 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.4129700804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.3441939458
Short name T276
Test name
Test status
Simulation time 16517124 ps
CPU time 1.34 seconds
Started Aug 25 01:10:38 PM UTC 24
Finished Aug 25 01:10:40 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441939458 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3441939458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2871952470
Short name T305
Test name
Test status
Simulation time 9032656170 ps
CPU time 303.71 seconds
Started Aug 25 01:09:42 PM UTC 24
Finished Aug 25 01:14:50 PM UTC 24
Peak memory 401664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871952470 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2871952470 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.3598870482
Short name T351
Test name
Test status
Simulation time 6703712676 ps
CPU time 566.86 seconds
Started Aug 25 01:09:42 PM UTC 24
Finished Aug 25 01:19:17 PM UTC 24
Peak memory 252148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598870482 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3598870482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2615562070
Short name T273
Test name
Test status
Simulation time 1360721909 ps
CPU time 11.3 seconds
Started Aug 25 01:10:18 PM UTC 24
Finished Aug 25 01:10:31 PM UTC 24
Peak memory 235504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615562070 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2615562070 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1654205468
Short name T275
Test name
Test status
Simulation time 78599220 ps
CPU time 1.81 seconds
Started Aug 25 01:10:31 PM UTC 24
Finished Aug 25 01:10:34 PM UTC 24
Peak memory 227512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654205468 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1654205468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.834486696
Short name T279
Test name
Test status
Simulation time 3569696887 ps
CPU time 112.41 seconds
Started Aug 25 01:10:01 PM UTC 24
Finished Aug 25 01:11:56 PM UTC 24
Peak memory 297268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834486696 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.834486696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_error.343543062
Short name T333
Test name
Test status
Simulation time 19858514668 ps
CPU time 446.81 seconds
Started Aug 25 01:10:03 PM UTC 24
Finished Aug 25 01:17:37 PM UTC 24
Peak memory 489784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343543062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.343543062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.504951556
Short name T272
Test name
Test status
Simulation time 186137010 ps
CPU time 3.61 seconds
Started Aug 25 01:10:12 PM UTC 24
Finished Aug 25 01:10:17 PM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504951556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.504951556 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.3348911676
Short name T698
Test name
Test status
Simulation time 73583859264 ps
CPU time 4247.41 seconds
Started Aug 25 01:09:32 PM UTC 24
Finished Aug 25 02:21:13 PM UTC 24
Peak memory 3483960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348911676 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.3348911676 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.1911211645
Short name T317
Test name
Test status
Simulation time 69403983434 ps
CPU time 375.44 seconds
Started Aug 25 01:09:37 PM UTC 24
Finished Aug 25 01:15:58 PM UTC 24
Peak memory 434476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911211645 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1911211645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.1744545753
Short name T277
Test name
Test status
Simulation time 3486857688 ps
CPU time 77.17 seconds
Started Aug 25 01:09:25 PM UTC 24
Finished Aug 25 01:10:44 PM UTC 24
Peak memory 235748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744545753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1744545753 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.1794009589
Short name T313
Test name
Test status
Simulation time 44880272252 ps
CPU time 296.83 seconds
Started Aug 25 01:10:36 PM UTC 24
Finished Aug 25 01:15:38 PM UTC 24
Peak memory 454940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794009589 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1794009589 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.3142730756
Short name T286
Test name
Test status
Simulation time 51327674 ps
CPU time 1.18 seconds
Started Aug 25 01:12:29 PM UTC 24
Finished Aug 25 01:12:31 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142730756 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3142730756 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_app.366312739
Short name T280
Test name
Test status
Simulation time 2893399189 ps
CPU time 28.64 seconds
Started Aug 25 01:11:44 PM UTC 24
Finished Aug 25 01:12:14 PM UTC 24
Peak memory 252232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366312739 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.366312739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2554935093
Short name T407
Test name
Test status
Simulation time 30136598305 ps
CPU time 836.45 seconds
Started Aug 25 01:11:44 PM UTC 24
Finished Aug 25 01:25:52 PM UTC 24
Peak memory 256300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554935093 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2554935093 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.1882960945
Short name T287
Test name
Test status
Simulation time 1584658966 ps
CPU time 21.09 seconds
Started Aug 25 01:12:15 PM UTC 24
Finished Aug 25 01:12:38 PM UTC 24
Peak memory 234952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882960945 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.1882960945 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.196000764
Short name T283
Test name
Test status
Simulation time 26433269 ps
CPU time 1.27 seconds
Started Aug 25 01:12:23 PM UTC 24
Finished Aug 25 01:12:26 PM UTC 24
Peak memory 224312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196000764 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.196000764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.3578018128
Short name T347
Test name
Test status
Simulation time 6151759572 ps
CPU time 420.36 seconds
Started Aug 25 01:11:57 PM UTC 24
Finished Aug 25 01:19:04 PM UTC 24
Peak memory 334204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578018128 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3578018128 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_error.152047106
Short name T325
Test name
Test status
Simulation time 11985764591 ps
CPU time 281.42 seconds
Started Aug 25 01:12:09 PM UTC 24
Finished Aug 25 01:16:56 PM UTC 24
Peak memory 311556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152047106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.152047106 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.3990841591
Short name T285
Test name
Test status
Simulation time 3382492307 ps
CPU time 11.82 seconds
Started Aug 25 01:12:15 PM UTC 24
Finished Aug 25 01:12:28 PM UTC 24
Peak memory 227616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990841591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3990841591 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.3028400391
Short name T288
Test name
Test status
Simulation time 8640297892 ps
CPU time 22.95 seconds
Started Aug 25 01:12:26 PM UTC 24
Finished Aug 25 01:12:51 PM UTC 24
Peak memory 246212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028400391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3028400391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3279165243
Short name T451
Test name
Test status
Simulation time 112296527589 ps
CPU time 1258.22 seconds
Started Aug 25 01:10:45 PM UTC 24
Finished Aug 25 01:32:01 PM UTC 24
Peak memory 1290672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279165243 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3279165243 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1909703268
Short name T326
Test name
Test status
Simulation time 7385606979 ps
CPU time 331.01 seconds
Started Aug 25 01:11:23 PM UTC 24
Finished Aug 25 01:16:59 PM UTC 24
Peak memory 432372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909703268 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1909703268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.496762257
Short name T281
Test name
Test status
Simulation time 6969678499 ps
CPU time 90.88 seconds
Started Aug 25 01:10:41 PM UTC 24
Finished Aug 25 01:12:14 PM UTC 24
Peak memory 235876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496762257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.496762257 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.2106753687
Short name T489
Test name
Test status
Simulation time 103379315441 ps
CPU time 1390.03 seconds
Started Aug 25 01:12:29 PM UTC 24
Finished Aug 25 01:35:57 PM UTC 24
Peak memory 903896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106753687 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2106753687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.605809681
Short name T293
Test name
Test status
Simulation time 27981806 ps
CPU time 1.37 seconds
Started Aug 25 01:13:10 PM UTC 24
Finished Aug 25 01:13:12 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605809681 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.605809681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_app.2072237382
Short name T296
Test name
Test status
Simulation time 2017917305 ps
CPU time 62.18 seconds
Started Aug 25 01:12:41 PM UTC 24
Finished Aug 25 01:13:45 PM UTC 24
Peak memory 262308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072237382 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2072237382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.3609244587
Short name T153
Test name
Test status
Simulation time 2546110246 ps
CPU time 165.42 seconds
Started Aug 25 01:12:39 PM UTC 24
Finished Aug 25 01:15:28 PM UTC 24
Peak memory 246056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609244587 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3609244587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1949509435
Short name T290
Test name
Test status
Simulation time 71076166 ps
CPU time 1.8 seconds
Started Aug 25 01:12:59 PM UTC 24
Finished Aug 25 01:13:02 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949509435 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1949509435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.3691575787
Short name T292
Test name
Test status
Simulation time 69891705 ps
CPU time 1.37 seconds
Started Aug 25 01:13:03 PM UTC 24
Finished Aug 25 01:13:06 PM UTC 24
Peak memory 224848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691575787 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3691575787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_error.3496084800
Short name T390
Test name
Test status
Simulation time 30053155275 ps
CPU time 671.34 seconds
Started Aug 25 01:12:52 PM UTC 24
Finished Aug 25 01:24:14 PM UTC 24
Peak memory 391548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496084800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3496084800 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.3190657850
Short name T291
Test name
Test status
Simulation time 4560237803 ps
CPU time 11.25 seconds
Started Aug 25 01:12:52 PM UTC 24
Finished Aug 25 01:13:05 PM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190657850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.3190657850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3903094271
Short name T572
Test name
Test status
Simulation time 37544284657 ps
CPU time 2066.52 seconds
Started Aug 25 01:12:31 PM UTC 24
Finished Aug 25 01:47:25 PM UTC 24
Peak memory 1904852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903094271 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3903094271 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.1076365002
Short name T373
Test name
Test status
Simulation time 10392860818 ps
CPU time 550.2 seconds
Started Aug 25 01:12:32 PM UTC 24
Finished Aug 25 01:21:50 PM UTC 24
Peak memory 375088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076365002 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1076365002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.2175244961
Short name T295
Test name
Test status
Simulation time 1446720461 ps
CPU time 60.78 seconds
Started Aug 25 01:12:29 PM UTC 24
Finished Aug 25 01:13:31 PM UTC 24
Peak memory 235708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175244961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2175244961 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.796995827
Short name T324
Test name
Test status
Simulation time 6452313756 ps
CPU time 224.07 seconds
Started Aug 25 01:13:06 PM UTC 24
Finished Aug 25 01:16:54 PM UTC 24
Peak memory 334144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796995827 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.796995827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.3211707876
Short name T302
Test name
Test status
Simulation time 27931273 ps
CPU time 1.26 seconds
Started Aug 25 01:14:25 PM UTC 24
Finished Aug 25 01:14:27 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211707876 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3211707876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_app.4140081703
Short name T304
Test name
Test status
Simulation time 1119889457 ps
CPU time 48.72 seconds
Started Aug 25 01:13:46 PM UTC 24
Finished Aug 25 01:14:36 PM UTC 24
Peak memory 256184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140081703 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.4140081703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.266552924
Short name T527
Test name
Test status
Simulation time 53292778897 ps
CPU time 1707.16 seconds
Started Aug 25 01:13:33 PM UTC 24
Finished Aug 25 01:42:23 PM UTC 24
Peak memory 272680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266552924 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.266552924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.274642989
Short name T299
Test name
Test status
Simulation time 198067292 ps
CPU time 1.79 seconds
Started Aug 25 01:14:11 PM UTC 24
Finished Aug 25 01:14:14 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274642989 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.274642989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3704210065
Short name T300
Test name
Test status
Simulation time 28515819 ps
CPU time 1.71 seconds
Started Aug 25 01:14:14 PM UTC 24
Finished Aug 25 01:14:17 PM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704210065 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3704210065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1986479858
Short name T356
Test name
Test status
Simulation time 40704582914 ps
CPU time 362.95 seconds
Started Aug 25 01:13:51 PM UTC 24
Finished Aug 25 01:19:59 PM UTC 24
Peak memory 432480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986479858 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1986479858 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_error.637656758
Short name T344
Test name
Test status
Simulation time 25366371484 ps
CPU time 284.61 seconds
Started Aug 25 01:13:52 PM UTC 24
Finished Aug 25 01:18:41 PM UTC 24
Peak memory 405816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637656758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.637656758 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.3813987877
Short name T303
Test name
Test status
Simulation time 4985793959 ps
CPU time 17.98 seconds
Started Aug 25 01:14:11 PM UTC 24
Finished Aug 25 01:14:30 PM UTC 24
Peak memory 227640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813987877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3813987877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.3579584563
Short name T301
Test name
Test status
Simulation time 155577493 ps
CPU time 2.77 seconds
Started Aug 25 01:14:17 PM UTC 24
Finished Aug 25 01:14:21 PM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579584563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3579584563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2571804631
Short name T114
Test name
Test status
Simulation time 20408266431 ps
CPU time 523.45 seconds
Started Aug 25 01:13:18 PM UTC 24
Finished Aug 25 01:22:09 PM UTC 24
Peak memory 694484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571804631 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.2571804631 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.2348534631
Short name T297
Test name
Test status
Simulation time 629242404 ps
CPU time 24.73 seconds
Started Aug 25 01:13:25 PM UTC 24
Finished Aug 25 01:13:51 PM UTC 24
Peak memory 241840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348534631 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2348534631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.2770291822
Short name T298
Test name
Test status
Simulation time 3446914587 ps
CPU time 53.86 seconds
Started Aug 25 01:13:13 PM UTC 24
Finished Aug 25 01:14:08 PM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770291822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2770291822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.709791356
Short name T552
Test name
Test status
Simulation time 198435940360 ps
CPU time 1837.92 seconds
Started Aug 25 01:14:21 PM UTC 24
Finished Aug 25 01:45:24 PM UTC 24
Peak memory 1202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709791356 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.709791356 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.1905975142
Short name T310
Test name
Test status
Simulation time 26267685 ps
CPU time 1.34 seconds
Started Aug 25 01:15:21 PM UTC 24
Finished Aug 25 01:15:23 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905975142 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1905975142 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_app.1035637229
Short name T346
Test name
Test status
Simulation time 6422416817 ps
CPU time 260.43 seconds
Started Aug 25 01:14:37 PM UTC 24
Finished Aug 25 01:19:03 PM UTC 24
Peak memory 372976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035637229 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1035637229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.3111594648
Short name T487
Test name
Test status
Simulation time 85562008214 ps
CPU time 1235.44 seconds
Started Aug 25 01:14:37 PM UTC 24
Finished Aug 25 01:35:31 PM UTC 24
Peak memory 258284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111594648 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3111594648 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.167427924
Short name T315
Test name
Test status
Simulation time 3557161258 ps
CPU time 30.48 seconds
Started Aug 25 01:15:14 PM UTC 24
Finished Aug 25 01:15:46 PM UTC 24
Peak memory 243972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167427924 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.167427924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2626657020
Short name T309
Test name
Test status
Simulation time 18928905 ps
CPU time 1.51 seconds
Started Aug 25 01:15:14 PM UTC 24
Finished Aug 25 01:15:17 PM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626657020 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2626657020 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_error.490233198
Short name T306
Test name
Test status
Simulation time 1653227995 ps
CPU time 20.3 seconds
Started Aug 25 01:14:51 PM UTC 24
Finished Aug 25 01:15:13 PM UTC 24
Peak memory 245952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490233198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.490233198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.1771482185
Short name T307
Test name
Test status
Simulation time 1283328100 ps
CPU time 17.01 seconds
Started Aug 25 01:14:55 PM UTC 24
Finished Aug 25 01:15:14 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771482185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1771482185 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.914415514
Short name T68
Test name
Test status
Simulation time 146359937 ps
CPU time 1.93 seconds
Started Aug 25 01:15:16 PM UTC 24
Finished Aug 25 01:15:19 PM UTC 24
Peak memory 229320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914415514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.914415514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3939340865
Short name T684
Test name
Test status
Simulation time 57830487931 ps
CPU time 3229.93 seconds
Started Aug 25 01:14:28 PM UTC 24
Finished Aug 25 02:09:00 PM UTC 24
Peak memory 2853160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939340865 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3939340865 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.446587456
Short name T383
Test name
Test status
Simulation time 30464043324 ps
CPU time 540.18 seconds
Started Aug 25 01:14:31 PM UTC 24
Finished Aug 25 01:23:40 PM UTC 24
Peak memory 555256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446587456 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.446587456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.973161518
Short name T311
Test name
Test status
Simulation time 9093886360 ps
CPU time 64.46 seconds
Started Aug 25 01:14:25 PM UTC 24
Finished Aug 25 01:15:31 PM UTC 24
Peak memory 235812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973161518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.973161518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.251473519
Short name T320
Test name
Test status
Simulation time 21906452 ps
CPU time 1.29 seconds
Started Aug 25 01:16:08 PM UTC 24
Finished Aug 25 01:16:10 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251473519 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.251473519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_app.2202956844
Short name T327
Test name
Test status
Simulation time 8285105780 ps
CPU time 88.34 seconds
Started Aug 25 01:15:32 PM UTC 24
Finished Aug 25 01:17:03 PM UTC 24
Peak memory 278840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202956844 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2202956844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.462761811
Short name T646
Test name
Test status
Simulation time 430556773505 ps
CPU time 2365.55 seconds
Started Aug 25 01:15:29 PM UTC 24
Finished Aug 25 01:55:26 PM UTC 24
Peak memory 280876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462761811 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.462761811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.376861040
Short name T318
Test name
Test status
Simulation time 548319735 ps
CPU time 12.43 seconds
Started Aug 25 01:15:47 PM UTC 24
Finished Aug 25 01:16:01 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376861040 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.376861040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.3687337826
Short name T322
Test name
Test status
Simulation time 3257111441 ps
CPU time 37.87 seconds
Started Aug 25 01:15:52 PM UTC 24
Finished Aug 25 01:16:32 PM UTC 24
Peak memory 235624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687337826 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3687337826 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2116661279
Short name T400
Test name
Test status
Simulation time 71226281788 ps
CPU time 571.06 seconds
Started Aug 25 01:15:35 PM UTC 24
Finished Aug 25 01:25:15 PM UTC 24
Peak memory 512308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116661279 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2116661279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_error.3800978580
Short name T414
Test name
Test status
Simulation time 172235418969 ps
CPU time 671.25 seconds
Started Aug 25 01:15:39 PM UTC 24
Finished Aug 25 01:27:00 PM UTC 24
Peak memory 563516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800978580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3800978580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.3278701329
Short name T319
Test name
Test status
Simulation time 1751981362 ps
CPU time 22.95 seconds
Started Aug 25 01:15:42 PM UTC 24
Finished Aug 25 01:16:07 PM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278701329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3278701329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3302588307
Short name T713
Test name
Test status
Simulation time 111443167569 ps
CPU time 5074.57 seconds
Started Aug 25 01:15:25 PM UTC 24
Finished Aug 25 02:41:04 PM UTC 24
Peak memory 4215088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302588307 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3302588307 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.3698638881
Short name T338
Test name
Test status
Simulation time 65441508195 ps
CPU time 158.42 seconds
Started Aug 25 01:15:26 PM UTC 24
Finished Aug 25 01:18:07 PM UTC 24
Peak memory 307508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698638881 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3698638881 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.381370290
Short name T316
Test name
Test status
Simulation time 510598942 ps
CPU time 26.68 seconds
Started Aug 25 01:15:24 PM UTC 24
Finished Aug 25 01:15:52 PM UTC 24
Peak memory 235708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381370290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.381370290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.3790048143
Short name T118
Test name
Test status
Simulation time 10786454424 ps
CPU time 379.73 seconds
Started Aug 25 01:16:02 PM UTC 24
Finished Aug 25 01:22:27 PM UTC 24
Peak memory 350932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790048143 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3790048143 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.2235475384
Short name T330
Test name
Test status
Simulation time 19394709 ps
CPU time 1.29 seconds
Started Aug 25 01:17:15 PM UTC 24
Finished Aug 25 01:17:17 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235475384 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2235475384 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_app.1738277415
Short name T361
Test name
Test status
Simulation time 37155965830 ps
CPU time 245.62 seconds
Started Aug 25 01:16:37 PM UTC 24
Finished Aug 25 01:20:47 PM UTC 24
Peak memory 354624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738277415 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1738277415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.4202275429
Short name T567
Test name
Test status
Simulation time 49459750719 ps
CPU time 1789.1 seconds
Started Aug 25 01:16:33 PM UTC 24
Finished Aug 25 01:46:46 PM UTC 24
Peak memory 266544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202275429 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.4202275429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.1602566589
Short name T331
Test name
Test status
Simulation time 2561009087 ps
CPU time 21.68 seconds
Started Aug 25 01:17:00 PM UTC 24
Finished Aug 25 01:17:23 PM UTC 24
Peak memory 241920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602566589 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1602566589 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1477410721
Short name T328
Test name
Test status
Simulation time 186230226 ps
CPU time 1.97 seconds
Started Aug 25 01:17:04 PM UTC 24
Finished Aug 25 01:17:07 PM UTC 24
Peak memory 227528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477410721 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1477410721 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.2341034236
Short name T375
Test name
Test status
Simulation time 38184416648 ps
CPU time 353.88 seconds
Started Aug 25 01:16:44 PM UTC 24
Finished Aug 25 01:22:43 PM UTC 24
Peak memory 418048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341034236 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2341034236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_error.82111062
Short name T354
Test name
Test status
Simulation time 1541391415 ps
CPU time 160.82 seconds
Started Aug 25 01:16:55 PM UTC 24
Finished Aug 25 01:19:39 PM UTC 24
Peak memory 295160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82111062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.82111062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.3781062345
Short name T329
Test name
Test status
Simulation time 1496313121 ps
CPU time 13.66 seconds
Started Aug 25 01:16:56 PM UTC 24
Finished Aug 25 01:17:11 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781062345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.3781062345 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.3940457630
Short name T426
Test name
Test status
Simulation time 55810760325 ps
CPU time 723.43 seconds
Started Aug 25 01:16:20 PM UTC 24
Finished Aug 25 01:28:34 PM UTC 24
Peak memory 858420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940457630 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.3940457630 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.2949999634
Short name T334
Test name
Test status
Simulation time 730416234 ps
CPU time 71.52 seconds
Started Aug 25 01:16:26 PM UTC 24
Finished Aug 25 01:17:40 PM UTC 24
Peak memory 248108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949999634 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2949999634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.3840339746
Short name T335
Test name
Test status
Simulation time 11235001725 ps
CPU time 101.32 seconds
Started Aug 25 01:16:11 PM UTC 24
Finished Aug 25 01:17:55 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840339746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3840339746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.2780362083
Short name T432
Test name
Test status
Simulation time 33697995709 ps
CPU time 738.32 seconds
Started Aug 25 01:17:14 PM UTC 24
Finished Aug 25 01:29:43 PM UTC 24
Peak memory 320196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780362083 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2780362083 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.410445329
Short name T341
Test name
Test status
Simulation time 17340196 ps
CPU time 1.24 seconds
Started Aug 25 01:18:12 PM UTC 24
Finished Aug 25 01:18:15 PM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410445329 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.410445329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_app.3217184681
Short name T360
Test name
Test status
Simulation time 4577320039 ps
CPU time 184.26 seconds
Started Aug 25 01:17:33 PM UTC 24
Finished Aug 25 01:20:40 PM UTC 24
Peak memory 332012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217184681 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3217184681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.2886056899
Short name T458
Test name
Test status
Simulation time 29577234426 ps
CPU time 913.91 seconds
Started Aug 25 01:17:24 PM UTC 24
Finished Aug 25 01:32:50 PM UTC 24
Peak memory 246004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886056899 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2886056899 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3901822694
Short name T337
Test name
Test status
Simulation time 274153568 ps
CPU time 1.99 seconds
Started Aug 25 01:18:03 PM UTC 24
Finished Aug 25 01:18:06 PM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901822694 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3901822694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.394721487
Short name T339
Test name
Test status
Simulation time 36872500 ps
CPU time 2.01 seconds
Started Aug 25 01:18:07 PM UTC 24
Finished Aug 25 01:18:10 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394721487 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.394721487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.880526138
Short name T411
Test name
Test status
Simulation time 92237071299 ps
CPU time 520 seconds
Started Aug 25 01:17:38 PM UTC 24
Finished Aug 25 01:26:26 PM UTC 24
Peak memory 516476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880526138 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.880526138 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2062708197
Short name T394
Test name
Test status
Simulation time 21257189614 ps
CPU time 411.24 seconds
Started Aug 25 01:17:41 PM UTC 24
Finished Aug 25 01:24:39 PM UTC 24
Peak memory 487732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062708197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2062708197 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1351002497
Short name T336
Test name
Test status
Simulation time 339693628 ps
CPU time 4.68 seconds
Started Aug 25 01:17:56 PM UTC 24
Finished Aug 25 01:18:02 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351002497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1351002497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.1557751506
Short name T340
Test name
Test status
Simulation time 49677280 ps
CPU time 2.3 seconds
Started Aug 25 01:18:08 PM UTC 24
Finished Aug 25 01:18:12 PM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557751506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1557751506 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3691171764
Short name T691
Test name
Test status
Simulation time 230239897897 ps
CPU time 3454.14 seconds
Started Aug 25 01:17:16 PM UTC 24
Finished Aug 25 02:15:35 PM UTC 24
Peak memory 2791788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691171764 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3691171764 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.3561528014
Short name T391
Test name
Test status
Simulation time 7084976428 ps
CPU time 412.88 seconds
Started Aug 25 01:17:17 PM UTC 24
Finished Aug 25 01:24:17 PM UTC 24
Peak memory 338204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561528014 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3561528014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.538090133
Short name T343
Test name
Test status
Simulation time 38295775333 ps
CPU time 84.57 seconds
Started Aug 25 01:17:15 PM UTC 24
Finished Aug 25 01:18:41 PM UTC 24
Peak memory 235768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538090133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.538090133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.3882530763
Short name T641
Test name
Test status
Simulation time 156412971887 ps
CPU time 2175.29 seconds
Started Aug 25 01:18:11 PM UTC 24
Finished Aug 25 01:54:56 PM UTC 24
Peak memory 950592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882530763 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3882530763 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.1968564783
Short name T121
Test name
Test status
Simulation time 13861523 ps
CPU time 1.18 seconds
Started Aug 25 12:55:46 PM UTC 24
Finished Aug 25 12:55:48 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968564783 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1968564783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_app.3819905119
Short name T21
Test name
Test status
Simulation time 43114355085 ps
CPU time 346.87 seconds
Started Aug 25 12:55:24 PM UTC 24
Finished Aug 25 01:01:17 PM UTC 24
Peak memory 379184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819905119 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3819905119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.4164753860
Short name T187
Test name
Test status
Simulation time 7643186308 ps
CPU time 400.49 seconds
Started Aug 25 12:55:28 PM UTC 24
Finished Aug 25 01:02:15 PM UTC 24
Peak memory 315768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164753860 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.4164753860 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.3455801311
Short name T419
Test name
Test status
Simulation time 33166910874 ps
CPU time 1990.8 seconds
Started Aug 25 12:54:08 PM UTC 24
Finished Aug 25 01:27:46 PM UTC 24
Peak memory 274656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455801311 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3455801311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2189774079
Short name T196
Test name
Test status
Simulation time 126541392 ps
CPU time 16.49 seconds
Started Aug 25 12:55:39 PM UTC 24
Finished Aug 25 12:55:57 PM UTC 24
Peak memory 235500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189774079 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2189774079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.1738213907
Short name T90
Test name
Test status
Simulation time 579193144 ps
CPU time 2.23 seconds
Started Aug 25 12:55:42 PM UTC 24
Finished Aug 25 12:55:45 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738213907 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1738213907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.818681847
Short name T6
Test name
Test status
Simulation time 7126985294 ps
CPU time 60.89 seconds
Started Aug 25 12:55:42 PM UTC 24
Finished Aug 25 12:56:44 PM UTC 24
Peak memory 233956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818681847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.818681847 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1860966876
Short name T77
Test name
Test status
Simulation time 85023099 ps
CPU time 6.61 seconds
Started Aug 25 12:55:30 PM UTC 24
Finished Aug 25 12:55:38 PM UTC 24
Peak memory 231856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860966876 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1860966876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_error.3897104633
Short name T51
Test name
Test status
Simulation time 2851395590 ps
CPU time 95.93 seconds
Started Aug 25 12:55:33 PM UTC 24
Finished Aug 25 12:57:12 PM UTC 24
Peak memory 295220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897104633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3897104633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.888756813
Short name T14
Test name
Test status
Simulation time 382176677 ps
CPU time 6.18 seconds
Started Aug 25 12:55:36 PM UTC 24
Finished Aug 25 12:55:43 PM UTC 24
Peak memory 227508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888756813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.888756813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.60160477
Short name T40
Test name
Test status
Simulation time 4213708463 ps
CPU time 27.23 seconds
Started Aug 25 12:55:45 PM UTC 24
Finished Aug 25 12:56:14 PM UTC 24
Peak memory 245924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60160477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.60160477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.797190135
Short name T185
Test name
Test status
Simulation time 16619676605 ps
CPU time 843.27 seconds
Started Aug 25 12:54:06 PM UTC 24
Finished Aug 25 01:08:22 PM UTC 24
Peak memory 991456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797190135 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.797190135 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.1295031095
Short name T69
Test name
Test status
Simulation time 9633982764 ps
CPU time 90.1 seconds
Started Aug 25 12:55:32 PM UTC 24
Finished Aug 25 12:57:05 PM UTC 24
Peak memory 283264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295031095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1295031095 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.3483382675
Short name T39
Test name
Test status
Simulation time 24626757883 ps
CPU time 72.43 seconds
Started Aug 25 12:55:46 PM UTC 24
Finished Aug 25 12:57:00 PM UTC 24
Peak memory 278036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483382675 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3483382675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.3580828779
Short name T26
Test name
Test status
Simulation time 7095124077 ps
CPU time 183.28 seconds
Started Aug 25 12:54:08 PM UTC 24
Finished Aug 25 12:57:15 PM UTC 24
Peak memory 280860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580828779 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3580828779 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.570441665
Short name T142
Test name
Test status
Simulation time 4923600085 ps
CPU time 92.16 seconds
Started Aug 25 12:54:04 PM UTC 24
Finished Aug 25 12:55:39 PM UTC 24
Peak memory 235828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570441665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.570441665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.1333734211
Short name T321
Test name
Test status
Simulation time 9229833836 ps
CPU time 1222.93 seconds
Started Aug 25 12:55:45 PM UTC 24
Finished Aug 25 01:16:25 PM UTC 24
Peak memory 676084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333734211 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.1333734211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.3002948810
Short name T57
Test name
Test status
Simulation time 1696559798 ps
CPU time 69.48 seconds
Started Aug 25 12:55:45 PM UTC 24
Finished Aug 25 12:56:56 PM UTC 24
Peak memory 278772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3002948810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r
and_reset.3002948810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.403302687
Short name T138
Test name
Test status
Simulation time 104243961 ps
CPU time 4.29 seconds
Started Aug 25 12:55:21 PM UTC 24
Finished Aug 25 12:55:27 PM UTC 24
Peak memory 235836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403302687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.403302687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2593543206
Short name T139
Test name
Test status
Simulation time 659078773 ps
CPU time 5.09 seconds
Started Aug 25 12:55:23 PM UTC 24
Finished Aug 25 12:55:29 PM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593543206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2593543206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.1411171128
Short name T603
Test name
Test status
Simulation time 65342658678 ps
CPU time 3358.82 seconds
Started Aug 25 12:54:20 PM UTC 24
Finished Aug 25 01:51:01 PM UTC 24
Peak memory 3192992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411171128 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1411171128 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3866498098
Short name T194
Test name
Test status
Simulation time 2229946313 ps
CPU time 63.75 seconds
Started Aug 25 12:54:36 PM UTC 24
Finished Aug 25 12:55:42 PM UTC 24
Peak memory 256244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866498098 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3866498098 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.3797809176
Short name T140
Test name
Test status
Simulation time 3311235861 ps
CPU time 44.84 seconds
Started Aug 25 12:54:45 PM UTC 24
Finished Aug 25 12:55:32 PM UTC 24
Peak memory 235704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797809176 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3797809176 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.2336698391
Short name T137
Test name
Test status
Simulation time 648825614 ps
CPU time 29.59 seconds
Started Aug 25 12:54:50 PM UTC 24
Finished Aug 25 12:55:22 PM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336698391 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2336698391 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1417333715
Short name T212
Test name
Test status
Simulation time 32229346018 ps
CPU time 281.74 seconds
Started Aug 25 12:55:04 PM UTC 24
Finished Aug 25 12:59:50 PM UTC 24
Peak memory 444656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417333715 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1417333715 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3576612772
Short name T201
Test name
Test status
Simulation time 26147193212 ps
CPU time 211.48 seconds
Started Aug 25 12:55:05 PM UTC 24
Finished Aug 25 12:58:40 PM UTC 24
Peak memory 362712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576612772 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3576612772 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.2179807949
Short name T350
Test name
Test status
Simulation time 11056749 ps
CPU time 1.25 seconds
Started Aug 25 01:19:08 PM UTC 24
Finished Aug 25 01:19:11 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179807949 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2179807949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_app.2270949426
Short name T403
Test name
Test status
Simulation time 4528977261 ps
CPU time 394.23 seconds
Started Aug 25 01:18:42 PM UTC 24
Finished Aug 25 01:25:22 PM UTC 24
Peak memory 334208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270949426 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.2270949426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.1327101822
Short name T353
Test name
Test status
Simulation time 785595689 ps
CPU time 45.26 seconds
Started Aug 25 01:18:42 PM UTC 24
Finished Aug 25 01:19:29 PM UTC 24
Peak memory 233848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327101822 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1327101822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2369612271
Short name T363
Test name
Test status
Simulation time 3401933495 ps
CPU time 137.63 seconds
Started Aug 25 01:18:43 PM UTC 24
Finished Aug 25 01:21:03 PM UTC 24
Peak memory 309532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369612271 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2369612271 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_error.279918349
Short name T410
Test name
Test status
Simulation time 19405295980 ps
CPU time 427.08 seconds
Started Aug 25 01:19:02 PM UTC 24
Finished Aug 25 01:26:16 PM UTC 24
Peak memory 481588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279918349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.279918349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.1321166915
Short name T349
Test name
Test status
Simulation time 629086867 ps
CPU time 2.78 seconds
Started Aug 25 01:19:04 PM UTC 24
Finished Aug 25 01:19:08 PM UTC 24
Peak memory 227364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321166915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1321166915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.1783146766
Short name T65
Test name
Test status
Simulation time 34720060 ps
CPU time 2.09 seconds
Started Aug 25 01:19:05 PM UTC 24
Finished Aug 25 01:19:08 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783146766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1783146766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2721360962
Short name T547
Test name
Test status
Simulation time 11274027280 ps
CPU time 1556.08 seconds
Started Aug 25 01:18:25 PM UTC 24
Finished Aug 25 01:44:42 PM UTC 24
Peak memory 919860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721360962 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2721360962 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.2100644444
Short name T416
Test name
Test status
Simulation time 15521842285 ps
CPU time 524.24 seconds
Started Aug 25 01:18:37 PM UTC 24
Finished Aug 25 01:27:29 PM UTC 24
Peak memory 375088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100644444 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2100644444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.3386998114
Short name T345
Test name
Test status
Simulation time 461754532 ps
CPU time 25.45 seconds
Started Aug 25 01:18:15 PM UTC 24
Finished Aug 25 01:18:42 PM UTC 24
Peak memory 235704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386998114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3386998114 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.3502697517
Short name T417
Test name
Test status
Simulation time 13407027367 ps
CPU time 502.5 seconds
Started Aug 25 01:19:06 PM UTC 24
Finished Aug 25 01:27:37 PM UTC 24
Peak memory 367240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502697517 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3502697517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.1228060194
Short name T359
Test name
Test status
Simulation time 18340130 ps
CPU time 1.23 seconds
Started Aug 25 01:20:27 PM UTC 24
Finished Aug 25 01:20:30 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228060194 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1228060194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_app.269627841
Short name T362
Test name
Test status
Simulation time 3606795326 ps
CPU time 76.43 seconds
Started Aug 25 01:19:30 PM UTC 24
Finished Aug 25 01:20:48 PM UTC 24
Peak memory 270744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269627841 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.269627841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3270858553
Short name T115
Test name
Test status
Simulation time 4925509106 ps
CPU time 161.5 seconds
Started Aug 25 01:19:24 PM UTC 24
Finished Aug 25 01:22:09 PM UTC 24
Peak memory 252168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270858553 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3270858553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3247117550
Short name T117
Test name
Test status
Simulation time 3348731678 ps
CPU time 154.4 seconds
Started Aug 25 01:19:40 PM UTC 24
Finished Aug 25 01:22:18 PM UTC 24
Peak memory 268564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247117550 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3247117550 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_error.2898656566
Short name T376
Test name
Test status
Simulation time 9784969617 ps
CPU time 170.97 seconds
Started Aug 25 01:19:50 PM UTC 24
Finished Aug 25 01:22:44 PM UTC 24
Peak memory 284984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898656566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2898656566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2523149048
Short name T357
Test name
Test status
Simulation time 3985169238 ps
CPU time 22.67 seconds
Started Aug 25 01:20:00 PM UTC 24
Finished Aug 25 01:20:24 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523149048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2523149048 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.3674921533
Short name T358
Test name
Test status
Simulation time 60325364 ps
CPU time 1.99 seconds
Started Aug 25 01:20:23 PM UTC 24
Finished Aug 25 01:20:26 PM UTC 24
Peak memory 231304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674921533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3674921533 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.1113011590
Short name T591
Test name
Test status
Simulation time 66597167057 ps
CPU time 1830.82 seconds
Started Aug 25 01:19:12 PM UTC 24
Finished Aug 25 01:50:07 PM UTC 24
Peak memory 985372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113011590 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.1113011590 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.4002331754
Short name T439
Test name
Test status
Simulation time 19034733693 ps
CPU time 663.99 seconds
Started Aug 25 01:19:18 PM UTC 24
Finished Aug 25 01:30:32 PM UTC 24
Peak memory 663800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002331754 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4002331754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.2009624705
Short name T355
Test name
Test status
Simulation time 5581404834 ps
CPU time 37.78 seconds
Started Aug 25 01:19:10 PM UTC 24
Finished Aug 25 01:19:49 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009624705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2009624705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.1135470167
Short name T113
Test name
Test status
Simulation time 6576397780 ps
CPU time 87.55 seconds
Started Aug 25 01:20:25 PM UTC 24
Finished Aug 25 01:21:55 PM UTC 24
Peak memory 268640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135470167 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1135470167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.3480568790
Short name T370
Test name
Test status
Simulation time 94154317 ps
CPU time 1.36 seconds
Started Aug 25 01:21:37 PM UTC 24
Finished Aug 25 01:21:40 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480568790 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3480568790 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_app.77815939
Short name T365
Test name
Test status
Simulation time 9007757198 ps
CPU time 32.5 seconds
Started Aug 25 01:20:49 PM UTC 24
Finished Aug 25 01:21:23 PM UTC 24
Peak memory 252204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77815939 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.77815939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1778955762
Short name T574
Test name
Test status
Simulation time 126567744749 ps
CPU time 1583.86 seconds
Started Aug 25 01:20:48 PM UTC 24
Finished Aug 25 01:47:33 PM UTC 24
Peak memory 268528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778955762 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1778955762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.759829729
Short name T389
Test name
Test status
Simulation time 32626028559 ps
CPU time 167.25 seconds
Started Aug 25 01:21:04 PM UTC 24
Finished Aug 25 01:23:55 PM UTC 24
Peak memory 299312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759829729 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.759829729 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_error.728204336
Short name T430
Test name
Test status
Simulation time 23430975938 ps
CPU time 476.27 seconds
Started Aug 25 01:21:13 PM UTC 24
Finished Aug 25 01:29:16 PM UTC 24
Peak memory 356724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728204336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.728204336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.4112400992
Short name T367
Test name
Test status
Simulation time 756295972 ps
CPU time 10.25 seconds
Started Aug 25 01:21:25 PM UTC 24
Finished Aug 25 01:21:36 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112400992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4112400992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3837682293
Short name T369
Test name
Test status
Simulation time 102040710 ps
CPU time 1.97 seconds
Started Aug 25 01:21:35 PM UTC 24
Finished Aug 25 01:21:38 PM UTC 24
Peak memory 231304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837682293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3837682293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3624420925
Short name T702
Test name
Test status
Simulation time 101300203983 ps
CPU time 3699.77 seconds
Started Aug 25 01:20:44 PM UTC 24
Finished Aug 25 02:23:13 PM UTC 24
Peak memory 1718524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624420925 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3624420925 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3352410155
Short name T120
Test name
Test status
Simulation time 3059462444 ps
CPU time 113.08 seconds
Started Aug 25 01:20:44 PM UTC 24
Finished Aug 25 01:22:40 PM UTC 24
Peak memory 291120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352410155 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3352410155 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.3930200438
Short name T364
Test name
Test status
Simulation time 4458538062 ps
CPU time 39.8 seconds
Started Aug 25 01:20:31 PM UTC 24
Finished Aug 25 01:21:12 PM UTC 24
Peak memory 232072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930200438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3930200438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.790839688
Short name T658
Test name
Test status
Simulation time 52036130471 ps
CPU time 2176.87 seconds
Started Aug 25 01:21:36 PM UTC 24
Finished Aug 25 01:58:22 PM UTC 24
Peak memory 465540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790839688 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.790839688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.659764020
Short name T116
Test name
Test status
Simulation time 39349046 ps
CPU time 1.25 seconds
Started Aug 25 01:22:10 PM UTC 24
Finished Aug 25 01:22:12 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659764020 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.659764020 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_app.4287978180
Short name T386
Test name
Test status
Simulation time 2642832482 ps
CPU time 117.52 seconds
Started Aug 25 01:21:51 PM UTC 24
Finished Aug 25 01:23:52 PM UTC 24
Peak memory 262460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287978180 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4287978180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.4008238782
Short name T436
Test name
Test status
Simulation time 13799010832 ps
CPU time 489.11 seconds
Started Aug 25 01:21:41 PM UTC 24
Finished Aug 25 01:29:58 PM UTC 24
Peak memory 246012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008238782 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.4008238782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.4292496073
Short name T420
Test name
Test status
Simulation time 95996957057 ps
CPU time 354.84 seconds
Started Aug 25 01:21:51 PM UTC 24
Finished Aug 25 01:27:52 PM UTC 24
Peak memory 325872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292496073 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.4292496073 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_error.1747566694
Short name T399
Test name
Test status
Simulation time 1813685878 ps
CPU time 192.06 seconds
Started Aug 25 01:21:53 PM UTC 24
Finished Aug 25 01:25:08 PM UTC 24
Peak memory 297204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747566694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1747566694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2941762086
Short name T55
Test name
Test status
Simulation time 1010373505 ps
CPU time 31.08 seconds
Started Aug 25 01:21:56 PM UTC 24
Finished Aug 25 01:22:28 PM UTC 24
Peak memory 258576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941762086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2941762086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.3937074887
Short name T686
Test name
Test status
Simulation time 109143778466 ps
CPU time 2826.67 seconds
Started Aug 25 01:21:39 PM UTC 24
Finished Aug 25 02:09:23 PM UTC 24
Peak memory 2656620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937074887 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.3937074887 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.1152135277
Short name T443
Test name
Test status
Simulation time 15646145711 ps
CPU time 545.49 seconds
Started Aug 25 01:21:40 PM UTC 24
Finished Aug 25 01:30:54 PM UTC 24
Peak memory 563504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152135277 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1152135277 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.3499950361
Short name T372
Test name
Test status
Simulation time 156494999 ps
CPU time 8.34 seconds
Started Aug 25 01:21:38 PM UTC 24
Finished Aug 25 01:21:48 PM UTC 24
Peak memory 235708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499950361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.3499950361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.4127021777
Short name T560
Test name
Test status
Simulation time 37248753945 ps
CPU time 1409.42 seconds
Started Aug 25 01:21:56 PM UTC 24
Finished Aug 25 01:45:44 PM UTC 24
Peak memory 967308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127021777 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4127021777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.717596760
Short name T379
Test name
Test status
Simulation time 22798596 ps
CPU time 1.24 seconds
Started Aug 25 01:22:48 PM UTC 24
Finished Aug 25 01:22:50 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717596760 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.717596760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_app.2647427444
Short name T421
Test name
Test status
Simulation time 4779524465 ps
CPU time 319.3 seconds
Started Aug 25 01:22:29 PM UTC 24
Finished Aug 25 01:27:56 PM UTC 24
Peak memory 313604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647427444 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.2647427444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.3931458403
Short name T660
Test name
Test status
Simulation time 15921021395 ps
CPU time 2154.63 seconds
Started Aug 25 01:22:28 PM UTC 24
Finished Aug 25 01:58:54 PM UTC 24
Peak memory 258352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931458403 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3931458403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.3919290000
Short name T94
Test name
Test status
Simulation time 48750017317 ps
CPU time 456.02 seconds
Started Aug 25 01:22:33 PM UTC 24
Finished Aug 25 01:30:18 PM UTC 24
Peak memory 471264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919290000 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3919290000 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_error.937101328
Short name T378
Test name
Test status
Simulation time 185137547 ps
CPU time 4.52 seconds
Started Aug 25 01:22:41 PM UTC 24
Finished Aug 25 01:22:46 PM UTC 24
Peak memory 235116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937101328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.937101328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.3159670096
Short name T380
Test name
Test status
Simulation time 1021987402 ps
CPU time 12.82 seconds
Started Aug 25 01:22:45 PM UTC 24
Finished Aug 25 01:22:59 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159670096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3159670096 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.848643867
Short name T62
Test name
Test status
Simulation time 85122896 ps
CPU time 2.13 seconds
Started Aug 25 01:22:45 PM UTC 24
Finished Aug 25 01:22:49 PM UTC 24
Peak memory 231736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848643867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.848643867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1694540850
Short name T718
Test name
Test status
Simulation time 458599754926 ps
CPU time 6453.09 seconds
Started Aug 25 01:22:13 PM UTC 24
Finished Aug 25 03:11:06 PM UTC 24
Peak memory 4405672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694540850 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1694540850 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.3093011679
Short name T474
Test name
Test status
Simulation time 15587620416 ps
CPU time 721.96 seconds
Started Aug 25 01:22:19 PM UTC 24
Finished Aug 25 01:34:32 PM UTC 24
Peak memory 641348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093011679 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3093011679 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.3801629684
Short name T387
Test name
Test status
Simulation time 19680950212 ps
CPU time 99.2 seconds
Started Aug 25 01:22:10 PM UTC 24
Finished Aug 25 01:23:52 PM UTC 24
Peak memory 235768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801629684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3801629684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.3897591159
Short name T385
Test name
Test status
Simulation time 38750562 ps
CPU time 1.21 seconds
Started Aug 25 01:23:47 PM UTC 24
Finished Aug 25 01:23:49 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897591159 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3897591159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_app.1746291349
Short name T427
Test name
Test status
Simulation time 50504020037 ps
CPU time 324.21 seconds
Started Aug 25 01:23:13 PM UTC 24
Finished Aug 25 01:28:42 PM UTC 24
Peak memory 309520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746291349 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1746291349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.3579401737
Short name T639
Test name
Test status
Simulation time 13505770017 ps
CPU time 1866.84 seconds
Started Aug 25 01:23:00 PM UTC 24
Finished Aug 25 01:54:33 PM UTC 24
Peak memory 254252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579401737 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3579401737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2247717895
Short name T382
Test name
Test status
Simulation time 90531997 ps
CPU time 8.21 seconds
Started Aug 25 01:23:17 PM UTC 24
Finished Aug 25 01:23:27 PM UTC 24
Peak memory 235832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247717895 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2247717895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_error.3896141973
Short name T392
Test name
Test status
Simulation time 981304219 ps
CPU time 63.56 seconds
Started Aug 25 01:23:21 PM UTC 24
Finished Aug 25 01:24:27 PM UTC 24
Peak memory 266488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896141973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3896141973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.616978866
Short name T384
Test name
Test status
Simulation time 2563100025 ps
CPU time 17.56 seconds
Started Aug 25 01:23:27 PM UTC 24
Finished Aug 25 01:23:46 PM UTC 24
Peak memory 229608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616978866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.616978866 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.2179917675
Short name T63
Test name
Test status
Simulation time 189017475 ps
CPU time 2.03 seconds
Started Aug 25 01:23:41 PM UTC 24
Finished Aug 25 01:23:44 PM UTC 24
Peak memory 231820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179917675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2179917675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1982022968
Short name T717
Test name
Test status
Simulation time 875337426536 ps
CPU time 5899.62 seconds
Started Aug 25 01:22:51 PM UTC 24
Finished Aug 25 03:02:27 PM UTC 24
Peak memory 4049120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982022968 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1982022968 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.4236326033
Short name T498
Test name
Test status
Simulation time 21797375303 ps
CPU time 799.51 seconds
Started Aug 25 01:22:59 PM UTC 24
Finished Aug 25 01:36:30 PM UTC 24
Peak memory 690624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236326033 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.4236326033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1708379518
Short name T397
Test name
Test status
Simulation time 10033825763 ps
CPU time 117.55 seconds
Started Aug 25 01:22:50 PM UTC 24
Finished Aug 25 01:24:50 PM UTC 24
Peak memory 235896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708379518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1708379518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.3196158188
Short name T654
Test name
Test status
Simulation time 211346999647 ps
CPU time 2003.79 seconds
Started Aug 25 01:23:45 PM UTC 24
Finished Aug 25 01:57:35 PM UTC 24
Peak memory 1510080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196158188 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3196158188 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.1138761175
Short name T395
Test name
Test status
Simulation time 30082430 ps
CPU time 1.28 seconds
Started Aug 25 01:24:40 PM UTC 24
Finished Aug 25 01:24:42 PM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138761175 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1138761175 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_app.1779482856
Short name T467
Test name
Test status
Simulation time 65192735698 ps
CPU time 578.3 seconds
Started Aug 25 01:23:56 PM UTC 24
Finished Aug 25 01:33:43 PM UTC 24
Peak memory 565696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779482856 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1779482856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.1475562845
Short name T506
Test name
Test status
Simulation time 50073025944 ps
CPU time 871.67 seconds
Started Aug 25 01:23:54 PM UTC 24
Finished Aug 25 01:38:38 PM UTC 24
Peak memory 252260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475562845 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1475562845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2676193478
Short name T462
Test name
Test status
Simulation time 58617931399 ps
CPU time 534.1 seconds
Started Aug 25 01:24:14 PM UTC 24
Finished Aug 25 01:33:16 PM UTC 24
Peak memory 514364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676193478 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2676193478 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_error.41402899
Short name T447
Test name
Test status
Simulation time 122835284506 ps
CPU time 442.84 seconds
Started Aug 25 01:24:17 PM UTC 24
Finished Aug 25 01:31:47 PM UTC 24
Peak memory 493876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41402899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.41402899 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.3087892755
Short name T396
Test name
Test status
Simulation time 6764699202 ps
CPU time 19.52 seconds
Started Aug 25 01:24:27 PM UTC 24
Finished Aug 25 01:24:48 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087892755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3087892755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.2050609045
Short name T393
Test name
Test status
Simulation time 34057052 ps
CPU time 2.12 seconds
Started Aug 25 01:24:32 PM UTC 24
Finished Aug 25 01:24:35 PM UTC 24
Peak memory 233804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050609045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.2050609045 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3825470166
Short name T703
Test name
Test status
Simulation time 110837233258 ps
CPU time 3612.58 seconds
Started Aug 25 01:23:53 PM UTC 24
Finished Aug 25 02:24:54 PM UTC 24
Peak memory 1702316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825470166 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3825470166 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.3016276490
Short name T459
Test name
Test status
Simulation time 5109510147 ps
CPU time 545.48 seconds
Started Aug 25 01:23:53 PM UTC 24
Finished Aug 25 01:33:07 PM UTC 24
Peak memory 364916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016276490 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3016276490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.126341557
Short name T388
Test name
Test status
Simulation time 56168998 ps
CPU time 2.84 seconds
Started Aug 25 01:23:50 PM UTC 24
Finished Aug 25 01:23:54 PM UTC 24
Peak memory 231864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126341557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.126341557 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2615667894
Short name T478
Test name
Test status
Simulation time 14766421796 ps
CPU time 615.46 seconds
Started Aug 25 01:24:36 PM UTC 24
Finished Aug 25 01:35:01 PM UTC 24
Peak memory 547520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615667894 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2615667894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.452142095
Short name T404
Test name
Test status
Simulation time 52297489 ps
CPU time 1.29 seconds
Started Aug 25 01:25:45 PM UTC 24
Finished Aug 25 01:25:48 PM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452142095 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.452142095 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_app.921176081
Short name T406
Test name
Test status
Simulation time 6424569973 ps
CPU time 52.68 seconds
Started Aug 25 01:24:58 PM UTC 24
Finished Aug 25 01:25:52 PM UTC 24
Peak memory 254332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921176081 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.921176081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.2429141538
Short name T398
Test name
Test status
Simulation time 235138113 ps
CPU time 4.54 seconds
Started Aug 25 01:24:52 PM UTC 24
Finished Aug 25 01:24:57 PM UTC 24
Peak memory 231800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429141538 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.2429141538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3934624111
Short name T428
Test name
Test status
Simulation time 6559866259 ps
CPU time 237.74 seconds
Started Aug 25 01:25:10 PM UTC 24
Finished Aug 25 01:29:12 PM UTC 24
Peak memory 282864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934624111 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3934624111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_error.3838704468
Short name T453
Test name
Test status
Simulation time 30229541301 ps
CPU time 410.47 seconds
Started Aug 25 01:25:16 PM UTC 24
Finished Aug 25 01:32:13 PM UTC 24
Peak memory 463104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838704468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3838704468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.3474753444
Short name T402
Test name
Test status
Simulation time 315271371 ps
CPU time 2.13 seconds
Started Aug 25 01:25:19 PM UTC 24
Finished Aug 25 01:25:22 PM UTC 24
Peak memory 227432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474753444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3474753444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2114957714
Short name T56
Test name
Test status
Simulation time 1263830297 ps
CPU time 19.82 seconds
Started Aug 25 01:25:23 PM UTC 24
Finished Aug 25 01:25:44 PM UTC 24
Peak memory 244256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114957714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2114957714 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3094573563
Short name T708
Test name
Test status
Simulation time 86545501119 ps
CPU time 3774.74 seconds
Started Aug 25 01:24:43 PM UTC 24
Finished Aug 25 02:28:28 PM UTC 24
Peak memory 3229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094573563 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3094573563 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.2340162482
Short name T441
Test name
Test status
Simulation time 9179377031 ps
CPU time 358.08 seconds
Started Aug 25 01:24:49 PM UTC 24
Finished Aug 25 01:30:53 PM UTC 24
Peak memory 434420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340162482 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2340162482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.1788661754
Short name T405
Test name
Test status
Simulation time 12358292265 ps
CPU time 67.21 seconds
Started Aug 25 01:24:41 PM UTC 24
Finished Aug 25 01:25:50 PM UTC 24
Peak memory 235744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788661754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1788661754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.988370916
Short name T546
Test name
Test status
Simulation time 13236058709 ps
CPU time 1134.47 seconds
Started Aug 25 01:25:23 PM UTC 24
Finished Aug 25 01:44:34 PM UTC 24
Peak memory 567956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988370916 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.988370916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.1834769263
Short name T415
Test name
Test status
Simulation time 21506027 ps
CPU time 1.22 seconds
Started Aug 25 01:26:59 PM UTC 24
Finished Aug 25 01:27:01 PM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834769263 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1834769263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_app.527572807
Short name T422
Test name
Test status
Simulation time 2044737406 ps
CPU time 122.33 seconds
Started Aug 25 01:25:55 PM UTC 24
Finished Aug 25 01:27:59 PM UTC 24
Peak memory 264444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527572807 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.527572807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.595493935
Short name T590
Test name
Test status
Simulation time 10873221535 ps
CPU time 1423.91 seconds
Started Aug 25 01:25:54 PM UTC 24
Finished Aug 25 01:49:58 PM UTC 24
Peak memory 254232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595493935 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.595493935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.24318501
Short name T460
Test name
Test status
Simulation time 26757685696 ps
CPU time 409.2 seconds
Started Aug 25 01:26:15 PM UTC 24
Finished Aug 25 01:33:10 PM UTC 24
Peak memory 461044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24318501 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.24318501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_error.2049641199
Short name T514
Test name
Test status
Simulation time 136401822166 ps
CPU time 806.62 seconds
Started Aug 25 01:26:17 PM UTC 24
Finished Aug 25 01:39:56 PM UTC 24
Peak memory 651632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049641199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2049641199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1196785626
Short name T412
Test name
Test status
Simulation time 6310302079 ps
CPU time 17.44 seconds
Started Aug 25 01:26:26 PM UTC 24
Finished Aug 25 01:26:45 PM UTC 24
Peak memory 227712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196785626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1196785626 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.2828412596
Short name T413
Test name
Test status
Simulation time 1762481467 ps
CPU time 11.07 seconds
Started Aug 25 01:26:45 PM UTC 24
Finished Aug 25 01:26:57 PM UTC 24
Peak memory 246420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828412596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2828412596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1144166718
Short name T457
Test name
Test status
Simulation time 5897484226 ps
CPU time 402.63 seconds
Started Aug 25 01:25:51 PM UTC 24
Finished Aug 25 01:32:40 PM UTC 24
Peak memory 393528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144166718 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1144166718 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.167279163
Short name T490
Test name
Test status
Simulation time 17275091012 ps
CPU time 611.38 seconds
Started Aug 25 01:25:54 PM UTC 24
Finished Aug 25 01:36:14 PM UTC 24
Peak memory 583916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167279163 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.167279163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.117115981
Short name T409
Test name
Test status
Simulation time 2715736149 ps
CPU time 24 seconds
Started Aug 25 01:25:48 PM UTC 24
Finished Aug 25 01:26:14 PM UTC 24
Peak memory 235752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117115981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.117115981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.3820057751
Short name T434
Test name
Test status
Simulation time 13968252538 ps
CPU time 172.12 seconds
Started Aug 25 01:26:55 PM UTC 24
Finished Aug 25 01:29:50 PM UTC 24
Peak memory 344772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820057751 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3820057751 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.442904745
Short name T424
Test name
Test status
Simulation time 65266793 ps
CPU time 1.27 seconds
Started Aug 25 01:28:01 PM UTC 24
Finished Aug 25 01:28:03 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442904745 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.442904745 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_app.2552523780
Short name T435
Test name
Test status
Simulation time 1699610097 ps
CPU time 137.29 seconds
Started Aug 25 01:27:37 PM UTC 24
Finished Aug 25 01:29:57 PM UTC 24
Peak memory 266496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552523780 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2552523780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.774758697
Short name T528
Test name
Test status
Simulation time 13221892162 ps
CPU time 894.45 seconds
Started Aug 25 01:27:30 PM UTC 24
Finished Aug 25 01:42:37 PM UTC 24
Peak memory 252104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774758697 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.774758697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2435746672
Short name T456
Test name
Test status
Simulation time 5215186898 ps
CPU time 293.21 seconds
Started Aug 25 01:27:38 PM UTC 24
Finished Aug 25 01:32:36 PM UTC 24
Peak memory 303416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435746672 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2435746672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2119376014
Short name T471
Test name
Test status
Simulation time 23127616214 ps
CPU time 384.44 seconds
Started Aug 25 01:27:47 PM UTC 24
Finished Aug 25 01:34:18 PM UTC 24
Peak memory 350432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119376014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2119376014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.3966706063
Short name T423
Test name
Test status
Simulation time 1166573380 ps
CPU time 5.23 seconds
Started Aug 25 01:27:53 PM UTC 24
Finished Aug 25 01:28:00 PM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966706063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3966706063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.1867670985
Short name T60
Test name
Test status
Simulation time 147127128 ps
CPU time 2.07 seconds
Started Aug 25 01:27:57 PM UTC 24
Finished Aug 25 01:28:01 PM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867670985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1867670985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3395264837
Short name T710
Test name
Test status
Simulation time 56298976577 ps
CPU time 4288.74 seconds
Started Aug 25 01:27:02 PM UTC 24
Finished Aug 25 02:39:26 PM UTC 24
Peak memory 1900764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395264837 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3395264837 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.3964692806
Short name T492
Test name
Test status
Simulation time 69667762722 ps
CPU time 538.61 seconds
Started Aug 25 01:27:14 PM UTC 24
Finished Aug 25 01:36:20 PM UTC 24
Peak memory 377120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964692806 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3964692806 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.4245595164
Short name T418
Test name
Test status
Simulation time 4845532703 ps
CPU time 34.27 seconds
Started Aug 25 01:27:02 PM UTC 24
Finished Aug 25 01:27:37 PM UTC 24
Peak memory 235828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245595164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.4245595164 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.1989575896
Short name T675
Test name
Test status
Simulation time 52622081171 ps
CPU time 2103.67 seconds
Started Aug 25 01:28:00 PM UTC 24
Finished Aug 25 02:03:33 PM UTC 24
Peak memory 678208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989575896 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1989575896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.3445541860
Short name T200
Test name
Test status
Simulation time 12891161 ps
CPU time 1.26 seconds
Started Aug 25 12:57:45 PM UTC 24
Finished Aug 25 12:57:48 PM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445541860 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3445541860 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1078530981
Short name T221
Test name
Test status
Simulation time 8825613718 ps
CPU time 318.44 seconds
Started Aug 25 12:56:57 PM UTC 24
Finished Aug 25 01:02:21 PM UTC 24
Peak memory 311616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078530981 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1078530981 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3808111921
Short name T151
Test name
Test status
Simulation time 16890456750 ps
CPU time 999.43 seconds
Started Aug 25 12:55:55 PM UTC 24
Finished Aug 25 01:12:50 PM UTC 24
Peak memory 254260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808111921 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3808111921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.1453117596
Short name T199
Test name
Test status
Simulation time 1433533042 ps
CPU time 30.46 seconds
Started Aug 25 12:57:13 PM UTC 24
Finished Aug 25 12:57:45 PM UTC 24
Peak memory 234404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453117596 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.1453117596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3787904947
Short name T91
Test name
Test status
Simulation time 86081321 ps
CPU time 1.58 seconds
Started Aug 25 12:57:16 PM UTC 24
Finished Aug 25 12:57:19 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787904947 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3787904947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.535845582
Short name T109
Test name
Test status
Simulation time 5809527990 ps
CPU time 71.14 seconds
Started Aug 25 12:57:18 PM UTC 24
Finished Aug 25 12:58:31 PM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535845582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.535845582 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.1297443902
Short name T22
Test name
Test status
Simulation time 18131842065 ps
CPU time 579.04 seconds
Started Aug 25 12:56:59 PM UTC 24
Finished Aug 25 01:06:47 PM UTC 24
Peak memory 528664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297443902 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1297443902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_error.447098259
Short name T53
Test name
Test status
Simulation time 31395867121 ps
CPU time 454.85 seconds
Started Aug 25 12:57:06 PM UTC 24
Finished Aug 25 01:04:49 PM UTC 24
Peak memory 340276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447098259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.447098259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.1107707477
Short name T122
Test name
Test status
Simulation time 7994322658 ps
CPU time 9.05 seconds
Started Aug 25 12:57:07 PM UTC 24
Finished Aug 25 12:57:17 PM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107707477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1107707477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1788293537
Short name T78
Test name
Test status
Simulation time 39872695 ps
CPU time 2.91 seconds
Started Aug 25 12:57:19 PM UTC 24
Finished Aug 25 12:57:23 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788293537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1788293537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2349932650
Short name T477
Test name
Test status
Simulation time 51566812878 ps
CPU time 2311.58 seconds
Started Aug 25 12:55:49 PM UTC 24
Finished Aug 25 01:34:52 PM UTC 24
Peak memory 2109800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349932650 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2349932650 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.3402647589
Short name T70
Test name
Test status
Simulation time 19496636033 ps
CPU time 190.91 seconds
Started Aug 25 12:57:01 PM UTC 24
Finished Aug 25 01:00:16 PM UTC 24
Peak memory 350848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402647589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3402647589 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.169287218
Short name T123
Test name
Test status
Simulation time 7281216913 ps
CPU time 117.56 seconds
Started Aug 25 12:57:45 PM UTC 24
Finished Aug 25 12:59:46 PM UTC 24
Peak memory 296368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169287218 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.169287218 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.1801612877
Short name T202
Test name
Test status
Simulation time 1257035758 ps
CPU time 163.43 seconds
Started Aug 25 12:55:54 PM UTC 24
Finished Aug 25 12:58:41 PM UTC 24
Peak memory 264432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801612877 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1801612877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.4135919850
Short name T195
Test name
Test status
Simulation time 624711530 ps
CPU time 3.32 seconds
Started Aug 25 12:55:49 PM UTC 24
Finished Aug 25 12:55:53 PM UTC 24
Peak memory 235776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135919850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4135919850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.1549904470
Short name T425
Test name
Test status
Simulation time 67548038096 ps
CPU time 1843.61 seconds
Started Aug 25 12:57:24 PM UTC 24
Finished Aug 25 01:28:33 PM UTC 24
Peak memory 674516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549904470 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1549904470 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3777872444
Short name T197
Test name
Test status
Simulation time 126520377 ps
CPU time 5.02 seconds
Started Aug 25 12:56:45 PM UTC 24
Finished Aug 25 12:56:51 PM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777872444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3777872444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.1396561509
Short name T198
Test name
Test status
Simulation time 318709156 ps
CPU time 4.98 seconds
Started Aug 25 12:56:52 PM UTC 24
Finished Aug 25 12:56:58 PM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396561509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1396561509 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.518375943
Short name T633
Test name
Test status
Simulation time 63918584034 ps
CPU time 3441.92 seconds
Started Aug 25 12:55:58 PM UTC 24
Finished Aug 25 01:54:04 PM UTC 24
Peak memory 3156192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518375943 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.518375943 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3195809381
Short name T674
Test name
Test status
Simulation time 332745737773 ps
CPU time 3983.51 seconds
Started Aug 25 12:56:02 PM UTC 24
Finished Aug 25 02:03:18 PM UTC 24
Peak memory 2992284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195809381 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3195809381 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3548268493
Short name T545
Test name
Test status
Simulation time 947131530541 ps
CPU time 2866.46 seconds
Started Aug 25 12:56:06 PM UTC 24
Finished Aug 25 01:44:32 PM UTC 24
Peak memory 2341020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548268493 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3548268493 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.181452620
Short name T448
Test name
Test status
Simulation time 95423067283 ps
CPU time 2106.04 seconds
Started Aug 25 12:56:15 PM UTC 24
Finished Aug 25 01:31:49 PM UTC 24
Peak memory 1718428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181452620 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.181452620 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.2741179670
Short name T671
Test name
Test status
Simulation time 72518149340 ps
CPU time 3960.46 seconds
Started Aug 25 12:56:18 PM UTC 24
Finished Aug 25 02:03:11 PM UTC 24
Peak memory 3657892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741179670 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2741179670 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.10488613
Short name T189
Test name
Test status
Simulation time 52556582818 ps
CPU time 655.42 seconds
Started Aug 25 12:56:26 PM UTC 24
Finished Aug 25 01:07:31 PM UTC 24
Peak memory 368796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10488613 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.10488613 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.4093295326
Short name T433
Test name
Test status
Simulation time 38984667 ps
CPU time 1.19 seconds
Started Aug 25 01:29:44 PM UTC 24
Finished Aug 25 01:29:46 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093295326 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.4093295326 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_app.3131778126
Short name T445
Test name
Test status
Simulation time 1407374966 ps
CPU time 141.99 seconds
Started Aug 25 01:28:43 PM UTC 24
Finished Aug 25 01:31:08 PM UTC 24
Peak memory 270508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131778126 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3131778126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.1496174924
Short name T672
Test name
Test status
Simulation time 15606664722 ps
CPU time 2053.46 seconds
Started Aug 25 01:28:35 PM UTC 24
Finished Aug 25 02:03:17 PM UTC 24
Peak memory 256240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496174924 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1496174924 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2117042479
Short name T469
Test name
Test status
Simulation time 9773310407 ps
CPU time 285.39 seconds
Started Aug 25 01:29:12 PM UTC 24
Finished Aug 25 01:34:02 PM UTC 24
Peak memory 364924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117042479 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2117042479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_error.1560276353
Short name T486
Test name
Test status
Simulation time 10760792045 ps
CPU time 371.21 seconds
Started Aug 25 01:29:13 PM UTC 24
Finished Aug 25 01:35:30 PM UTC 24
Peak memory 465204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560276353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1560276353 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.2134687971
Short name T431
Test name
Test status
Simulation time 793203383 ps
CPU time 12.52 seconds
Started Aug 25 01:29:17 PM UTC 24
Finished Aug 25 01:29:31 PM UTC 24
Peak memory 227664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134687971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2134687971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.2082076259
Short name T61
Test name
Test status
Simulation time 48834813 ps
CPU time 1.92 seconds
Started Aug 25 01:29:31 PM UTC 24
Finished Aug 25 01:29:35 PM UTC 24
Peak memory 231340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082076259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.2082076259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3638822385
Short name T712
Test name
Test status
Simulation time 135352855186 ps
CPU time 4259.04 seconds
Started Aug 25 01:28:04 PM UTC 24
Finished Aug 25 02:39:59 PM UTC 24
Peak memory 3377520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638822385 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3638822385 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.1609434606
Short name T497
Test name
Test status
Simulation time 27739435410 ps
CPU time 467.39 seconds
Started Aug 25 01:28:34 PM UTC 24
Finished Aug 25 01:36:29 PM UTC 24
Peak memory 506168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609434606 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1609434606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.1896246546
Short name T429
Test name
Test status
Simulation time 2474599361 ps
CPU time 68.48 seconds
Started Aug 25 01:28:02 PM UTC 24
Finished Aug 25 01:29:12 PM UTC 24
Peak memory 235768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896246546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1896246546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3918603663
Short name T550
Test name
Test status
Simulation time 93539540325 ps
CPU time 920.51 seconds
Started Aug 25 01:29:36 PM UTC 24
Finished Aug 25 01:45:09 PM UTC 24
Peak memory 790764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918603663 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3918603663 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.2385660992
Short name T444
Test name
Test status
Simulation time 12880666 ps
CPU time 1.13 seconds
Started Aug 25 01:30:54 PM UTC 24
Finished Aug 25 01:30:56 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385660992 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2385660992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_app.2912920122
Short name T455
Test name
Test status
Simulation time 8953018705 ps
CPU time 140.73 seconds
Started Aug 25 01:30:08 PM UTC 24
Finished Aug 25 01:32:32 PM UTC 24
Peak memory 309556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912920122 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2912920122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.4248525494
Short name T586
Test name
Test status
Simulation time 15596036503 ps
CPU time 1098.85 seconds
Started Aug 25 01:29:59 PM UTC 24
Finished Aug 25 01:48:33 PM UTC 24
Peak memory 260392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248525494 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.4248525494 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2317450660
Short name T454
Test name
Test status
Simulation time 2854514440 ps
CPU time 113.23 seconds
Started Aug 25 01:30:18 PM UTC 24
Finished Aug 25 01:32:14 PM UTC 24
Peak memory 293112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317450660 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2317450660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_error.2772333362
Short name T470
Test name
Test status
Simulation time 10308265729 ps
CPU time 216.41 seconds
Started Aug 25 01:30:30 PM UTC 24
Finished Aug 25 01:34:11 PM UTC 24
Peak memory 356660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772333362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2772333362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.1768799132
Short name T112
Test name
Test status
Simulation time 1110035170 ps
CPU time 7.2 seconds
Started Aug 25 01:30:32 PM UTC 24
Finished Aug 25 01:30:41 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768799132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1768799132 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.1544418509
Short name T440
Test name
Test status
Simulation time 42397292 ps
CPU time 2.1 seconds
Started Aug 25 01:30:42 PM UTC 24
Finished Aug 25 01:30:45 PM UTC 24
Peak memory 233860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544418509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1544418509 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.3287602428
Short name T499
Test name
Test status
Simulation time 31946964182 ps
CPU time 438.15 seconds
Started Aug 25 01:29:51 PM UTC 24
Finished Aug 25 01:37:16 PM UTC 24
Peak memory 602420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287602428 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.3287602428 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.3800859798
Short name T522
Test name
Test status
Simulation time 20367862286 ps
CPU time 691.77 seconds
Started Aug 25 01:29:58 PM UTC 24
Finished Aug 25 01:41:40 PM UTC 24
Peak memory 633080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800859798 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3800859798 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.2280498829
Short name T437
Test name
Test status
Simulation time 14169686762 ps
CPU time 18.53 seconds
Started Aug 25 01:29:47 PM UTC 24
Finished Aug 25 01:30:07 PM UTC 24
Peak memory 235808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280498829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.2280498829 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.3474938607
Short name T582
Test name
Test status
Simulation time 23858407087 ps
CPU time 1044.06 seconds
Started Aug 25 01:30:46 PM UTC 24
Finished Aug 25 01:48:24 PM UTC 24
Peak memory 383684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474938607 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3474938607 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.3584534444
Short name T452
Test name
Test status
Simulation time 39045890 ps
CPU time 1.35 seconds
Started Aug 25 01:32:01 PM UTC 24
Finished Aug 25 01:32:04 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584534444 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3584534444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_app.911188113
Short name T503
Test name
Test status
Simulation time 4251460491 ps
CPU time 378.71 seconds
Started Aug 25 01:31:09 PM UTC 24
Finished Aug 25 01:37:34 PM UTC 24
Peak memory 327976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911188113 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.911188113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.3646785264
Short name T645
Test name
Test status
Simulation time 22355235875 ps
CPU time 1436.16 seconds
Started Aug 25 01:31:02 PM UTC 24
Finished Aug 25 01:55:18 PM UTC 24
Peak memory 254252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646785264 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3646785264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1262438885
Short name T93
Test name
Test status
Simulation time 19597540858 ps
CPU time 612.65 seconds
Started Aug 25 01:31:32 PM UTC 24
Finished Aug 25 01:41:54 PM UTC 24
Peak memory 524572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262438885 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1262438885 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_error.2616235067
Short name T524
Test name
Test status
Simulation time 72030082495 ps
CPU time 586.28 seconds
Started Aug 25 01:31:48 PM UTC 24
Finished Aug 25 01:41:44 PM UTC 24
Peak memory 545084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616235067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2616235067 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.381158403
Short name T449
Test name
Test status
Simulation time 612538926 ps
CPU time 2.88 seconds
Started Aug 25 01:31:50 PM UTC 24
Finished Aug 25 01:31:54 PM UTC 24
Peak memory 227344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381158403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.381158403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.1969040012
Short name T450
Test name
Test status
Simulation time 61208453 ps
CPU time 2.33 seconds
Started Aug 25 01:31:55 PM UTC 24
Finished Aug 25 01:31:59 PM UTC 24
Peak memory 233804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969040012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1969040012 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.787983620
Short name T676
Test name
Test status
Simulation time 47988133615 ps
CPU time 1939.99 seconds
Started Aug 25 01:30:55 PM UTC 24
Finished Aug 25 02:03:41 PM UTC 24
Peak memory 1050924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787983620 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.787983620 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.2932618047
Short name T510
Test name
Test status
Simulation time 28601205912 ps
CPU time 489.25 seconds
Started Aug 25 01:30:57 PM UTC 24
Finished Aug 25 01:39:13 PM UTC 24
Peak memory 362808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932618047 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2932618047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.4061045220
Short name T446
Test name
Test status
Simulation time 3629661404 ps
CPU time 34.7 seconds
Started Aug 25 01:30:55 PM UTC 24
Finished Aug 25 01:31:31 PM UTC 24
Peak memory 235852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061045220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.4061045220 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.26875581
Short name T682
Test name
Test status
Simulation time 195203730503 ps
CPU time 2061.46 seconds
Started Aug 25 01:31:59 PM UTC 24
Finished Aug 25 02:06:48 PM UTC 24
Peak memory 825988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26875581 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.26875581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2791199169
Short name T463
Test name
Test status
Simulation time 32936222 ps
CPU time 1.45 seconds
Started Aug 25 01:33:18 PM UTC 24
Finished Aug 25 01:33:20 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791199169 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2791199169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_app.1214672701
Short name T475
Test name
Test status
Simulation time 1742219768 ps
CPU time 122.73 seconds
Started Aug 25 01:32:37 PM UTC 24
Finished Aug 25 01:34:42 PM UTC 24
Peak memory 258236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214672701 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1214672701 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.2207312980
Short name T519
Test name
Test status
Simulation time 14609310624 ps
CPU time 507.8 seconds
Started Aug 25 01:32:33 PM UTC 24
Finished Aug 25 01:41:09 PM UTC 24
Peak memory 252204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207312980 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2207312980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.263599898
Short name T92
Test name
Test status
Simulation time 20753420194 ps
CPU time 378.3 seconds
Started Aug 25 01:32:41 PM UTC 24
Finished Aug 25 01:39:05 PM UTC 24
Peak memory 434428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263599898 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.263599898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_error.1790128500
Short name T544
Test name
Test status
Simulation time 20938364939 ps
CPU time 672.74 seconds
Started Aug 25 01:32:51 PM UTC 24
Finished Aug 25 01:44:14 PM UTC 24
Peak memory 633144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790128500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1790128500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.653800748
Short name T464
Test name
Test status
Simulation time 2516529668 ps
CPU time 17.67 seconds
Started Aug 25 01:33:07 PM UTC 24
Finished Aug 25 01:33:26 PM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653800748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.653800748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.487451537
Short name T461
Test name
Test status
Simulation time 54700126 ps
CPU time 2.26 seconds
Started Aug 25 01:33:11 PM UTC 24
Finished Aug 25 01:33:15 PM UTC 24
Peak memory 231816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487451537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.487451537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1092291289
Short name T651
Test name
Test status
Simulation time 106635367162 ps
CPU time 1480.1 seconds
Started Aug 25 01:32:14 PM UTC 24
Finished Aug 25 01:57:14 PM UTC 24
Peak memory 1411372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092291289 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1092291289 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.3939803995
Short name T537
Test name
Test status
Simulation time 72582682900 ps
CPU time 661.25 seconds
Started Aug 25 01:32:15 PM UTC 24
Finished Aug 25 01:43:25 PM UTC 24
Peak memory 614648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939803995 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3939803995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.2278155466
Short name T465
Test name
Test status
Simulation time 27644780563 ps
CPU time 81.58 seconds
Started Aug 25 01:32:05 PM UTC 24
Finished Aug 25 01:33:28 PM UTC 24
Peak memory 231924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278155466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.2278155466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.3462444525
Short name T630
Test name
Test status
Simulation time 41861500950 ps
CPU time 1200.37 seconds
Started Aug 25 01:33:15 PM UTC 24
Finished Aug 25 01:53:32 PM UTC 24
Peak memory 809348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462444525 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3462444525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3914400279
Short name T473
Test name
Test status
Simulation time 25312325 ps
CPU time 1.42 seconds
Started Aug 25 01:34:19 PM UTC 24
Finished Aug 25 01:34:21 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914400279 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3914400279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_app.487516465
Short name T491
Test name
Test status
Simulation time 32873313888 ps
CPU time 150.94 seconds
Started Aug 25 01:33:44 PM UTC 24
Finished Aug 25 01:36:18 PM UTC 24
Peak memory 272692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487516465 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.487516465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.1151098702
Short name T482
Test name
Test status
Simulation time 814666447 ps
CPU time 111.74 seconds
Started Aug 25 01:33:30 PM UTC 24
Finished Aug 25 01:35:24 PM UTC 24
Peak memory 235756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151098702 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1151098702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.1356009075
Short name T479
Test name
Test status
Simulation time 9278412877 ps
CPU time 68.56 seconds
Started Aug 25 01:33:59 PM UTC 24
Finished Aug 25 01:35:10 PM UTC 24
Peak memory 264572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356009075 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1356009075 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_error.500483140
Short name T517
Test name
Test status
Simulation time 17550263028 ps
CPU time 387.45 seconds
Started Aug 25 01:34:03 PM UTC 24
Finished Aug 25 01:40:37 PM UTC 24
Peak memory 461108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500483140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.500483140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.3115799662
Short name T472
Test name
Test status
Simulation time 3153253340 ps
CPU time 7.37 seconds
Started Aug 25 01:34:12 PM UTC 24
Finished Aug 25 01:34:20 PM UTC 24
Peak memory 227656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115799662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3115799662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.1696656916
Short name T79
Test name
Test status
Simulation time 55639175 ps
CPU time 2.07 seconds
Started Aug 25 01:34:13 PM UTC 24
Finished Aug 25 01:34:16 PM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696656916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1696656916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1874807453
Short name T624
Test name
Test status
Simulation time 31816110634 ps
CPU time 1142.84 seconds
Started Aug 25 01:33:27 PM UTC 24
Finished Aug 25 01:52:45 PM UTC 24
Peak memory 694640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874807453 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.1874807453 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.1081512808
Short name T538
Test name
Test status
Simulation time 10270581044 ps
CPU time 594.78 seconds
Started Aug 25 01:33:29 PM UTC 24
Finished Aug 25 01:43:32 PM UTC 24
Peak memory 393520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081512808 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1081512808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.1989605142
Short name T468
Test name
Test status
Simulation time 4880987987 ps
CPU time 36.36 seconds
Started Aug 25 01:33:21 PM UTC 24
Finished Aug 25 01:33:59 PM UTC 24
Peak memory 235828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989605142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1989605142 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.1565433037
Short name T653
Test name
Test status
Simulation time 13441981413 ps
CPU time 1367.24 seconds
Started Aug 25 01:34:17 PM UTC 24
Finished Aug 25 01:57:23 PM UTC 24
Peak memory 739636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565433037 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1565433037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.7918328
Short name T484
Test name
Test status
Simulation time 44494993 ps
CPU time 1.27 seconds
Started Aug 25 01:35:25 PM UTC 24
Finished Aug 25 01:35:27 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7918328 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.7918328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_app.1766095680
Short name T559
Test name
Test status
Simulation time 24092213434 ps
CPU time 641.29 seconds
Started Aug 25 01:34:44 PM UTC 24
Finished Aug 25 01:45:35 PM UTC 24
Peak memory 575812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766095680 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1766095680 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.1800270478
Short name T485
Test name
Test status
Simulation time 2743978687 ps
CPU time 43.26 seconds
Started Aug 25 01:34:43 PM UTC 24
Finished Aug 25 01:35:28 PM UTC 24
Peak memory 244228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800270478 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1800270478 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.1664795114
Short name T483
Test name
Test status
Simulation time 1366143258 ps
CPU time 33.2 seconds
Started Aug 25 01:34:52 PM UTC 24
Finished Aug 25 01:35:27 PM UTC 24
Peak memory 252148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664795114 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1664795114 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.2404701764
Short name T480
Test name
Test status
Simulation time 2443001517 ps
CPU time 3.7 seconds
Started Aug 25 01:35:11 PM UTC 24
Finished Aug 25 01:35:15 PM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404701764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2404701764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.3803182783
Short name T481
Test name
Test status
Simulation time 42111197 ps
CPU time 1.99 seconds
Started Aug 25 01:35:17 PM UTC 24
Finished Aug 25 01:35:20 PM UTC 24
Peak memory 231340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803182783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3803182783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.3450696943
Short name T705
Test name
Test status
Simulation time 21451297645 ps
CPU time 3049.43 seconds
Started Aug 25 01:34:22 PM UTC 24
Finished Aug 25 02:25:52 PM UTC 24
Peak memory 1503552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450696943 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.3450696943 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.4174790457
Short name T530
Test name
Test status
Simulation time 58510446255 ps
CPU time 486.34 seconds
Started Aug 25 01:34:33 PM UTC 24
Finished Aug 25 01:42:47 PM UTC 24
Peak memory 544988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174790457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.4174790457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.565732896
Short name T476
Test name
Test status
Simulation time 1492868300 ps
CPU time 20.88 seconds
Started Aug 25 01:34:21 PM UTC 24
Finished Aug 25 01:34:43 PM UTC 24
Peak memory 235772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565732896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.565732896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3805651268
Short name T683
Test name
Test status
Simulation time 271599364687 ps
CPU time 1932.31 seconds
Started Aug 25 01:35:21 PM UTC 24
Finished Aug 25 02:07:59 PM UTC 24
Peak memory 1374984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805651268 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3805651268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.2572256619
Short name T495
Test name
Test status
Simulation time 66762043 ps
CPU time 1.29 seconds
Started Aug 25 01:36:22 PM UTC 24
Finished Aug 25 01:36:24 PM UTC 24
Peak memory 225516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572256619 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2572256619 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_app.3422128159
Short name T509
Test name
Test status
Simulation time 9941740010 ps
CPU time 198.29 seconds
Started Aug 25 01:35:31 PM UTC 24
Finished Aug 25 01:38:53 PM UTC 24
Peak memory 328000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422128159 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3422128159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.2275032649
Short name T566
Test name
Test status
Simulation time 72616562036 ps
CPU time 636.68 seconds
Started Aug 25 01:35:31 PM UTC 24
Finished Aug 25 01:46:18 PM UTC 24
Peak memory 250096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275032649 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2275032649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3762778688
Short name T500
Test name
Test status
Simulation time 1883740548 ps
CPU time 101.8 seconds
Started Aug 25 01:35:38 PM UTC 24
Finished Aug 25 01:37:23 PM UTC 24
Peak memory 256292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762778688 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3762778688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_error.4057708677
Short name T564
Test name
Test status
Simulation time 50527060498 ps
CPU time 597.21 seconds
Started Aug 25 01:35:57 PM UTC 24
Finished Aug 25 01:46:04 PM UTC 24
Peak memory 577852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057708677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.4057708677 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.2586638426
Short name T493
Test name
Test status
Simulation time 209180542 ps
CPU time 4.05 seconds
Started Aug 25 01:36:16 PM UTC 24
Finished Aug 25 01:36:21 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586638426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2586638426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2762827537
Short name T494
Test name
Test status
Simulation time 39561142 ps
CPU time 2.61 seconds
Started Aug 25 01:36:19 PM UTC 24
Finished Aug 25 01:36:22 PM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762827537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2762827537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.528973512
Short name T709
Test name
Test status
Simulation time 290972488117 ps
CPU time 3152.22 seconds
Started Aug 25 01:35:28 PM UTC 24
Finished Aug 25 02:28:41 PM UTC 24
Peak memory 2662700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528973512 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.528973512 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1838106559
Short name T558
Test name
Test status
Simulation time 134049348821 ps
CPU time 594.8 seconds
Started Aug 25 01:35:29 PM UTC 24
Finished Aug 25 01:45:33 PM UTC 24
Peak memory 401656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838106559 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1838106559 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3359035093
Short name T488
Test name
Test status
Simulation time 821775105 ps
CPU time 8.76 seconds
Started Aug 25 01:35:28 PM UTC 24
Finished Aug 25 01:35:38 PM UTC 24
Peak memory 235680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359035093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3359035093 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.3992398619
Short name T706
Test name
Test status
Simulation time 285602551835 ps
CPU time 2959.38 seconds
Started Aug 25 01:36:21 PM UTC 24
Finished Aug 25 02:26:19 PM UTC 24
Peak memory 1379004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992398619 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3992398619 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.2130716676
Short name T504
Test name
Test status
Simulation time 40855306 ps
CPU time 1.23 seconds
Started Aug 25 01:37:35 PM UTC 24
Finished Aug 25 01:37:37 PM UTC 24
Peak memory 224676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130716676 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2130716676 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_app.2021672340
Short name T529
Test name
Test status
Simulation time 16251304335 ps
CPU time 364.39 seconds
Started Aug 25 01:36:31 PM UTC 24
Finished Aug 25 01:42:42 PM UTC 24
Peak memory 420156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021672340 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2021672340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1711050603
Short name T610
Test name
Test status
Simulation time 27135174878 ps
CPU time 871.14 seconds
Started Aug 25 01:36:29 PM UTC 24
Finished Aug 25 01:51:13 PM UTC 24
Peak memory 252144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711050603 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1711050603 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.3526719080
Short name T539
Test name
Test status
Simulation time 8006819050 ps
CPU time 381.45 seconds
Started Aug 25 01:37:10 PM UTC 24
Finished Aug 25 01:43:38 PM UTC 24
Peak memory 321816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526719080 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3526719080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_error.2416247269
Short name T501
Test name
Test status
Simulation time 84170994 ps
CPU time 4.49 seconds
Started Aug 25 01:37:17 PM UTC 24
Finished Aug 25 01:37:23 PM UTC 24
Peak memory 233784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416247269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.2416247269 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1275957029
Short name T505
Test name
Test status
Simulation time 1972547521 ps
CPU time 12.83 seconds
Started Aug 25 01:37:23 PM UTC 24
Finished Aug 25 01:37:37 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275957029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1275957029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.566553804
Short name T502
Test name
Test status
Simulation time 56955228 ps
CPU time 2.16 seconds
Started Aug 25 01:37:23 PM UTC 24
Finished Aug 25 01:37:27 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566553804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.566553804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.1966090864
Short name T670
Test name
Test status
Simulation time 10685937387 ps
CPU time 1562.2 seconds
Started Aug 25 01:36:25 PM UTC 24
Finished Aug 25 02:02:48 PM UTC 24
Peak memory 880916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966090864 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.1966090864 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.3006986035
Short name T507
Test name
Test status
Simulation time 13469995021 ps
CPU time 132.93 seconds
Started Aug 25 01:36:28 PM UTC 24
Finished Aug 25 01:38:44 PM UTC 24
Peak memory 305452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006986035 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3006986035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.4207401292
Short name T496
Test name
Test status
Simulation time 206829351 ps
CPU time 3.62 seconds
Started Aug 25 01:36:23 PM UTC 24
Finished Aug 25 01:36:28 PM UTC 24
Peak memory 235376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207401292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.4207401292 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.2973241503
Short name T673
Test name
Test status
Simulation time 67411649670 ps
CPU time 1528.17 seconds
Started Aug 25 01:37:27 PM UTC 24
Finished Aug 25 02:03:18 PM UTC 24
Peak memory 1090240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973241503 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2973241503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.2604967310
Short name T513
Test name
Test status
Simulation time 33992495 ps
CPU time 1.22 seconds
Started Aug 25 01:39:28 PM UTC 24
Finished Aug 25 01:39:31 PM UTC 24
Peak memory 224796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604967310 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2604967310 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_app.32891773
Short name T578
Test name
Test status
Simulation time 10797274033 ps
CPU time 537.36 seconds
Started Aug 25 01:38:50 PM UTC 24
Finished Aug 25 01:47:56 PM UTC 24
Peak memory 356660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32891773 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.32891773 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2162008037
Short name T649
Test name
Test status
Simulation time 25604260325 ps
CPU time 1024.9 seconds
Started Aug 25 01:38:46 PM UTC 24
Finished Aug 25 01:56:06 PM UTC 24
Peak memory 252140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162008037 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2162008037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.306468965
Short name T571
Test name
Test status
Simulation time 15691508186 ps
CPU time 500.7 seconds
Started Aug 25 01:38:54 PM UTC 24
Finished Aug 25 01:47:22 PM UTC 24
Peak memory 489780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306468965 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.306468965 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_error.3134482841
Short name T534
Test name
Test status
Simulation time 2407291557 ps
CPU time 233.76 seconds
Started Aug 25 01:39:08 PM UTC 24
Finished Aug 25 01:43:06 PM UTC 24
Peak memory 317688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134482841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3134482841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.1772156033
Short name T512
Test name
Test status
Simulation time 1250667446 ps
CPU time 15.33 seconds
Started Aug 25 01:39:11 PM UTC 24
Finished Aug 25 01:39:27 PM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772156033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1772156033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.912983979
Short name T511
Test name
Test status
Simulation time 115896539 ps
CPU time 1.98 seconds
Started Aug 25 01:39:14 PM UTC 24
Finished Aug 25 01:39:17 PM UTC 24
Peak memory 233352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912983979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.912983979 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2254219665
Short name T714
Test name
Test status
Simulation time 26643304361 ps
CPU time 3824.69 seconds
Started Aug 25 01:37:41 PM UTC 24
Finished Aug 25 02:42:16 PM UTC 24
Peak memory 1741100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254219665 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2254219665 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.1819063210
Short name T525
Test name
Test status
Simulation time 5043529317 ps
CPU time 196.18 seconds
Started Aug 25 01:38:40 PM UTC 24
Finished Aug 25 01:42:00 PM UTC 24
Peak memory 299236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819063210 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1819063210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.611540654
Short name T508
Test name
Test status
Simulation time 8083066805 ps
CPU time 66.98 seconds
Started Aug 25 01:37:41 PM UTC 24
Finished Aug 25 01:38:50 PM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611540654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.611540654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.3206205399
Short name T516
Test name
Test status
Simulation time 1600505882 ps
CPU time 63.28 seconds
Started Aug 25 01:39:18 PM UTC 24
Finished Aug 25 01:40:23 PM UTC 24
Peak memory 262384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206205399 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3206205399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.4284450855
Short name T523
Test name
Test status
Simulation time 12419631 ps
CPU time 1.25 seconds
Started Aug 25 01:41:40 PM UTC 24
Finished Aug 25 01:41:43 PM UTC 24
Peak memory 226116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284450855 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4284450855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_app.615104307
Short name T561
Test name
Test status
Simulation time 15855698710 ps
CPU time 309.1 seconds
Started Aug 25 01:40:39 PM UTC 24
Finished Aug 25 01:45:53 PM UTC 24
Peak memory 409996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615104307 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.615104307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.1469425551
Short name T518
Test name
Test status
Simulation time 993857740 ps
CPU time 15.54 seconds
Started Aug 25 01:40:24 PM UTC 24
Finished Aug 25 01:40:41 PM UTC 24
Peak memory 233980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469425551 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1469425551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2889505889
Short name T589
Test name
Test status
Simulation time 248681359282 ps
CPU time 511.52 seconds
Started Aug 25 01:40:42 PM UTC 24
Finished Aug 25 01:49:21 PM UTC 24
Peak memory 524664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889505889 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2889505889 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_error.2987532296
Short name T536
Test name
Test status
Simulation time 3430763023 ps
CPU time 121.85 seconds
Started Aug 25 01:41:10 PM UTC 24
Finished Aug 25 01:43:15 PM UTC 24
Peak memory 301372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987532296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2987532296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.2428407636
Short name T521
Test name
Test status
Simulation time 1205637025 ps
CPU time 14.63 seconds
Started Aug 25 01:41:13 PM UTC 24
Finished Aug 25 01:41:29 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428407636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2428407636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.1556318486
Short name T37
Test name
Test status
Simulation time 49828915 ps
CPU time 2.18 seconds
Started Aug 25 01:41:30 PM UTC 24
Finished Aug 25 01:41:33 PM UTC 24
Peak memory 231816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556318486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1556318486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2748638172
Short name T690
Test name
Test status
Simulation time 14538885919 ps
CPU time 2097.75 seconds
Started Aug 25 01:39:56 PM UTC 24
Finished Aug 25 02:15:24 PM UTC 24
Peak memory 1089840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748638172 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2748638172 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1579817446
Short name T553
Test name
Test status
Simulation time 7268135173 ps
CPU time 320.99 seconds
Started Aug 25 01:39:59 PM UTC 24
Finished Aug 25 01:45:25 PM UTC 24
Peak memory 438516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579817446 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1579817446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.3968581995
Short name T520
Test name
Test status
Simulation time 2093063442 ps
CPU time 98.27 seconds
Started Aug 25 01:39:31 PM UTC 24
Finished Aug 25 01:41:12 PM UTC 24
Peak memory 235748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968581995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3968581995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.2535944745
Short name T696
Test name
Test status
Simulation time 381046387030 ps
CPU time 2214.47 seconds
Started Aug 25 01:41:34 PM UTC 24
Finished Aug 25 02:18:59 PM UTC 24
Peak memory 643724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535944745 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2535944745 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.2806079632
Short name T211
Test name
Test status
Simulation time 31338918 ps
CPU time 1.37 seconds
Started Aug 25 12:59:38 PM UTC 24
Finished Aug 25 12:59:41 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806079632 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.2806079632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_app.3016893588
Short name T241
Test name
Test status
Simulation time 8747617695 ps
CPU time 398.92 seconds
Started Aug 25 12:58:55 PM UTC 24
Finished Aug 25 01:05:41 PM UTC 24
Peak memory 327932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016893588 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3016893588 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2525185230
Short name T242
Test name
Test status
Simulation time 11703531282 ps
CPU time 394.4 seconds
Started Aug 25 12:59:03 PM UTC 24
Finished Aug 25 01:05:43 PM UTC 24
Peak memory 438572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525185230 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2525185230 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.3621251653
Short name T374
Test name
Test status
Simulation time 10116268302 ps
CPU time 1398.65 seconds
Started Aug 25 12:58:12 PM UTC 24
Finished Aug 25 01:21:51 PM UTC 24
Peak memory 252220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621251653 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3621251653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.2072000754
Short name T87
Test name
Test status
Simulation time 89938743 ps
CPU time 1.69 seconds
Started Aug 25 12:59:19 PM UTC 24
Finished Aug 25 12:59:22 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072000754 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2072000754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.1796992462
Short name T95
Test name
Test status
Simulation time 86269248 ps
CPU time 1.66 seconds
Started Aug 25 12:59:20 PM UTC 24
Finished Aug 25 12:59:23 PM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796992462 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1796992462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.256519065
Short name T213
Test name
Test status
Simulation time 19620386674 ps
CPU time 55.55 seconds
Started Aug 25 12:59:22 PM UTC 24
Finished Aug 25 01:00:19 PM UTC 24
Peak memory 235764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256519065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.256519065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3822365162
Short name T86
Test name
Test status
Simulation time 30369236353 ps
CPU time 205.66 seconds
Started Aug 25 12:59:03 PM UTC 24
Finished Aug 25 01:02:32 PM UTC 24
Peak memory 319764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822365162 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3822365162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_error.1573427534
Short name T18
Test name
Test status
Simulation time 19728614308 ps
CPU time 402.75 seconds
Started Aug 25 12:59:06 PM UTC 24
Finished Aug 25 01:05:55 PM UTC 24
Peak memory 467260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573427534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1573427534 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.3929859338
Short name T208
Test name
Test status
Simulation time 1039246060 ps
CPU time 14.54 seconds
Started Aug 25 12:59:08 PM UTC 24
Finished Aug 25 12:59:24 PM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929859338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3929859338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.1725963522
Short name T34
Test name
Test status
Simulation time 9817858727 ps
CPU time 63.15 seconds
Started Aug 25 12:59:23 PM UTC 24
Finished Aug 25 01:00:28 PM UTC 24
Peak memory 262504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725963522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1725963522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2772312187
Short name T711
Test name
Test status
Simulation time 892882897924 ps
CPU time 6037.25 seconds
Started Aug 25 12:57:59 PM UTC 24
Finished Aug 25 02:39:55 PM UTC 24
Peak memory 3985808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772312187 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2772312187 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.691042947
Short name T72
Test name
Test status
Simulation time 6022843773 ps
CPU time 230.19 seconds
Started Aug 25 12:59:03 PM UTC 24
Finished Aug 25 01:02:57 PM UTC 24
Peak memory 359044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691042947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.691042947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.4266399349
Short name T124
Test name
Test status
Simulation time 19062043466 ps
CPU time 158.98 seconds
Started Aug 25 12:59:34 PM UTC 24
Finished Aug 25 01:02:17 PM UTC 24
Peak memory 300532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266399349 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.4266399349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.1935180719
Short name T192
Test name
Test status
Simulation time 14324155803 ps
CPU time 456.77 seconds
Started Aug 25 12:58:02 PM UTC 24
Finished Aug 25 01:05:47 PM UTC 24
Peak memory 524532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935180719 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1935180719 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.76444090
Short name T186
Test name
Test status
Simulation time 20627802463 ps
CPU time 74.28 seconds
Started Aug 25 12:57:48 PM UTC 24
Finished Aug 25 12:59:04 PM UTC 24
Peak memory 235840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76444090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.76444090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.3480855770
Short name T551
Test name
Test status
Simulation time 102504505402 ps
CPU time 2711.29 seconds
Started Aug 25 12:59:25 PM UTC 24
Finished Aug 25 01:45:12 PM UTC 24
Peak memory 789284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480855770 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3480855770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.203564716
Short name T203
Test name
Test status
Simulation time 709242795 ps
CPU time 5.91 seconds
Started Aug 25 12:58:47 PM UTC 24
Finished Aug 25 12:58:54 PM UTC 24
Peak memory 235812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203564716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.203564716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.4265821296
Short name T205
Test name
Test status
Simulation time 107034024 ps
CPU time 4.01 seconds
Started Aug 25 12:58:55 PM UTC 24
Finished Aug 25 12:59:00 PM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265821296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4265821296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.199627160
Short name T210
Test name
Test status
Simulation time 2667776959 ps
CPU time 73.46 seconds
Started Aug 25 12:58:23 PM UTC 24
Finished Aug 25 12:59:38 PM UTC 24
Peak memory 262300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199627160 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.199627160 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.2274583446
Short name T209
Test name
Test status
Simulation time 2063093310 ps
CPU time 64.79 seconds
Started Aug 25 12:58:27 PM UTC 24
Finished Aug 25 12:59:34 PM UTC 24
Peak memory 256108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274583446 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2274583446 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3926898059
Short name T207
Test name
Test status
Simulation time 5659083640 ps
CPU time 44.09 seconds
Started Aug 25 12:58:31 PM UTC 24
Finished Aug 25 12:59:17 PM UTC 24
Peak memory 241828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926898059 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3926898059 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3834892436
Short name T204
Test name
Test status
Simulation time 3050115955 ps
CPU time 26.89 seconds
Started Aug 25 12:58:32 PM UTC 24
Finished Aug 25 12:59:00 PM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834892436 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3834892436 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.361429464
Short name T680
Test name
Test status
Simulation time 73158121114 ps
CPU time 4018.28 seconds
Started Aug 25 12:58:41 PM UTC 24
Finished Aug 25 02:06:31 PM UTC 24
Peak memory 3625116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361429464 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.361429464 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.739969041
Short name T219
Test name
Test status
Simulation time 5323309935 ps
CPU time 196.96 seconds
Started Aug 25 12:58:42 PM UTC 24
Finished Aug 25 01:02:03 PM UTC 24
Peak memory 360732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739969041 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.739969041 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.3344604358
Short name T533
Test name
Test status
Simulation time 42604050 ps
CPU time 1.23 seconds
Started Aug 25 01:43:03 PM UTC 24
Finished Aug 25 01:43:05 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344604358 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3344604358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_app.322723834
Short name T531
Test name
Test status
Simulation time 1321768962 ps
CPU time 48.4 seconds
Started Aug 25 01:42:03 PM UTC 24
Finished Aug 25 01:42:53 PM UTC 24
Peak memory 256180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322723834 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.322723834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1565305145
Short name T662
Test name
Test status
Simulation time 53823931827 ps
CPU time 1019.01 seconds
Started Aug 25 01:42:01 PM UTC 24
Finished Aug 25 01:59:15 PM UTC 24
Peak memory 258352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565305145 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1565305145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.140247138
Short name T609
Test name
Test status
Simulation time 47291593900 ps
CPU time 515.93 seconds
Started Aug 25 01:42:24 PM UTC 24
Finished Aug 25 01:51:08 PM UTC 24
Peak memory 508304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140247138 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.140247138 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_error.3472347997
Short name T588
Test name
Test status
Simulation time 38333734684 ps
CPU time 379.52 seconds
Started Aug 25 01:42:38 PM UTC 24
Finished Aug 25 01:49:03 PM UTC 24
Peak memory 481716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472347997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3472347997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2074342551
Short name T532
Test name
Test status
Simulation time 4677847173 ps
CPU time 17.13 seconds
Started Aug 25 01:42:43 PM UTC 24
Finished Aug 25 01:43:02 PM UTC 24
Peak memory 229756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074342551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2074342551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.3528956046
Short name T535
Test name
Test status
Simulation time 652084757 ps
CPU time 21.19 seconds
Started Aug 25 01:42:47 PM UTC 24
Finished Aug 25 01:43:10 PM UTC 24
Peak memory 245956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528956046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3528956046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2071020223
Short name T622
Test name
Test status
Simulation time 133084177725 ps
CPU time 633.77 seconds
Started Aug 25 01:41:45 PM UTC 24
Finished Aug 25 01:52:27 PM UTC 24
Peak memory 817524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071020223 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2071020223 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.2672815197
Short name T643
Test name
Test status
Simulation time 22469458241 ps
CPU time 774.69 seconds
Started Aug 25 01:41:55 PM UTC 24
Finished Aug 25 01:55:00 PM UTC 24
Peak memory 702768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672815197 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2672815197 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.1190333911
Short name T526
Test name
Test status
Simulation time 1380699111 ps
CPU time 17.01 seconds
Started Aug 25 01:41:43 PM UTC 24
Finished Aug 25 01:42:02 PM UTC 24
Peak memory 235720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190333911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1190333911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.1282486866
Short name T688
Test name
Test status
Simulation time 49183661967 ps
CPU time 1644.45 seconds
Started Aug 25 01:42:54 PM UTC 24
Finished Aug 25 02:10:42 PM UTC 24
Peak memory 383696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282486866 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1282486866 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.2209208340
Short name T542
Test name
Test status
Simulation time 31862155 ps
CPU time 1.34 seconds
Started Aug 25 01:43:57 PM UTC 24
Finished Aug 25 01:43:59 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209208340 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2209208340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_app.582079100
Short name T620
Test name
Test status
Simulation time 193156158288 ps
CPU time 519.3 seconds
Started Aug 25 01:43:15 PM UTC 24
Finished Aug 25 01:52:02 PM UTC 24
Peak memory 502060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582079100 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.582079100 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.1425741765
Short name T692
Test name
Test status
Simulation time 33612917232 ps
CPU time 1967.1 seconds
Started Aug 25 01:43:11 PM UTC 24
Finished Aug 25 02:16:25 PM UTC 24
Peak memory 268528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425741765 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1425741765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.2908436610
Short name T581
Test name
Test status
Simulation time 36802360770 ps
CPU time 291.33 seconds
Started Aug 25 01:43:26 PM UTC 24
Finished Aug 25 01:48:23 PM UTC 24
Peak memory 356672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908436610 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.2908436610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1666904587
Short name T644
Test name
Test status
Simulation time 56537033993 ps
CPU time 693.22 seconds
Started Aug 25 01:43:33 PM UTC 24
Finished Aug 25 01:55:16 PM UTC 24
Peak memory 639208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666904587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1666904587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.294770565
Short name T541
Test name
Test status
Simulation time 2513208218 ps
CPU time 16.2 seconds
Started Aug 25 01:43:38 PM UTC 24
Finished Aug 25 01:43:56 PM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294770565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.294770565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.2319487657
Short name T97
Test name
Test status
Simulation time 106609089 ps
CPU time 2.24 seconds
Started Aug 25 01:43:47 PM UTC 24
Finished Aug 25 01:43:50 PM UTC 24
Peak memory 233776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319487657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2319487657 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.198537987
Short name T697
Test name
Test status
Simulation time 59043809735 ps
CPU time 2128.2 seconds
Started Aug 25 01:43:07 PM UTC 24
Finished Aug 25 02:19:04 PM UTC 24
Peak memory 1108272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198537987 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.198537987 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.2316352629
Short name T543
Test name
Test status
Simulation time 943350754 ps
CPU time 56.74 seconds
Started Aug 25 01:43:07 PM UTC 24
Finished Aug 25 01:44:05 PM UTC 24
Peak memory 252080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316352629 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2316352629 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2671364411
Short name T548
Test name
Test status
Simulation time 10794623398 ps
CPU time 97.5 seconds
Started Aug 25 01:43:06 PM UTC 24
Finished Aug 25 01:44:45 PM UTC 24
Peak memory 235748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671364411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2671364411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.550241865
Short name T685
Test name
Test status
Simulation time 13611326987 ps
CPU time 1489.66 seconds
Started Aug 25 01:43:51 PM UTC 24
Finished Aug 25 02:09:01 PM UTC 24
Peak memory 514776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550241865 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.550241865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.48813074
Short name T556
Test name
Test status
Simulation time 13338801 ps
CPU time 1.23 seconds
Started Aug 25 01:45:25 PM UTC 24
Finished Aug 25 01:45:28 PM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48813074 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.48813074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_app.1268567942
Short name T557
Test name
Test status
Simulation time 14774120743 ps
CPU time 53.04 seconds
Started Aug 25 01:44:34 PM UTC 24
Finished Aug 25 01:45:29 PM UTC 24
Peak memory 256312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268567942 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1268567942 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.4004349898
Short name T679
Test name
Test status
Simulation time 106527112310 ps
CPU time 1296.83 seconds
Started Aug 25 01:44:33 PM UTC 24
Finished Aug 25 02:06:28 PM UTC 24
Peak memory 262384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004349898 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.4004349898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1744686475
Short name T580
Test name
Test status
Simulation time 7424445119 ps
CPU time 199.5 seconds
Started Aug 25 01:44:43 PM UTC 24
Finished Aug 25 01:48:07 PM UTC 24
Peak memory 282960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744686475 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1744686475 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_error.695527441
Short name T636
Test name
Test status
Simulation time 12021084086 ps
CPU time 564.14 seconds
Started Aug 25 01:44:46 PM UTC 24
Finished Aug 25 01:54:19 PM UTC 24
Peak memory 542944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695527441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.695527441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.1456976574
Short name T555
Test name
Test status
Simulation time 3501174357 ps
CPU time 17.24 seconds
Started Aug 25 01:45:08 PM UTC 24
Finished Aug 25 01:45:26 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456976574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1456976574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.1743537764
Short name T554
Test name
Test status
Simulation time 1636598885 ps
CPU time 14.84 seconds
Started Aug 25 01:45:10 PM UTC 24
Finished Aug 25 01:45:26 PM UTC 24
Peak memory 246228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743537764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1743537764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1695098524
Short name T689
Test name
Test status
Simulation time 12264005762 ps
CPU time 1690.42 seconds
Started Aug 25 01:44:06 PM UTC 24
Finished Aug 25 02:12:39 PM UTC 24
Peak memory 938364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695098524 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1695098524 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.4185946141
Short name T577
Test name
Test status
Simulation time 4592393156 ps
CPU time 213.52 seconds
Started Aug 25 01:44:15 PM UTC 24
Finished Aug 25 01:47:52 PM UTC 24
Peak memory 350456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185946141 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4185946141 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.3445343366
Short name T549
Test name
Test status
Simulation time 2609322086 ps
CPU time 64.39 seconds
Started Aug 25 01:44:00 PM UTC 24
Finished Aug 25 01:45:06 PM UTC 24
Peak memory 235828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445343366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3445343366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.695102140
Short name T699
Test name
Test status
Simulation time 40292613974 ps
CPU time 2187.39 seconds
Started Aug 25 01:45:13 PM UTC 24
Finished Aug 25 02:22:10 PM UTC 24
Peak memory 823948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695102140 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.695102140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.2531257642
Short name T565
Test name
Test status
Simulation time 15020076 ps
CPU time 1.23 seconds
Started Aug 25 01:46:02 PM UTC 24
Finished Aug 25 01:46:04 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531257642 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2531257642 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_app.2138457013
Short name T657
Test name
Test status
Simulation time 41211202545 ps
CPU time 755.63 seconds
Started Aug 25 01:45:30 PM UTC 24
Finished Aug 25 01:58:17 PM UTC 24
Peak memory 665920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138457013 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2138457013 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1230129617
Short name T678
Test name
Test status
Simulation time 31350801047 ps
CPU time 1195.39 seconds
Started Aug 25 01:45:28 PM UTC 24
Finished Aug 25 02:05:41 PM UTC 24
Peak memory 252204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230129617 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1230129617 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2363551023
Short name T573
Test name
Test status
Simulation time 67150991266 ps
CPU time 111.04 seconds
Started Aug 25 01:45:33 PM UTC 24
Finished Aug 25 01:47:27 PM UTC 24
Peak memory 297252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363551023 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2363551023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_error.1682314026
Short name T613
Test name
Test status
Simulation time 13683485345 ps
CPU time 348.44 seconds
Started Aug 25 01:45:36 PM UTC 24
Finished Aug 25 01:51:29 PM UTC 24
Peak memory 338148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682314026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.1682314026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.1552878162
Short name T563
Test name
Test status
Simulation time 1186468710 ps
CPU time 14.49 seconds
Started Aug 25 01:45:46 PM UTC 24
Finished Aug 25 01:46:01 PM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552878162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1552878162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.4096128962
Short name T562
Test name
Test status
Simulation time 48331572 ps
CPU time 2.09 seconds
Started Aug 25 01:45:55 PM UTC 24
Finished Aug 25 01:45:58 PM UTC 24
Peak memory 231820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096128962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.4096128962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.283768886
Short name T694
Test name
Test status
Simulation time 13388291250 ps
CPU time 1916.41 seconds
Started Aug 25 01:45:27 PM UTC 24
Finished Aug 25 02:17:50 PM UTC 24
Peak memory 991540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283768886 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.283768886 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.2668699466
Short name T611
Test name
Test status
Simulation time 35071247794 ps
CPU time 348.63 seconds
Started Aug 25 01:45:27 PM UTC 24
Finished Aug 25 01:51:21 PM UTC 24
Peak memory 442760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668699466 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2668699466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.3852048359
Short name T569
Test name
Test status
Simulation time 3816130434 ps
CPU time 100.13 seconds
Started Aug 25 01:45:26 PM UTC 24
Finished Aug 25 01:47:09 PM UTC 24
Peak memory 235232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852048359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3852048359 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.3268050532
Short name T599
Test name
Test status
Simulation time 3756270931 ps
CPU time 265.53 seconds
Started Aug 25 01:45:59 PM UTC 24
Finished Aug 25 01:50:29 PM UTC 24
Peak memory 291156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268050532 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3268050532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.1993273136
Short name T576
Test name
Test status
Simulation time 14694166 ps
CPU time 1.28 seconds
Started Aug 25 01:47:34 PM UTC 24
Finished Aug 25 01:47:36 PM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993273136 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1993273136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_app.3576370506
Short name T621
Test name
Test status
Simulation time 4008901715 ps
CPU time 317.15 seconds
Started Aug 25 01:46:47 PM UTC 24
Finished Aug 25 01:52:10 PM UTC 24
Peak memory 311608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576370506 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3576370506 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.3710203429
Short name T667
Test name
Test status
Simulation time 43476485902 ps
CPU time 774.22 seconds
Started Aug 25 01:46:47 PM UTC 24
Finished Aug 25 01:59:52 PM UTC 24
Peak memory 250152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710203429 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3710203429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.2534620572
Short name T648
Test name
Test status
Simulation time 28950037626 ps
CPU time 505.34 seconds
Started Aug 25 01:47:10 PM UTC 24
Finished Aug 25 01:55:43 PM UTC 24
Peak memory 360768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534620572 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2534620572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_error.1215156395
Short name T655
Test name
Test status
Simulation time 23767205891 ps
CPU time 615.57 seconds
Started Aug 25 01:47:21 PM UTC 24
Finished Aug 25 01:57:45 PM UTC 24
Peak memory 405748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215156395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1215156395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.3932756350
Short name T575
Test name
Test status
Simulation time 1314389581 ps
CPU time 9.01 seconds
Started Aug 25 01:47:24 PM UTC 24
Finished Aug 25 01:47:34 PM UTC 24
Peak memory 227512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932756350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3932756350 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.2621072876
Short name T579
Test name
Test status
Simulation time 1770693009 ps
CPU time 30.44 seconds
Started Aug 25 01:47:26 PM UTC 24
Finished Aug 25 01:47:58 PM UTC 24
Peak memory 264428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621072876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2621072876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.672886878
Short name T597
Test name
Test status
Simulation time 6710891754 ps
CPU time 251.8 seconds
Started Aug 25 01:46:05 PM UTC 24
Finished Aug 25 01:50:21 PM UTC 24
Peak memory 469296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672886878 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.672886878 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.3810026438
Short name T661
Test name
Test status
Simulation time 20528285266 ps
CPU time 750.07 seconds
Started Aug 25 01:46:18 PM UTC 24
Finished Aug 25 01:58:59 PM UTC 24
Peak memory 653560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810026438 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3810026438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.1196007464
Short name T570
Test name
Test status
Simulation time 1499342861 ps
CPU time 74.27 seconds
Started Aug 25 01:46:04 PM UTC 24
Finished Aug 25 01:47:20 PM UTC 24
Peak memory 235808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196007464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1196007464 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.3502782221
Short name T716
Test name
Test status
Simulation time 54983059550 ps
CPU time 3655.99 seconds
Started Aug 25 01:47:28 PM UTC 24
Finished Aug 25 02:49:12 PM UTC 24
Peak memory 1055428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502782221 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3502782221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.3491035855
Short name T585
Test name
Test status
Simulation time 12561949 ps
CPU time 1.29 seconds
Started Aug 25 01:48:30 PM UTC 24
Finished Aug 25 01:48:33 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491035855 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.3491035855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_app.2910963130
Short name T606
Test name
Test status
Simulation time 36740821262 ps
CPU time 182.34 seconds
Started Aug 25 01:47:59 PM UTC 24
Finished Aug 25 01:51:04 PM UTC 24
Peak memory 319744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910963130 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2910963130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.360686324
Short name T656
Test name
Test status
Simulation time 10513298331 ps
CPU time 600.86 seconds
Started Aug 25 01:47:57 PM UTC 24
Finished Aug 25 01:58:06 PM UTC 24
Peak memory 252200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360686324 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.360686324 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_error.2673603616
Short name T664
Test name
Test status
Simulation time 27996092659 ps
CPU time 655.14 seconds
Started Aug 25 01:48:22 PM UTC 24
Finished Aug 25 01:59:27 PM UTC 24
Peak memory 614716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673603616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2673603616 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.2920735381
Short name T584
Test name
Test status
Simulation time 2084630096 ps
CPU time 7.22 seconds
Started Aug 25 01:48:24 PM UTC 24
Finished Aug 25 01:48:32 PM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920735381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2920735381 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2028641548
Short name T80
Test name
Test status
Simulation time 39562512 ps
CPU time 2.05 seconds
Started Aug 25 01:48:25 PM UTC 24
Finished Aug 25 01:48:28 PM UTC 24
Peak memory 231788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028641548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2028641548 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.954247512
Short name T719
Test name
Test status
Simulation time 88157180568 ps
CPU time 5559.56 seconds
Started Aug 25 01:47:37 PM UTC 24
Finished Aug 25 03:21:25 PM UTC 24
Peak memory 4096404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954247512 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.954247512 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.313668351
Short name T631
Test name
Test status
Simulation time 14336523116 ps
CPU time 338.53 seconds
Started Aug 25 01:47:53 PM UTC 24
Finished Aug 25 01:53:38 PM UTC 24
Peak memory 438584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313668351 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.313668351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.243149188
Short name T583
Test name
Test status
Simulation time 7017070824 ps
CPU time 52.3 seconds
Started Aug 25 01:47:35 PM UTC 24
Finished Aug 25 01:48:29 PM UTC 24
Peak memory 231888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243149188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.243149188 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.719905109
Short name T601
Test name
Test status
Simulation time 9972158782 ps
CPU time 132.84 seconds
Started Aug 25 01:48:29 PM UTC 24
Finished Aug 25 01:50:45 PM UTC 24
Peak memory 278756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719905109 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.719905109 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.2156261949
Short name T595
Test name
Test status
Simulation time 25028555 ps
CPU time 1.24 seconds
Started Aug 25 01:50:14 PM UTC 24
Finished Aug 25 01:50:16 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156261949 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.2156261949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_app.1519442387
Short name T593
Test name
Test status
Simulation time 5890277091 ps
CPU time 62.18 seconds
Started Aug 25 01:49:05 PM UTC 24
Finished Aug 25 01:50:09 PM UTC 24
Peak memory 264564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519442387 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1519442387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.1590005613
Short name T701
Test name
Test status
Simulation time 34562402370 ps
CPU time 1996.07 seconds
Started Aug 25 01:48:54 PM UTC 24
Finished Aug 25 02:22:38 PM UTC 24
Peak memory 272684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590005613 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1590005613 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.563183654
Short name T614
Test name
Test status
Simulation time 4215030085 ps
CPU time 135.43 seconds
Started Aug 25 01:49:22 PM UTC 24
Finished Aug 25 01:51:40 PM UTC 24
Peak memory 301360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563183654 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.563183654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_error.2233819911
Short name T642
Test name
Test status
Simulation time 6440237747 ps
CPU time 295.38 seconds
Started Aug 25 01:49:59 PM UTC 24
Finished Aug 25 01:54:59 PM UTC 24
Peak memory 319796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233819911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2233819911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.1492146519
Short name T596
Test name
Test status
Simulation time 944462181 ps
CPU time 7.71 seconds
Started Aug 25 01:50:07 PM UTC 24
Finished Aug 25 01:50:16 PM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492146519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1492146519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.4261422904
Short name T594
Test name
Test status
Simulation time 108028617 ps
CPU time 1.83 seconds
Started Aug 25 01:50:09 PM UTC 24
Finished Aug 25 01:50:12 PM UTC 24
Peak memory 231304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261422904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4261422904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.3934163463
Short name T700
Test name
Test status
Simulation time 162907140074 ps
CPU time 2012.87 seconds
Started Aug 25 01:48:33 PM UTC 24
Finished Aug 25 02:22:33 PM UTC 24
Peak memory 1927476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934163463 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.3934163463 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.3442514587
Short name T592
Test name
Test status
Simulation time 8082207583 ps
CPU time 91.54 seconds
Started Aug 25 01:48:34 PM UTC 24
Finished Aug 25 01:50:08 PM UTC 24
Peak memory 254192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442514587 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3442514587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.3836012596
Short name T587
Test name
Test status
Simulation time 449323309 ps
CPU time 17.99 seconds
Started Aug 25 01:48:33 PM UTC 24
Finished Aug 25 01:48:53 PM UTC 24
Peak memory 231920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836012596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.3836012596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1862238521
Short name T602
Test name
Test status
Simulation time 4144610099 ps
CPU time 41.8 seconds
Started Aug 25 01:50:10 PM UTC 24
Finished Aug 25 01:50:53 PM UTC 24
Peak memory 262396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862238521 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1862238521 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.65829894
Short name T608
Test name
Test status
Simulation time 42226918 ps
CPU time 1.21 seconds
Started Aug 25 01:51:04 PM UTC 24
Finished Aug 25 01:51:06 PM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65829894 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.65829894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_app.1624464862
Short name T604
Test name
Test status
Simulation time 323879815 ps
CPU time 31.06 seconds
Started Aug 25 01:50:30 PM UTC 24
Finished Aug 25 01:51:03 PM UTC 24
Peak memory 245936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624464862 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1624464862 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.53358663
Short name T637
Test name
Test status
Simulation time 3298838242 ps
CPU time 226.62 seconds
Started Aug 25 01:50:29 PM UTC 24
Finished Aug 25 01:54:20 PM UTC 24
Peak memory 235824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53358663 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.53358663 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.457673931
Short name T617
Test name
Test status
Simulation time 2290776472 ps
CPU time 65.57 seconds
Started Aug 25 01:50:38 PM UTC 24
Finished Aug 25 01:51:46 PM UTC 24
Peak memory 264472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457673931 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.457673931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_error.4126484834
Short name T652
Test name
Test status
Simulation time 8563905383 ps
CPU time 387.2 seconds
Started Aug 25 01:50:45 PM UTC 24
Finished Aug 25 01:57:19 PM UTC 24
Peak memory 457080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126484834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.4126484834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.1099787702
Short name T605
Test name
Test status
Simulation time 1828071764 ps
CPU time 8.04 seconds
Started Aug 25 01:50:53 PM UTC 24
Finished Aug 25 01:51:03 PM UTC 24
Peak memory 229632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099787702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1099787702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.1293846144
Short name T607
Test name
Test status
Simulation time 120271720 ps
CPU time 1.91 seconds
Started Aug 25 01:51:01 PM UTC 24
Finished Aug 25 01:51:05 PM UTC 24
Peak memory 231304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293846144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1293846144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.3148533972
Short name T695
Test name
Test status
Simulation time 32307546616 ps
CPU time 1634.32 seconds
Started Aug 25 01:50:17 PM UTC 24
Finished Aug 25 02:17:53 PM UTC 24
Peak memory 1691944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148533972 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.3148533972 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.3680948891
Short name T638
Test name
Test status
Simulation time 11255522987 ps
CPU time 237.81 seconds
Started Aug 25 01:50:22 PM UTC 24
Finished Aug 25 01:54:24 PM UTC 24
Peak memory 371056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680948891 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3680948891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.14691943
Short name T600
Test name
Test status
Simulation time 1216476319 ps
CPU time 18.9 seconds
Started Aug 25 01:50:17 PM UTC 24
Finished Aug 25 01:50:37 PM UTC 24
Peak memory 235708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14691943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.14691943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3447306343
Short name T707
Test name
Test status
Simulation time 174778992239 ps
CPU time 2185.93 seconds
Started Aug 25 01:51:04 PM UTC 24
Finished Aug 25 02:28:01 PM UTC 24
Peak memory 678200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447306343 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3447306343 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.3168620933
Short name T618
Test name
Test status
Simulation time 16339858 ps
CPU time 1.29 seconds
Started Aug 25 01:51:45 PM UTC 24
Finished Aug 25 01:51:47 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168620933 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.3168620933 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_app.2851329203
Short name T628
Test name
Test status
Simulation time 3518439748 ps
CPU time 117.48 seconds
Started Aug 25 01:51:14 PM UTC 24
Finished Aug 25 01:53:15 PM UTC 24
Peak memory 258300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851329203 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2851329203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.102237323
Short name T647
Test name
Test status
Simulation time 9203200676 ps
CPU time 256.43 seconds
Started Aug 25 01:51:09 PM UTC 24
Finished Aug 25 01:55:30 PM UTC 24
Peak memory 252196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102237323 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.102237323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3965132751
Short name T619
Test name
Test status
Simulation time 751112870 ps
CPU time 36.49 seconds
Started Aug 25 01:51:22 PM UTC 24
Finished Aug 25 01:52:00 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965132751 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3965132751 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_error.3006426473
Short name T663
Test name
Test status
Simulation time 15668014422 ps
CPU time 465.78 seconds
Started Aug 25 01:51:24 PM UTC 24
Finished Aug 25 01:59:17 PM UTC 24
Peak memory 356604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006426473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3006426473 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.820154859
Short name T615
Test name
Test status
Simulation time 691184434 ps
CPU time 10.06 seconds
Started Aug 25 01:51:30 PM UTC 24
Finished Aug 25 01:51:42 PM UTC 24
Peak memory 229616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820154859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.820154859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.1752630150
Short name T616
Test name
Test status
Simulation time 88548720 ps
CPU time 2.13 seconds
Started Aug 25 01:51:40 PM UTC 24
Finished Aug 25 01:51:44 PM UTC 24
Peak memory 231752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752630150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1752630150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.840113395
Short name T668
Test name
Test status
Simulation time 9954041163 ps
CPU time 521.97 seconds
Started Aug 25 01:51:06 PM UTC 24
Finished Aug 25 01:59:56 PM UTC 24
Peak memory 686324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840113395 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.840113395 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.3869948492
Short name T665
Test name
Test status
Simulation time 15658104123 ps
CPU time 506.28 seconds
Started Aug 25 01:51:07 PM UTC 24
Finished Aug 25 01:59:41 PM UTC 24
Peak memory 360688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869948492 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3869948492 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.544982252
Short name T612
Test name
Test status
Simulation time 531448443 ps
CPU time 15.98 seconds
Started Aug 25 01:51:06 PM UTC 24
Finished Aug 25 01:51:23 PM UTC 24
Peak memory 235764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544982252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.544982252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.1898901738
Short name T687
Test name
Test status
Simulation time 17729888437 ps
CPU time 1087.1 seconds
Started Aug 25 01:51:42 PM UTC 24
Finished Aug 25 02:10:06 PM UTC 24
Peak memory 678220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898901738 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1898901738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.79655322
Short name T629
Test name
Test status
Simulation time 17265695 ps
CPU time 1.22 seconds
Started Aug 25 01:53:14 PM UTC 24
Finished Aug 25 01:53:16 PM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79655322 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.79655322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_app.3889171953
Short name T627
Test name
Test status
Simulation time 3503150380 ps
CPU time 59.84 seconds
Started Aug 25 01:52:11 PM UTC 24
Finished Aug 25 01:53:13 PM UTC 24
Peak memory 248128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889171953 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.3889171953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3038830525
Short name T623
Test name
Test status
Simulation time 226391470 ps
CPU time 30.29 seconds
Started Aug 25 01:52:03 PM UTC 24
Finished Aug 25 01:52:35 PM UTC 24
Peak memory 235756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038830525 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3038830525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1056453137
Short name T650
Test name
Test status
Simulation time 19527053947 ps
CPU time 246.05 seconds
Started Aug 25 01:52:28 PM UTC 24
Finished Aug 25 01:56:39 PM UTC 24
Peak memory 352500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056453137 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1056453137 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_error.4200967953
Short name T666
Test name
Test status
Simulation time 8468393084 ps
CPU time 426.66 seconds
Started Aug 25 01:52:35 PM UTC 24
Finished Aug 25 01:59:49 PM UTC 24
Peak memory 356580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200967953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4200967953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.2414782108
Short name T625
Test name
Test status
Simulation time 520779052 ps
CPU time 7.15 seconds
Started Aug 25 01:52:46 PM UTC 24
Finished Aug 25 01:52:55 PM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414782108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2414782108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.4266222456
Short name T626
Test name
Test status
Simulation time 61585677 ps
CPU time 2.02 seconds
Started Aug 25 01:52:55 PM UTC 24
Finished Aug 25 01:52:59 PM UTC 24
Peak memory 233948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266222456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.4266222456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.541184329
Short name T669
Test name
Test status
Simulation time 11026801788 ps
CPU time 544.01 seconds
Started Aug 25 01:51:48 PM UTC 24
Finished Aug 25 02:01:00 PM UTC 24
Peak memory 731448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541184329 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.541184329 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.270421017
Short name T659
Test name
Test status
Simulation time 3549337551 ps
CPU time 388.68 seconds
Started Aug 25 01:52:01 PM UTC 24
Finished Aug 25 01:58:36 PM UTC 24
Peak memory 330008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270421017 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.270421017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.623231940
Short name T632
Test name
Test status
Simulation time 7850097468 ps
CPU time 120.94 seconds
Started Aug 25 01:51:47 PM UTC 24
Finished Aug 25 01:53:50 PM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623231940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.623231940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.474114432
Short name T704
Test name
Test status
Simulation time 15454673025 ps
CPU time 1917.38 seconds
Started Aug 25 01:53:00 PM UTC 24
Finished Aug 25 02:25:23 PM UTC 24
Peak memory 596748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474114432 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.474114432 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3089594783
Short name T216
Test name
Test status
Simulation time 23365849 ps
CPU time 1.38 seconds
Started Aug 25 01:01:43 PM UTC 24
Finished Aug 25 01:01:46 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089594783 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3089594783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_app.460035163
Short name T235
Test name
Test status
Simulation time 9109759748 ps
CPU time 207.79 seconds
Started Aug 25 01:00:17 PM UTC 24
Finished Aug 25 01:03:49 PM UTC 24
Peak memory 274804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460035163 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.460035163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3443165036
Short name T265
Test name
Test status
Simulation time 9563749770 ps
CPU time 512.26 seconds
Started Aug 25 01:00:20 PM UTC 24
Finished Aug 25 01:09:00 PM UTC 24
Peak memory 340340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443165036 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3443165036 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.2656437426
Short name T377
Test name
Test status
Simulation time 9143620715 ps
CPU time 1341.11 seconds
Started Aug 25 01:00:01 PM UTC 24
Finished Aug 25 01:22:46 PM UTC 24
Peak memory 252128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656437426 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2656437426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.2999876312
Short name T220
Test name
Test status
Simulation time 1122335212 ps
CPU time 36.67 seconds
Started Aug 25 01:01:29 PM UTC 24
Finished Aug 25 01:02:08 PM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999876312 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2999876312 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3272119915
Short name T215
Test name
Test status
Simulation time 68357039 ps
CPU time 1.38 seconds
Started Aug 25 01:01:36 PM UTC 24
Finished Aug 25 01:01:38 PM UTC 24
Peak memory 224856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272119915 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3272119915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.184501329
Short name T217
Test name
Test status
Simulation time 457061916 ps
CPU time 9.01 seconds
Started Aug 25 01:01:36 PM UTC 24
Finished Aug 25 01:01:46 PM UTC 24
Peak memory 229888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184501329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.184501329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.3511193835
Short name T85
Test name
Test status
Simulation time 3809743800 ps
CPU time 97.43 seconds
Started Aug 25 01:00:27 PM UTC 24
Finished Aug 25 01:02:07 PM UTC 24
Peak memory 268596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511193835 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.3511193835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.2392579261
Short name T214
Test name
Test status
Simulation time 2299266745 ps
CPU time 9.48 seconds
Started Aug 25 01:01:18 PM UTC 24
Finished Aug 25 01:01:29 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392579261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2392579261 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1687831062
Short name T442
Test name
Test status
Simulation time 99542044457 ps
CPU time 1841.35 seconds
Started Aug 25 12:59:47 PM UTC 24
Finished Aug 25 01:30:53 PM UTC 24
Peak memory 930040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687831062 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1687831062 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.1559618788
Short name T73
Test name
Test status
Simulation time 2597698221 ps
CPU time 218.22 seconds
Started Aug 25 01:00:29 PM UTC 24
Finished Aug 25 01:04:11 PM UTC 24
Peak memory 285420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559618788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1559618788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.1556838665
Short name T24
Test name
Test status
Simulation time 2501876032 ps
CPU time 109.11 seconds
Started Aug 25 12:59:51 PM UTC 24
Finished Aug 25 01:01:42 PM UTC 24
Peak memory 295280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556838665 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1556838665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.2812600193
Short name T206
Test name
Test status
Simulation time 3525119315 ps
CPU time 16.96 seconds
Started Aug 25 12:59:41 PM UTC 24
Finished Aug 25 01:00:00 PM UTC 24
Peak memory 235812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812600193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2812600193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.3333880514
Short name T119
Test name
Test status
Simulation time 119647754643 ps
CPU time 1232.35 seconds
Started Aug 25 01:01:42 PM UTC 24
Finished Aug 25 01:22:32 PM UTC 24
Peak memory 612664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333880514 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3333880514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.238437098
Short name T71
Test name
Test status
Simulation time 3797875809 ps
CPU time 55.54 seconds
Started Aug 25 01:01:43 PM UTC 24
Finished Aug 25 01:02:41 PM UTC 24
Peak memory 252612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=238437098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_ra
nd_reset.238437098 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.2349405914
Short name T226
Test name
Test status
Simulation time 26001116 ps
CPU time 1.29 seconds
Started Aug 25 01:02:41 PM UTC 24
Finished Aug 25 01:02:44 PM UTC 24
Peak memory 225276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349405914 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2349405914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_app.4030729835
Short name T228
Test name
Test status
Simulation time 606696162 ps
CPU time 68.43 seconds
Started Aug 25 01:01:57 PM UTC 24
Finished Aug 25 01:03:07 PM UTC 24
Peak memory 245944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030729835 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4030729835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1600759705
Short name T224
Test name
Test status
Simulation time 837931802 ps
CPU time 27.97 seconds
Started Aug 25 01:02:00 PM UTC 24
Finished Aug 25 01:02:29 PM UTC 24
Peak memory 241840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600759705 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1600759705 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.2357516797
Short name T149
Test name
Test status
Simulation time 5349896655 ps
CPU time 488.55 seconds
Started Aug 25 01:01:55 PM UTC 24
Finished Aug 25 01:10:12 PM UTC 24
Peak memory 241976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357516797 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.2357516797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.543909564
Short name T229
Test name
Test status
Simulation time 804492793 ps
CPU time 50.85 seconds
Started Aug 25 01:02:17 PM UTC 24
Finished Aug 25 01:03:10 PM UTC 24
Peak memory 235072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543909564 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.543909564 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.2893169216
Short name T223
Test name
Test status
Simulation time 96577165 ps
CPU time 2.07 seconds
Started Aug 25 01:02:21 PM UTC 24
Finished Aug 25 01:02:24 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893169216 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2893169216 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.2745632364
Short name T230
Test name
Test status
Simulation time 30440547439 ps
CPU time 44.8 seconds
Started Aug 25 01:02:25 PM UTC 24
Finished Aug 25 01:03:12 PM UTC 24
Peak memory 235832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745632364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2745632364 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.1532073992
Short name T262
Test name
Test status
Simulation time 37686475374 ps
CPU time 360.52 seconds
Started Aug 25 01:02:04 PM UTC 24
Finished Aug 25 01:08:11 PM UTC 24
Peak memory 405816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532073992 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.1532073992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_error.3009630043
Short name T240
Test name
Test status
Simulation time 5893449777 ps
CPU time 202.75 seconds
Started Aug 25 01:02:09 PM UTC 24
Finished Aug 25 01:05:36 PM UTC 24
Peak memory 352576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009630043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3009630043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1899704241
Short name T222
Test name
Test status
Simulation time 415790899 ps
CPU time 6.86 seconds
Started Aug 25 01:02:16 PM UTC 24
Finished Aug 25 01:02:24 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899704241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1899704241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2469977893
Short name T227
Test name
Test status
Simulation time 4868806864 ps
CPU time 30.16 seconds
Started Aug 25 01:02:25 PM UTC 24
Finished Aug 25 01:02:57 PM UTC 24
Peak memory 243980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469977893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2469977893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.3018712981
Short name T681
Test name
Test status
Simulation time 29367558780 ps
CPU time 3840.27 seconds
Started Aug 25 01:01:47 PM UTC 24
Finished Aug 25 02:06:37 PM UTC 24
Peak memory 1648920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018712981 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.3018712981 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.4000702897
Short name T271
Test name
Test status
Simulation time 9583358330 ps
CPU time 466.96 seconds
Started Aug 25 01:02:08 PM UTC 24
Finished Aug 25 01:10:03 PM UTC 24
Peak memory 346724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000702897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4000702897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.1334575856
Short name T191
Test name
Test status
Simulation time 47136054852 ps
CPU time 190.17 seconds
Started Aug 25 01:01:47 PM UTC 24
Finished Aug 25 01:05:00 PM UTC 24
Peak memory 313616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334575856 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1334575856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.3273840993
Short name T218
Test name
Test status
Simulation time 570991819 ps
CPU time 9.16 seconds
Started Aug 25 01:01:45 PM UTC 24
Finished Aug 25 01:01:56 PM UTC 24
Peak memory 235836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273840993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3273840993 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.597480788
Short name T225
Test name
Test status
Simulation time 1160817592 ps
CPU time 9.5 seconds
Started Aug 25 01:02:30 PM UTC 24
Finished Aug 25 01:02:41 PM UTC 24
Peak memory 235760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597480788 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.597480788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.1772812558
Short name T236
Test name
Test status
Simulation time 41669576 ps
CPU time 1.18 seconds
Started Aug 25 01:04:13 PM UTC 24
Finished Aug 25 01:04:15 PM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772812558 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1772812558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_app.3630023098
Short name T249
Test name
Test status
Simulation time 2957019351 ps
CPU time 235.27 seconds
Started Aug 25 01:02:58 PM UTC 24
Finished Aug 25 01:06:57 PM UTC 24
Peak memory 285072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630023098 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3630023098 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2499083031
Short name T239
Test name
Test status
Simulation time 19701612358 ps
CPU time 151.45 seconds
Started Aug 25 01:03:00 PM UTC 24
Finished Aug 25 01:05:35 PM UTC 24
Peak memory 299312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499083031 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2499083031 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3383571764
Short name T438
Test name
Test status
Simulation time 33777533608 ps
CPU time 1631.28 seconds
Started Aug 25 01:02:58 PM UTC 24
Finished Aug 25 01:30:29 PM UTC 24
Peak memory 266548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383571764 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3383571764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.723657331
Short name T233
Test name
Test status
Simulation time 214146154 ps
CPU time 5.54 seconds
Started Aug 25 01:03:24 PM UTC 24
Finished Aug 25 01:03:31 PM UTC 24
Peak memory 234860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723657331 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.723657331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2603569772
Short name T232
Test name
Test status
Simulation time 47893308 ps
CPU time 1.7 seconds
Started Aug 25 01:03:26 PM UTC 24
Finished Aug 25 01:03:29 PM UTC 24
Peak memory 227536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603569772 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2603569772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.880587694
Short name T169
Test name
Test status
Simulation time 14662051258 ps
CPU time 60.09 seconds
Started Aug 25 01:03:30 PM UTC 24
Finished Aug 25 01:04:32 PM UTC 24
Peak memory 235768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880587694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.880587694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1361431850
Short name T82
Test name
Test status
Simulation time 6317907650 ps
CPU time 194.4 seconds
Started Aug 25 01:03:08 PM UTC 24
Finished Aug 25 01:06:25 PM UTC 24
Peak memory 332008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361431850 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1361431850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_error.933944538
Short name T19
Test name
Test status
Simulation time 9668265759 ps
CPU time 502.04 seconds
Started Aug 25 01:03:13 PM UTC 24
Finished Aug 25 01:11:43 PM UTC 24
Peak memory 485688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933944538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.933944538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.2287698317
Short name T234
Test name
Test status
Simulation time 2350648140 ps
CPU time 11.16 seconds
Started Aug 25 01:03:23 PM UTC 24
Finished Aug 25 01:03:35 PM UTC 24
Peak memory 227644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287698317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2287698317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.739960747
Short name T35
Test name
Test status
Simulation time 3472292063 ps
CPU time 62.22 seconds
Started Aug 25 01:03:31 PM UTC 24
Finished Aug 25 01:04:36 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739960747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.739960747 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1283054954
Short name T677
Test name
Test status
Simulation time 151962236404 ps
CPU time 3723.21 seconds
Started Aug 25 01:02:43 PM UTC 24
Finished Aug 25 02:05:36 PM UTC 24
Peak memory 3213612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283054954 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.1283054954 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.4134236393
Short name T74
Test name
Test status
Simulation time 14606972236 ps
CPU time 119.28 seconds
Started Aug 25 01:03:11 PM UTC 24
Finished Aug 25 01:05:13 PM UTC 24
Peak memory 303816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134236393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.4134236393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.3294487130
Short name T23
Test name
Test status
Simulation time 29687316732 ps
CPU time 248.4 seconds
Started Aug 25 01:02:45 PM UTC 24
Finished Aug 25 01:06:57 PM UTC 24
Peak memory 383216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294487130 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3294487130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.1065020738
Short name T231
Test name
Test status
Simulation time 832664635 ps
CPU time 39.25 seconds
Started Aug 25 01:02:42 PM UTC 24
Finished Aug 25 01:03:22 PM UTC 24
Peak memory 233452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065020738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1065020738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.1403822503
Short name T408
Test name
Test status
Simulation time 70209148375 ps
CPU time 1318.4 seconds
Started Aug 25 01:03:36 PM UTC 24
Finished Aug 25 01:25:54 PM UTC 24
Peak memory 627312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403822503 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1403822503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.2925984822
Short name T33
Test name
Test status
Simulation time 299934983 ps
CPU time 36.94 seconds
Started Aug 25 01:03:49 PM UTC 24
Finished Aug 25 01:04:28 PM UTC 24
Peak memory 251712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2925984822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_r
and_reset.2925984822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.3031419672
Short name T244
Test name
Test status
Simulation time 13847738 ps
CPU time 1.21 seconds
Started Aug 25 01:05:48 PM UTC 24
Finished Aug 25 01:05:50 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031419672 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3031419672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_app.1757119900
Short name T237
Test name
Test status
Simulation time 557195505 ps
CPU time 3.7 seconds
Started Aug 25 01:04:39 PM UTC 24
Finished Aug 25 01:04:44 PM UTC 24
Peak memory 229896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757119900 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1757119900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.1509158388
Short name T255
Test name
Test status
Simulation time 5956747376 ps
CPU time 172.16 seconds
Started Aug 25 01:04:45 PM UTC 24
Finished Aug 25 01:07:40 PM UTC 24
Peak memory 317680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509158388 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1509158388 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.3266192462
Short name T368
Test name
Test status
Simulation time 29855417391 ps
CPU time 1006.19 seconds
Started Aug 25 01:04:37 PM UTC 24
Finished Aug 25 01:21:37 PM UTC 24
Peak memory 248116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266192462 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3266192462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.64602008
Short name T247
Test name
Test status
Simulation time 1524403530 ps
CPU time 46.29 seconds
Started Aug 25 01:05:27 PM UTC 24
Finished Aug 25 01:06:16 PM UTC 24
Peak memory 245112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64602008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +
UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.64602008 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.1264810086
Short name T246
Test name
Test status
Simulation time 473903312 ps
CPU time 36.75 seconds
Started Aug 25 01:05:35 PM UTC 24
Finished Aug 25 01:06:14 PM UTC 24
Peak memory 235480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264810086 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1264810086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.3355968323
Short name T248
Test name
Test status
Simulation time 5510905146 ps
CPU time 49.69 seconds
Started Aug 25 01:05:37 PM UTC 24
Finished Aug 25 01:06:28 PM UTC 24
Peak memory 232100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355968323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3355968323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.438592143
Short name T264
Test name
Test status
Simulation time 95126380370 ps
CPU time 212.99 seconds
Started Aug 25 01:04:46 PM UTC 24
Finished Aug 25 01:08:23 PM UTC 24
Peak memory 295224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438592143 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.438592143 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_error.134092118
Short name T162
Test name
Test status
Simulation time 37673205281 ps
CPU time 667.21 seconds
Started Aug 25 01:05:01 PM UTC 24
Finished Aug 25 01:16:18 PM UTC 24
Peak memory 645456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134092118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.134092118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.3566698658
Short name T238
Test name
Test status
Simulation time 3710750025 ps
CPU time 11.64 seconds
Started Aug 25 01:05:13 PM UTC 24
Finished Aug 25 01:05:26 PM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566698658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.3566698658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.475530541
Short name T243
Test name
Test status
Simulation time 68411854 ps
CPU time 1.87 seconds
Started Aug 25 01:05:42 PM UTC 24
Finished Aug 25 01:05:44 PM UTC 24
Peak memory 231404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475530541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.475530541 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3796128411
Short name T640
Test name
Test status
Simulation time 21653350970 ps
CPU time 2979.21 seconds
Started Aug 25 01:04:29 PM UTC 24
Finished Aug 25 01:54:47 PM UTC 24
Peak memory 1444204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796128411 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3796128411 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.1704122819
Short name T274
Test name
Test status
Simulation time 38076544222 ps
CPU time 337.27 seconds
Started Aug 25 01:04:50 PM UTC 24
Finished Aug 25 01:10:33 PM UTC 24
Peak memory 420480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704122819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1704122819 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2218630847
Short name T332
Test name
Test status
Simulation time 100461575829 ps
CPU time 768.47 seconds
Started Aug 25 01:04:33 PM UTC 24
Finished Aug 25 01:17:32 PM UTC 24
Peak memory 661788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218630847 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2218630847 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.3824582739
Short name T193
Test name
Test status
Simulation time 14026472139 ps
CPU time 99.34 seconds
Started Aug 25 01:04:16 PM UTC 24
Finished Aug 25 01:05:57 PM UTC 24
Peak memory 235768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824582739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3824582739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.1495980133
Short name T150
Test name
Test status
Simulation time 27379373496 ps
CPU time 409.73 seconds
Started Aug 25 01:05:44 PM UTC 24
Finished Aug 25 01:12:40 PM UTC 24
Peak memory 312048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495980133 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1495980133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.1228927818
Short name T252
Test name
Test status
Simulation time 221518915 ps
CPU time 1.24 seconds
Started Aug 25 01:07:13 PM UTC 24
Finished Aug 25 01:07:16 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228927818 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1228927818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_app.1187283279
Short name T294
Test name
Test status
Simulation time 12905134617 ps
CPU time 415.92 seconds
Started Aug 25 01:06:14 PM UTC 24
Finished Aug 25 01:13:17 PM UTC 24
Peak memory 450860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187283279 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1187283279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1790396152
Short name T269
Test name
Test status
Simulation time 17653950680 ps
CPU time 200.81 seconds
Started Aug 25 01:06:16 PM UTC 24
Finished Aug 25 01:09:41 PM UTC 24
Peak memory 272764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790396152 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1790396152 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.3843315711
Short name T366
Test name
Test status
Simulation time 52443946039 ps
CPU time 918.03 seconds
Started Aug 25 01:06:04 PM UTC 24
Finished Aug 25 01:21:35 PM UTC 24
Peak memory 258424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843315711 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3843315711 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3082488268
Short name T256
Test name
Test status
Simulation time 5035949073 ps
CPU time 46.67 seconds
Started Aug 25 01:06:58 PM UTC 24
Finished Aug 25 01:07:47 PM UTC 24
Peak memory 251920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082488268 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3082488268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.983033330
Short name T251
Test name
Test status
Simulation time 1572354241 ps
CPU time 15.51 seconds
Started Aug 25 01:06:58 PM UTC 24
Finished Aug 25 01:07:15 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983033330 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.983033330 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.3521376671
Short name T253
Test name
Test status
Simulation time 4338449999 ps
CPU time 21.01 seconds
Started Aug 25 01:07:01 PM UTC 24
Finished Aug 25 01:07:23 PM UTC 24
Peak memory 235852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521376671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3521376671 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3284966144
Short name T282
Test name
Test status
Simulation time 18003050122 ps
CPU time 349.86 seconds
Started Aug 25 01:06:27 PM UTC 24
Finished Aug 25 01:12:22 PM UTC 24
Peak memory 319800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284966144 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3284966144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_error.3351548551
Short name T348
Test name
Test status
Simulation time 20144671811 ps
CPU time 727.45 seconds
Started Aug 25 01:06:48 PM UTC 24
Finished Aug 25 01:19:06 PM UTC 24
Peak memory 690420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351548551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3351548551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.1777406864
Short name T250
Test name
Test status
Simulation time 722889249 ps
CPU time 3.6 seconds
Started Aug 25 01:06:57 PM UTC 24
Finished Aug 25 01:07:02 PM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777406864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1777406864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.4052010400
Short name T36
Test name
Test status
Simulation time 406738244 ps
CPU time 2.12 seconds
Started Aug 25 01:07:03 PM UTC 24
Finished Aug 25 01:07:06 PM UTC 24
Peak memory 231856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052010400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.4052010400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3697651711
Short name T715
Test name
Test status
Simulation time 176776932219 ps
CPU time 5895.57 seconds
Started Aug 25 01:05:56 PM UTC 24
Finished Aug 25 02:45:27 PM UTC 24
Peak memory 4333968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697651711 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3697651711 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.3175485515
Short name T284
Test name
Test status
Simulation time 36991895442 ps
CPU time 353.33 seconds
Started Aug 25 01:06:29 PM UTC 24
Finished Aug 25 01:12:28 PM UTC 24
Peak memory 412296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175485515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3175485515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.598874409
Short name T190
Test name
Test status
Simulation time 68576662161 ps
CPU time 511.47 seconds
Started Aug 25 01:05:58 PM UTC 24
Finished Aug 25 01:14:38 PM UTC 24
Peak memory 547128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598874409 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.598874409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.3993884263
Short name T245
Test name
Test status
Simulation time 850147541 ps
CPU time 10.95 seconds
Started Aug 25 01:05:51 PM UTC 24
Finished Aug 25 01:06:03 PM UTC 24
Peak memory 231876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993884263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3993884263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.1198757846
Short name T278
Test name
Test status
Simulation time 67122436356 ps
CPU time 269.37 seconds
Started Aug 25 01:07:09 PM UTC 24
Finished Aug 25 01:11:43 PM UTC 24
Peak memory 332492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198757846 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1198757846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_24/kmac_masked-sim-vcs/9.kmac_stress_all/latest
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