Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16830068	1			T3	129		T11	118		T9	434
all_values[1]	16830068	1			T3	129		T11	118		T9	434
all_values[2]	16830068	1			T3	129		T11	118		T9	434

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

478753

1

T3

67

T11

236

T9

189

auto[1]

50011451

1

T3

320

T11

118

T9

1113

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50280396

1

T3

375

T11

336

T9

1293

auto[1]

209808

1

T3

12

T11

18

T9

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	161117	1			T11	112		T37	1		T4	3
all_values[0]	auto[0]	auto[1]	1346	1			T11	6		T37	2		T39	6
all_values[0]	auto[1]	auto[0]	16599015	1			T3	125		T9	431		T37	909
all_values[0]	auto[1]	auto[1]	68590	1			T3	4		T9	3		T37	107
all_values[1]	auto[0]	auto[0]	140032	1			T3	59		T9	187		T37	1
all_values[1]	auto[0]	auto[1]	984	1			T3	2		T9	2		T37	2
all_values[1]	auto[1]	auto[0]	16620100	1			T3	66		T11	112		T9	244
all_values[1]	auto[1]	auto[1]	68952	1			T3	2		T11	6		T9	1
all_values[2]	auto[0]	auto[0]	174280	1			T3	5		T11	112		T4	1
all_values[2]	auto[0]	auto[1]	994	1			T3	1		T11	6		T39	4
all_values[2]	auto[1]	auto[0]	16585852	1			T3	120		T9	431		T37	910
all_values[2]	auto[1]	auto[1]	68942	1			T3	3		T9	3		T37	109