Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57002 1 T3 2 T11 6 T9 2
auto[1] 49782 1 T3 4 T9 6 T40 4



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 26721 1 T11 5 T37 28 T4 18
lower_val 26410 1 T3 5 T9 2 T37 35
zero_val 847 1 T3 1 T11 1 T9 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 41198 1 T37 70 T4 46 T39 4
lower_val 40390 1 T3 2 T11 6 T37 76
zero_val 25196 1 T3 4 T9 8 T40 4



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 7197 1 T37 16 T4 11 T39 1
higher_val higher_val auto[1] 3054 1 T23 1 T94 20 T53 20
higher_val lower_val auto[0] 6962 1 T11 5 T37 12 T4 7
higher_val lower_val auto[1] 3212 1 T94 26 T53 14 T54 1
higher_val zero_val auto[0] 48 1 T54 1 T28 1 T146 1
higher_val zero_val auto[1] 6248 1 T23 1 T94 36 T53 38
lower_val higher_val auto[0] 7201 1 T37 14 T4 14 T27 14
lower_val higher_val auto[1] 3091 1 T40 1 T23 1 T94 20
lower_val lower_val auto[0] 6854 1 T37 21 T4 6 T27 8
lower_val lower_val auto[1] 3102 1 T3 2 T43 1 T23 1
lower_val zero_val auto[0] 63 1 T3 1 T9 1 T198 1
lower_val zero_val auto[1] 6099 1 T3 2 T9 1 T40 1
zero_val higher_val auto[0] 263 1 T37 1 T4 1 T27 1
zero_val higher_val auto[1] 67 1 T28 3 T199 1 T200 1
zero_val lower_val auto[0] 270 1 T11 1 T39 1 T12 1
zero_val lower_val auto[1] 44 1 T198 1 T20 2 T28 3
zero_val zero_val auto[0] 149 1 T3 1 T9 1 T40 1
zero_val zero_val auto[1] 54 1 T198 1 T15 2 T199 1

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