Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16830068	1			T3	129		T11	118		T9	434
all_pins[1]	16830068	1			T3	129		T11	118		T9	434
all_pins[2]	16830068	1			T3	129		T11	118		T9	434

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50174818	1			T3	382		T11	354		T9	869
values[0x1]	315386	1			T3	5		T9	433		T37	107
transitions[0x0=>0x1]	313674	1			T3	5		T9	429		T37	107
transitions[0x1=>0x0]	313703	1			T3	5		T9	430		T37	107

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16761478	1			T3	125		T11	118		T9	431
all_pins[0]	values[0x1]	68590	1			T3	4		T9	3		T37	107
all_pins[0]	transitions[0x0=>0x1]	68583	1			T3	4		T9	3		T37	107
all_pins[0]	transitions[0x1=>0x0]	6060	1			T3	1		T43	2		T69	18
all_pins[1]	values[0x0]	16824001	1			T3	128		T11	118		T9	434
all_pins[1]	values[0x1]	6067	1			T3	1		T43	2		T69	18
all_pins[1]	transitions[0x0=>0x1]	5845	1			T3	1		T43	2		T69	18
all_pins[1]	transitions[0x1=>0x0]	240507	1			T9	430		T19	80		T13	453
all_pins[2]	values[0x0]	16589339	1			T3	129		T11	118		T9	4
all_pins[2]	values[0x1]	240729	1			T9	430		T19	80		T13	453
all_pins[2]	transitions[0x0=>0x1]	239246	1			T9	426		T19	80		T13	449
all_pins[2]	transitions[0x1=>0x0]	67136	1			T3	4		T37	107		T40	5