Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::state_read_mask_cg

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
share	2	0	2	100.00	100	1	1	2
state_read_mask	4	0	4	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_mask_share_cross	8	0	8	100.00	100	1	1	0

Summary for Variable share

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for share

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6261617

1

T3

48

T11

48

T9

450

auto[1]

6261582

1

T3

48

T11

48

T9

450

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Summary for Variable state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for state_read_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	12461921	1			T3	96		T11	96		T9	896
triple_byte_access	20528	1			T9	2		T27	18		T12	2
halfword_access	20196	1			T27	14		T19	6		T71	6
byte_access	20554	1			T9	2		T27	24		T12	4

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Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for state_mask_share_cross

Bins

share	state_read_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	6230978	1			T3	48		T11	48		T9	448
auto[0]	triple_byte_access	10264	1			T9	1		T27	9		T12	1
auto[0]	halfword_access	10098	1			T27	7		T19	3		T71	3
auto[0]	byte_access	10277	1			T9	1		T27	12		T12	2
auto[1]	word_access	6230943	1			T3	48		T11	48		T9	448
auto[1]	triple_byte_access	10264	1			T9	1		T27	9		T12	1
auto[1]	halfword_access	10098	1			T27	7		T19	3		T71	3
auto[1]	byte_access	10277	1			T9	1		T27	12		T12	2