| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.10 | 97.89 | 92.55 | 99.89 | 76.06 | 95.53 | 98.89 | 97.88 |
| T138 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2767737314 | Aug 27 07:03:00 AM UTC 24 | Aug 27 07:03:05 AM UTC 24 | 195528297 ps | ||
| T764 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4178842204 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 37698149 ps | ||
| T765 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4133191097 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 38336376 ps | ||
| T766 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1607645500 | Aug 27 07:02:57 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 142036056 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.3568282807 | Aug 27 07:03:01 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 152120862 ps | ||
| T767 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3532213097 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 45234409 ps | ||
| T768 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.513037092 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:06 AM UTC 24 | 285942193 ps | ||
| T769 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.4127456845 | Aug 27 07:02:56 AM UTC 24 | Aug 27 07:03:07 AM UTC 24 | 1000696914 ps | ||
| T770 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.4155674037 | Aug 27 07:02:49 AM UTC 24 | Aug 27 07:03:07 AM UTC 24 | 1014139863 ps | ||
| T771 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2696093687 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:07 AM UTC 24 | 91407226 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1014319234 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:07 AM UTC 24 | 331869011 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3228428260 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:11 AM UTC 24 | 16434347 ps | ||
| T772 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1549191872 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:11 AM UTC 24 | 38693516 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3572266752 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:11 AM UTC 24 | 33792828 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3662442343 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:12 AM UTC 24 | 143084259 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3473156983 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:12 AM UTC 24 | 133301147 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1816738220 | Aug 27 07:03:08 AM UTC 24 | Aug 27 07:03:13 AM UTC 24 | 811616380 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3770220046 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:15 AM UTC 24 | 27500809 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3208296049 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 34991092 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.997357308 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 16375394 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2482440919 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 92207662 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2942286629 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 24182843 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1509008016 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 46393251 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.382573727 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:16 AM UTC 24 | 462360762 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.59452559 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 57894917 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1678167544 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 263196875 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.506906238 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 90175513 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1341781696 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 29542723 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.522494946 | Aug 27 07:03:02 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 114411227 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.643075098 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:17 AM UTC 24 | 36661070 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2173164983 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:18 AM UTC 24 | 207366017 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1504666603 | Aug 27 07:03:13 AM UTC 24 | Aug 27 07:03:19 AM UTC 24 | 303110849 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2200530450 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:20 AM UTC 24 | 379412497 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2958867453 | Aug 27 07:03:16 AM UTC 24 | Aug 27 07:03:21 AM UTC 24 | 65634863 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.855494918 | Aug 27 07:03:12 AM UTC 24 | Aug 27 07:03:21 AM UTC 24 | 31867753 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1109181907 | Aug 27 07:03:16 AM UTC 24 | Aug 27 07:03:21 AM UTC 24 | 57677819 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.344183889 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:21 AM UTC 24 | 31642469 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2188558052 | Aug 27 07:03:12 AM UTC 24 | Aug 27 07:03:22 AM UTC 24 | 25837088 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4070546657 | Aug 27 07:03:12 AM UTC 24 | Aug 27 07:03:22 AM UTC 24 | 417111519 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.674219951 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:23 AM UTC 24 | 232450606 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.656192683 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:25 AM UTC 24 | 265102618 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1778746526 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:26 AM UTC 24 | 40300011 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1781120270 | Aug 27 07:03:13 AM UTC 24 | Aug 27 07:03:26 AM UTC 24 | 694387357 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4286304329 | Aug 27 07:03:04 AM UTC 24 | Aug 27 07:03:27 AM UTC 24 | 48857343 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1080767810 | Aug 27 07:03:21 AM UTC 24 | Aug 27 07:03:27 AM UTC 24 | 40301789 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.77651250 | Aug 27 07:03:13 AM UTC 24 | Aug 27 07:03:27 AM UTC 24 | 148870896 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2068638487 | Aug 27 07:03:14 AM UTC 24 | Aug 27 07:03:27 AM UTC 24 | 74348026 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1689198109 | Aug 27 07:03:22 AM UTC 24 | Aug 27 07:03:31 AM UTC 24 | 21241864 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2008886780 | Aug 27 07:03:22 AM UTC 24 | Aug 27 07:03:31 AM UTC 24 | 68576946 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2617708873 | Aug 27 07:03:28 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 100184843 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.4209693861 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 12663894 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.470425865 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 173457335 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.202535413 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 87266988 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1400230337 | Aug 27 07:03:20 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 20085987 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2245950147 | Aug 27 07:03:18 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 252196973 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2453552043 | Aug 27 07:03:22 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 54383016 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.233735563 | Aug 27 07:03:20 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 62503845 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2904879910 | Aug 27 07:03:22 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 263579642 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.932706833 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 49332520 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3610305611 | Aug 27 07:03:06 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 185522888 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1154613834 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 36199832 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2319473997 | Aug 27 07:03:20 AM UTC 24 | Aug 27 07:03:32 AM UTC 24 | 92433237 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3026494645 | Aug 27 07:03:22 AM UTC 24 | Aug 27 07:03:33 AM UTC 24 | 412022457 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.707052374 | Aug 27 07:03:03 AM UTC 24 | Aug 27 07:03:33 AM UTC 24 | 522424370 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1166837773 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:33 AM UTC 24 | 241547280 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2730517782 | Aug 27 07:03:18 AM UTC 24 | Aug 27 07:03:33 AM UTC 24 | 264137128 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4082008686 | Aug 27 07:03:07 AM UTC 24 | Aug 27 07:03:34 AM UTC 24 | 122028641 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1540127103 | Aug 27 07:03:20 AM UTC 24 | Aug 27 07:03:35 AM UTC 24 | 262600610 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2350988003 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:35 AM UTC 24 | 15050508 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1080029887 | Aug 27 07:03:27 AM UTC 24 | Aug 27 07:03:36 AM UTC 24 | 52345203 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3684914442 | Aug 27 07:03:27 AM UTC 24 | Aug 27 07:03:37 AM UTC 24 | 73415493 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.174234788 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:37 AM UTC 24 | 295853193 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1422457389 | Aug 27 07:03:27 AM UTC 24 | Aug 27 07:03:38 AM UTC 24 | 349916268 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1020524459 | Aug 27 07:03:36 AM UTC 24 | Aug 27 07:03:41 AM UTC 24 | 23806892 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1167108926 | Aug 27 07:03:39 AM UTC 24 | Aug 27 07:03:41 AM UTC 24 | 16912453 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1453797585 | Aug 27 07:03:36 AM UTC 24 | Aug 27 07:03:41 AM UTC 24 | 14137009 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.987013892 | Aug 27 07:03:36 AM UTC 24 | Aug 27 07:03:41 AM UTC 24 | 16496051 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2394134059 | Aug 27 07:03:32 AM UTC 24 | Aug 27 07:03:41 AM UTC 24 | 103653733 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.894626695 | Aug 27 07:03:37 AM UTC 24 | Aug 27 07:03:42 AM UTC 24 | 12921383 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.753277560 | Aug 27 07:03:37 AM UTC 24 | Aug 27 07:03:42 AM UTC 24 | 11246267 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.320404486 | Aug 27 07:03:20 AM UTC 24 | Aug 27 07:03:44 AM UTC 24 | 1558435824 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1700210549 | Aug 27 07:03:27 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 13970672 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2955645773 | Aug 27 07:03:40 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 14693224 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3321230415 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 13526935 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3539414922 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 39369368 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2188511231 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 57328900 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.4150948541 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 48995063 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.778439518 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:45 AM UTC 24 | 116326484 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.1434360934 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 16298071 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1263265086 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 52583549 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1514991387 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 16003847 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.589229510 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 30206536 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3473753787 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 12819209 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1819490257 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 48531268 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.486227742 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 16973401 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1854977545 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 35573074 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.251896492 | Aug 27 07:03:33 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 17081342 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1463222162 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 44286104 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1045994925 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 15382976 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1525269663 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 23369930 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.989778645 | Aug 27 07:03:23 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 14892136 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1594170856 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:03:46 AM UTC 24 | 40210970 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1612396210 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:03:47 AM UTC 24 | 93992065 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1561215802 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:03:47 AM UTC 24 | 46385677 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3296839558 | Aug 27 07:03:27 AM UTC 24 | Aug 27 07:03:47 AM UTC 24 | 97993746 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3680714202 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:03:47 AM UTC 24 | 122553456 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1423496581 | Aug 27 07:03:34 AM UTC 24 | Aug 27 07:03:56 AM UTC 24 | 68463405 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4124030178 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:03:57 AM UTC 24 | 210749243 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2633409101 | Aug 27 07:03:24 AM UTC 24 | Aug 27 07:03:57 AM UTC 24 | 124200522 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3329183351 | Aug 27 07:03:42 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 42036813 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.321456849 | Aug 27 07:03:41 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 38461355 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3709597729 | Aug 27 07:03:42 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 36795797 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2808862572 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 199087125 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4163808469 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 26524364 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3621083708 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:04:04 AM UTC 24 | 181071258 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1166662344 | Aug 27 07:03:35 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 11765269 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.518304711 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 109452157 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1438204196 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 14128528 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4245461570 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 248999066 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2353574764 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 42750556 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1299982270 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:05 AM UTC 24 | 49331527 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1329051593 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:06 AM UTC 24 | 26359568 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2017364619 | Aug 27 07:03:25 AM UTC 24 | Aug 27 07:04:06 AM UTC 24 | 150340577 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3396366010 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:06 AM UTC 24 | 320775039 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.609532093 | Aug 27 07:03:17 AM UTC 24 | Aug 27 07:04:07 AM UTC 24 | 152270354 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.230973601 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:07 AM UTC 24 | 234166674 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.120360866 | Aug 27 07:03:05 AM UTC 24 | Aug 27 07:04:09 AM UTC 24 | 510958968 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2194107154 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5760800410 ps |
| CPU time | 15.23 seconds |
| Started | Aug 27 05:00:55 PM UTC 24 |
| Finished | Aug 27 05:01:11 PM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194107154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2194107154 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.1029492001 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1115972472 ps |
| CPU time | 31.43 seconds |
| Started | Aug 27 05:00:56 PM UTC 24 |
| Finished | Aug 27 05:01:29 PM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029492001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1029492001 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3745278748 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 355845731 ps |
| CPU time | 4.19 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:54 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745278748 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3745278748 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.2150152829 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1219098474 ps |
| CPU time | 6.65 seconds |
| Started | Aug 27 05:00:54 PM UTC 24 |
| Finished | Aug 27 05:01:02 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150152829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2150152829 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3237390785 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 81706998853 ps |
| CPU time | 149.25 seconds |
| Started | Aug 27 05:02:12 PM UTC 24 |
| Finished | Aug 27 05:04:44 PM UTC 24 |
| Peak memory | 311672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237390785 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3237390785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.465069406 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 16134370972 ps |
| CPU time | 227.08 seconds |
| Started | Aug 27 05:07:35 PM UTC 24 |
| Finished | Aug 27 05:11:26 PM UTC 24 |
| Peak memory | 285384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=465069406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_ra nd_reset.465069406 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.386453551 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 17072527574 ps |
| CPU time | 76.76 seconds |
| Started | Aug 27 05:06:43 PM UTC 24 |
| Finished | Aug 27 05:08:02 PM UTC 24 |
| Peak memory | 292416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386453551 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.386453551 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1110593684 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 233977190 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110593684 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.1110 593684 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_error.98138960 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 23778127978 ps |
| CPU time | 455.89 seconds |
| Started | Aug 27 05:00:54 PM UTC 24 |
| Finished | Aug 27 05:08:36 PM UTC 24 |
| Peak memory | 377144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98138960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.98138960 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.279963574 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 411974201 ps |
| CPU time | 1.92 seconds |
| Started | Aug 27 05:15:47 PM UTC 24 |
| Finished | Aug 27 05:15:50 PM UTC 24 |
| Peak memory | 233332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279963574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.279963574 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.1448095878 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8302567549 ps |
| CPU time | 156.06 seconds |
| Started | Aug 27 05:00:58 PM UTC 24 |
| Finished | Aug 27 05:03:37 PM UTC 24 |
| Peak memory | 293100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448095878 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1448095878 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.3577989545 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 54007943 ps |
| CPU time | 2.03 seconds |
| Started | Aug 27 05:12:22 PM UTC 24 |
| Finished | Aug 27 05:12:26 PM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577989545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.3577989545 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.3228428260 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 16434347 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:11 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228428260 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3228428260 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.1621928312 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 25496537 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 05:00:54 PM UTC 24 |
| Finished | Aug 27 05:00:57 PM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621928312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1621928312 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.705376394 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 32938283 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:23:01 PM UTC 24 |
| Finished | Aug 27 05:23:04 PM UTC 24 |
| Peak memory | 231308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705376394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.705376394 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3098365261 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 159884549 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 05:02:39 PM UTC 24 |
| Finished | Aug 27 05:02:42 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098365261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3098365261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1650758665 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6248713263 ps |
| CPU time | 51.25 seconds |
| Started | Aug 27 05:01:05 PM UTC 24 |
| Finished | Aug 27 05:01:58 PM UTC 24 |
| Peak memory | 241912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650758665 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1650758665 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2097784816 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 151988633 ps |
| CPU time | 1.53 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:00 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097784816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2097784816 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.2053557262 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 45465990 ps |
| CPU time | 1.93 seconds |
| Started | Aug 27 05:04:27 PM UTC 24 |
| Finished | Aug 27 05:04:30 PM UTC 24 |
| Peak memory | 229324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053557262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2053557262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.793582738 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 17747908 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 07:02:48 AM UTC 24 |
| Finished | Aug 27 07:02:50 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793582738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.793582738 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.4028166722 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 17427889 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 05:00:57 PM UTC 24 |
| Finished | Aug 27 05:00:59 PM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028166722 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4028166722 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.3397609730 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 54199629 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 05:17:32 PM UTC 24 |
| Finished | Aug 27 05:17:36 PM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397609730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3397609730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.1117473375 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 79811536 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 05:37:00 PM UTC 24 |
| Finished | Aug 27 05:37:03 PM UTC 24 |
| Peak memory | 231768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117473375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1117473375 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_error.145493450 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1579746305 ps |
| CPU time | 23.6 seconds |
| Started | Aug 27 05:01:16 PM UTC 24 |
| Finished | Aug 27 05:01:41 PM UTC 24 |
| Peak memory | 262388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145493450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.145493450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2767737314 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 195528297 ps |
| CPU time | 3.58 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767737314 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.2767737314 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.2516520244 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 23728673635 ps |
| CPU time | 601.29 seconds |
| Started | Aug 27 05:01:42 PM UTC 24 |
| Finished | Aug 27 05:11:51 PM UTC 24 |
| Peak memory | 243936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516520244 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2516520244 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.455698259 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 35552552694 ps |
| CPU time | 389.16 seconds |
| Started | Aug 27 05:33:28 PM UTC 24 |
| Finished | Aug 27 05:40:03 PM UTC 24 |
| Peak memory | 465180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455698259 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.455698259 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.4239432146 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 26967507130 ps |
| CPU time | 298.92 seconds |
| Started | Aug 27 05:01:12 PM UTC 24 |
| Finished | Aug 27 05:06:15 PM UTC 24 |
| Peak memory | 325876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239432146 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.4239432146 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2520981760 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 31262960102 ps |
| CPU time | 372.14 seconds |
| Started | Aug 27 05:05:48 PM UTC 24 |
| Finished | Aug 27 05:12:05 PM UTC 24 |
| Peak memory | 500004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520981760 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2520981760 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3532213097 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 45234409 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532213097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.3532213097 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.2616858570 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 137901264 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:54 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616858570 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.2616858570 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.344183889 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 31642469 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:21 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344183889 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.344183889 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.2640314313 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 8492639696 ps |
| CPU time | 115.4 seconds |
| Started | Aug 27 05:19:07 PM UTC 24 |
| Finished | Aug 27 05:21:05 PM UTC 24 |
| Peak memory | 237940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640314313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2640314313 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.1647830424 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15098303172 ps |
| CPU time | 300.31 seconds |
| Started | Aug 27 05:01:15 PM UTC 24 |
| Finished | Aug 27 05:06:19 PM UTC 24 |
| Peak memory | 459448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647830424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1647830424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.609532093 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 152270354 ps |
| CPU time | 3.98 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:04:07 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609532093 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.609532093 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_error.1865389993 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3290471965 ps |
| CPU time | 300.53 seconds |
| Started | Aug 27 05:15:35 PM UTC 24 |
| Finished | Aug 27 05:20:40 PM UTC 24 |
| Peak memory | 327904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865389993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1865389993 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1083610271 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 17379868 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:51 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083610271 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1083610271 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.1499128005 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 842808814 ps |
| CPU time | 7.58 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499128005 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1499128005 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.4155674037 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1014139863 ps |
| CPU time | 16.75 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:03:07 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155674037 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.4155674037 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.390948733 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 170163338 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:54 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=390948733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_r w_with_rand_reset.390948733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.3810479220 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 19342411 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:51 AM UTC 24 |
| Peak memory | 224284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810479220 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3810479220 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1598033476 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 20117662 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:51 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598033476 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1598033476 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.4266856392 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 14245584 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 07:02:48 AM UTC 24 |
| Finished | Aug 27 07:02:50 AM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266856392 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.4266856392 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.528962435 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 43106195 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:52 AM UTC 24 |
| Peak memory | 224568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528962435 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.528962435 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1580583276 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 96760705 ps |
| CPU time | 1.56 seconds |
| Started | Aug 27 07:02:48 AM UTC 24 |
| Finished | Aug 27 07:02:50 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580583276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1580583276 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1416293980 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 273309984 ps |
| CPU time | 2.28 seconds |
| Started | Aug 27 07:02:48 AM UTC 24 |
| Finished | Aug 27 07:02:51 AM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416293980 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.1416 293980 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2494436405 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 207143392 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 07:02:49 AM UTC 24 |
| Finished | Aug 27 07:02:52 AM UTC 24 |
| Peak memory | 225684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494436405 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2494436405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1354392365 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1649720452 ps |
| CPU time | 8.95 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354392365 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1354392365 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.1507035116 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1511755578 ps |
| CPU time | 11.94 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507035116 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1507035116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2503167733 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 41559365 ps |
| CPU time | 1.42 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503167733 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2503167733 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2510057018 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 44327891 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:54 AM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2510057018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_ rw_with_rand_reset.2510057018 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2436491855 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 37776905 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436491855 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2436491855 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2026162602 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 14233136 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026162602 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2026162602 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.42957900 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 55684930 ps |
| CPU time | 1.61 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42957900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.42957900 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.4258235141 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 31513961 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:52 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258235141 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.4258235141 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3960054825 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 95670910 ps |
| CPU time | 1.93 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:55 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960054825 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3960054825 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3795316785 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 81609758 ps |
| CPU time | 1.32 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:52 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795316785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3795316785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3719207446 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 179753299 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719207446 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3719 207446 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2068686876 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 61092794 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 07:02:50 AM UTC 24 |
| Finished | Aug 27 07:02:55 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068686876 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2068686876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1678167544 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 263196875 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 226616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1678167544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem _rw_with_rand_reset.1678167544 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1509008016 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 46393251 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509008016 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1509008016 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.997357308 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 16375394 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 224708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997357308 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.997357308 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1341781696 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 29542723 ps |
| CPU time | 1.37 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341781696 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1341781696 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2696093687 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 91407226 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:07 AM UTC 24 |
| Peak memory | 230008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696093687 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.269 6093687 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2173164983 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 207366017 ps |
| CPU time | 3.11 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:18 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173164983 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2173164983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2200530450 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 379412497 ps |
| CPU time | 4.66 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:20 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200530450 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2200530450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1329051593 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 26359568 ps |
| CPU time | 2.03 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:06 AM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1329051593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem _rw_with_rand_reset.1329051593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1438204196 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 14128528 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438204196 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1438204196 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.518304711 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 109452157 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518304711 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.518304711 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1299982270 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 49331527 ps |
| CPU time | 1.72 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299982270 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1299982270 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1778746526 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 40300011 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:26 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778746526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1778746526 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4286304329 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 48857343 ps |
| CPU time | 1.39 seconds |
| Started | Aug 27 07:03:04 AM UTC 24 |
| Finished | Aug 27 07:03:27 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286304329 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.428 6304329 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.230973601 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 234166674 ps |
| CPU time | 3.41 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:07 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230973601 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.230973601 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.120360866 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 510958968 ps |
| CPU time | 5 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:09 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120360866 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.120360866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.932706833 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 49332520 ps |
| CPU time | 1.39 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=932706833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_ rw_with_rand_reset.932706833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.470425865 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 173457335 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470425865 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.470425865 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3610305611 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 185522888 ps |
| CPU time | 1.43 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610305611 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3610305611 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2353574764 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 42750556 ps |
| CPU time | 1.65 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353574764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2353574764 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.3396366010 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 320775039 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 07:03:05 AM UTC 24 |
| Finished | Aug 27 07:04:06 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396366010 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.339 6366010 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.674219951 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 232450606 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:23 AM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674219951 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.674219951 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.656192683 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 265102618 ps |
| CPU time | 4.27 seconds |
| Started | Aug 27 07:03:06 AM UTC 24 |
| Finished | Aug 27 07:03:25 AM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656192683 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.656192683 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3662442343 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 143084259 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:12 AM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3662442343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem _rw_with_rand_reset.3662442343 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3208296049 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 34991092 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208296049 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3208296049 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.4209693861 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 12663894 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209693861 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4209693861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.643075098 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 36661070 ps |
| CPU time | 2.03 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643075098 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.643075098 +enable_mask ing=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.202535413 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 87266988 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202535413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.202535413 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1154613834 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 36199832 ps |
| CPU time | 1.38 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 226608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154613834 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.115 4613834 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.4082008686 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 122028641 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:34 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082008686 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4082008686 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.1166837773 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 241547280 ps |
| CPU time | 2.53 seconds |
| Started | Aug 27 07:03:07 AM UTC 24 |
| Finished | Aug 27 07:03:33 AM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166837773 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1166837773 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2188558052 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 25837088 ps |
| CPU time | 1.4 seconds |
| Started | Aug 27 07:03:12 AM UTC 24 |
| Finished | Aug 27 07:03:22 AM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2188558052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem _rw_with_rand_reset.2188558052 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.855494918 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 31867753 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:03:12 AM UTC 24 |
| Finished | Aug 27 07:03:21 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855494918 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.855494918 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4070546657 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 417111519 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 07:03:12 AM UTC 24 |
| Finished | Aug 27 07:03:22 AM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070546657 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.4070546657 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1549191872 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 38693516 ps |
| CPU time | 0.8 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:11 AM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549191872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.1549191872 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3572266752 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 33792828 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:11 AM UTC 24 |
| Peak memory | 228540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572266752 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.357 2266752 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1816738220 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 811616380 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:13 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816738220 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1816738220 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3473156983 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 133301147 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 07:03:08 AM UTC 24 |
| Finished | Aug 27 07:03:12 AM UTC 24 |
| Peak memory | 225184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473156983 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3473156983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1561215802 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 46385677 ps |
| CPU time | 1.44 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:03:47 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1561215802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem _rw_with_rand_reset.1561215802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1109181907 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 57677819 ps |
| CPU time | 0.8 seconds |
| Started | Aug 27 07:03:16 AM UTC 24 |
| Finished | Aug 27 07:03:21 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109181907 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1109181907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2958867453 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 65634863 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:16 AM UTC 24 |
| Finished | Aug 27 07:03:21 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958867453 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2958867453 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4124030178 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 210749243 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:03:57 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124030178 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.4124030178 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1781120270 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 694387357 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 07:03:13 AM UTC 24 |
| Finished | Aug 27 07:03:26 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781120270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.1781120270 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.77651250 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 148870896 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 07:03:13 AM UTC 24 |
| Finished | Aug 27 07:03:27 AM UTC 24 |
| Peak memory | 228536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77651250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.77651 250 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.1504666603 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 303110849 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 07:03:13 AM UTC 24 |
| Finished | Aug 27 07:03:19 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504666603 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1504666603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2068638487 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 74348026 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 07:03:14 AM UTC 24 |
| Finished | Aug 27 07:03:27 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068638487 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2068638487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3621083708 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 181071258 ps |
| CPU time | 1.6 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 230708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3621083708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem _rw_with_rand_reset.3621083708 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2808862572 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 199087125 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808862572 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2808862572 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.1594170856 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 40210970 ps |
| CPU time | 0.75 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594170856 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.1594170856 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4163808469 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 26524364 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163808469 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.4163808469 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1612396210 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 93992065 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:03:47 AM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612396210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1612396210 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.4245461570 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 248999066 ps |
| CPU time | 2.71 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 230196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245461570 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.424 5461570 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3680714202 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 122553456 ps |
| CPU time | 1.79 seconds |
| Started | Aug 27 07:03:17 AM UTC 24 |
| Finished | Aug 27 07:03:47 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680714202 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3680714202 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1080767810 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 40301789 ps |
| CPU time | 1.79 seconds |
| Started | Aug 27 07:03:21 AM UTC 24 |
| Finished | Aug 27 07:03:27 AM UTC 24 |
| Peak memory | 230764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1080767810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem _rw_with_rand_reset.1080767810 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.233735563 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 62503845 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:03:20 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233735563 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.233735563 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.1400230337 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 20085987 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 07:03:20 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400230337 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1400230337 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2319473997 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 92433237 ps |
| CPU time | 1.31 seconds |
| Started | Aug 27 07:03:20 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319473997 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2319473997 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2245950147 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 252196973 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 07:03:18 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245950147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2245950147 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2730517782 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 264137128 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 07:03:18 AM UTC 24 |
| Finished | Aug 27 07:03:33 AM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730517782 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.273 0517782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.320404486 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1558435824 ps |
| CPU time | 3.27 seconds |
| Started | Aug 27 07:03:20 AM UTC 24 |
| Finished | Aug 27 07:03:44 AM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320404486 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.320404486 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1540127103 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 262600610 ps |
| CPU time | 4.3 seconds |
| Started | Aug 27 07:03:20 AM UTC 24 |
| Finished | Aug 27 07:03:35 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540127103 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1540127103 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2017364619 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 150340577 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 07:03:25 AM UTC 24 |
| Finished | Aug 27 07:04:06 AM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2017364619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem _rw_with_rand_reset.2017364619 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.989778645 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 14892136 ps |
| CPU time | 0.83 seconds |
| Started | Aug 27 07:03:23 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989778645 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.989778645 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1689198109 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 21241864 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:22 AM UTC 24 |
| Finished | Aug 27 07:03:31 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689198109 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1689198109 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2633409101 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 124200522 ps |
| CPU time | 1.91 seconds |
| Started | Aug 27 07:03:24 AM UTC 24 |
| Finished | Aug 27 07:03:57 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633409101 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2633409101 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2008886780 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 68576946 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 07:03:22 AM UTC 24 |
| Finished | Aug 27 07:03:31 AM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008886780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2008886780 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2904879910 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 263579642 ps |
| CPU time | 1.7 seconds |
| Started | Aug 27 07:03:22 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904879910 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.290 4879910 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2453552043 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 54383016 ps |
| CPU time | 1.58 seconds |
| Started | Aug 27 07:03:22 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 223024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453552043 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2453552043 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3026494645 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 412022457 ps |
| CPU time | 2.48 seconds |
| Started | Aug 27 07:03:22 AM UTC 24 |
| Finished | Aug 27 07:03:33 AM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026494645 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3026494645 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.174234788 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 295853193 ps |
| CPU time | 2.08 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:37 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=174234788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_ rw_with_rand_reset.174234788 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2617708873 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 100184843 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:03:28 AM UTC 24 |
| Finished | Aug 27 07:03:32 AM UTC 24 |
| Peak memory | 224556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617708873 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2617708873 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1700210549 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13970672 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:27 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700210549 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1700210549 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.2394134059 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 103653733 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 07:03:32 AM UTC 24 |
| Finished | Aug 27 07:03:41 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394134059 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.2394134059 +enable_ma sking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1080029887 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 52345203 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 07:03:27 AM UTC 24 |
| Finished | Aug 27 07:03:36 AM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080029887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.1080029887 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.3296839558 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 97993746 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 07:03:27 AM UTC 24 |
| Finished | Aug 27 07:03:47 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296839558 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.329 6839558 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3684914442 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 73415493 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 07:03:27 AM UTC 24 |
| Finished | Aug 27 07:03:37 AM UTC 24 |
| Peak memory | 224684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684914442 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3684914442 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1422457389 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 349916268 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 07:03:27 AM UTC 24 |
| Finished | Aug 27 07:03:38 AM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422457389 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1422457389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1484505382 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 286006030 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:59 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484505382 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1484505382 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1898476667 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1386434165 ps |
| CPU time | 8.91 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:03:03 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898476667 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1898476667 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.2732324158 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 41499653 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732324158 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2732324158 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1892666278 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 726233709 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 231700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1892666278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_ rw_with_rand_reset.1892666278 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.381949741 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 89520965 ps |
| CPU time | 1.44 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381949741 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.381949741 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3963696719 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 44146705 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:55 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963696719 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3963696719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.3539424338 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 54318842 ps |
| CPU time | 1.71 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:55 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539424338 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.3539424338 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2955683144 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 28475650 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:53 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955683144 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2955683144 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.838246181 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 34962301 ps |
| CPU time | 2 seconds |
| Started | Aug 27 07:02:53 AM UTC 24 |
| Finished | Aug 27 07:02:57 AM UTC 24 |
| Peak memory | 224516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838246181 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.838246181 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.812095042 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 25525981 ps |
| CPU time | 1.64 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:54 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812095042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.812095042 +enable_masking=1 + sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1583231266 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 419147567 ps |
| CPU time | 2.93 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583231266 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.1583 231266 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1825514314 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 83054796 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:55 AM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825514314 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1825514314 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1487189436 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 521178897 ps |
| CPU time | 4.79 seconds |
| Started | Aug 27 07:02:52 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487189436 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1487189436 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2188511231 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 57328900 ps |
| CPU time | 0.71 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188511231 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2188511231 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2350988003 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 15050508 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:35 AM UTC 24 |
| Peak memory | 225028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350988003 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2350988003 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3321230415 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 13526935 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321230415 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3321230415 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.3539414922 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 39369368 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539414922 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3539414922 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.4150948541 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 48995063 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150948541 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.4150948541 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.778439518 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 116326484 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778439518 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.778439518 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1514991387 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 16003847 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514991387 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1514991387 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.1434360934 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 16298071 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434360934 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1434360934 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3473753787 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 12819209 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473753787 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3473753787 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.486227742 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 16973401 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486227742 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.486227742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3530661152 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 292889682 ps |
| CPU time | 4.52 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530661152 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3530661152 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.4077783157 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 530077397 ps |
| CPU time | 7.45 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 225468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077783157 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4077783157 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1231033026 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 69093378 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231033026 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1231033026 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.367474575 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 239746901 ps |
| CPU time | 1.88 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 230760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=367474575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_r w_with_rand_reset.367474575 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.193892372 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 42565700 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193892372 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.193892372 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.474055953 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 11430573 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 224612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474055953 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.474055953 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.209187137 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 179709715 ps |
| CPU time | 1.75 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:57 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209187137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.209187137 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1924354227 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 54578449 ps |
| CPU time | 0.84 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 224548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924354227 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1924354227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3973343203 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 361727909 ps |
| CPU time | 2.49 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:02:59 AM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973343203 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.3973343203 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3573769546 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 45100259 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:56 AM UTC 24 |
| Peak memory | 224252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573769546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3573769546 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3859557402 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 457006129 ps |
| CPU time | 3.21 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859557402 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3859 557402 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1143394841 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 126761693 ps |
| CPU time | 2.79 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143394841 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1143394841 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.2635229782 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 238843141 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 07:02:54 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635229782 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.2635229782 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1854977545 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 35573074 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854977545 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1854977545 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.251896492 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 17081342 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251896492 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.251896492 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1263265086 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 52583549 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 07:03:33 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263265086 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1263265086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.589229510 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 30206536 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589229510 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.589229510 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1045994925 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 15382976 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045994925 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1045994925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1819490257 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 48531268 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819490257 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1819490257 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1525269663 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 23369930 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525269663 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1525269663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1463222162 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 44286104 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:46 AM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463222162 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1463222162 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1423496581 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 68463405 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 07:03:34 AM UTC 24 |
| Finished | Aug 27 07:03:56 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423496581 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1423496581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1166662344 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 11765269 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 07:03:35 AM UTC 24 |
| Finished | Aug 27 07:04:05 AM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166662344 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1166662344 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1607645500 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 142036056 ps |
| CPU time | 7.32 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 224968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607645500 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1607645500 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.4127456845 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1000696914 ps |
| CPU time | 9.27 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:03:07 AM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127456845 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.4127456845 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.1812265093 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 45947586 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 224488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812265093 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1812265093 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2426348199 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 177105593 ps |
| CPU time | 2.21 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 231492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2426348199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_ rw_with_rand_reset.2426348199 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.3318924480 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 32309460 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:59 AM UTC 24 |
| Peak memory | 224408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318924480 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3318924480 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2533623318 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 32388443 ps |
| CPU time | 0.76 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 224208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533623318 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2533623318 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2052711158 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 29698037 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 224284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052711158 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2052711158 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2020266424 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 16396924 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:58 AM UTC 24 |
| Peak memory | 223152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020266424 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2020266424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.4168613547 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 97008933 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168613547 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.4168613547 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.4144120378 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 42702030 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 07:02:55 AM UTC 24 |
| Finished | Aug 27 07:02:57 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144120378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.4144120378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2196609071 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 480744806 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:03:00 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196609071 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.2196 609071 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.2033060872 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 225354167 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:02:59 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033060872 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2033060872 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.3396546376 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 81540054 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 07:02:56 AM UTC 24 |
| Finished | Aug 27 07:03:00 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396546376 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.3396546376 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.1020524459 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 23806892 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 07:03:36 AM UTC 24 |
| Finished | Aug 27 07:03:41 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020524459 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1020524459 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.1453797585 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 14137009 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 07:03:36 AM UTC 24 |
| Finished | Aug 27 07:03:41 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453797585 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1453797585 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.987013892 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 16496051 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 07:03:36 AM UTC 24 |
| Finished | Aug 27 07:03:41 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987013892 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.987013892 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.894626695 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 12921383 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:37 AM UTC 24 |
| Finished | Aug 27 07:03:42 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894626695 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.894626695 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.753277560 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 11246267 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:37 AM UTC 24 |
| Finished | Aug 27 07:03:42 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753277560 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.753277560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1167108926 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 16912453 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 07:03:39 AM UTC 24 |
| Finished | Aug 27 07:03:41 AM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167108926 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1167108926 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2955645773 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 14693224 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 07:03:40 AM UTC 24 |
| Finished | Aug 27 07:03:45 AM UTC 24 |
| Peak memory | 224620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955645773 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2955645773 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.321456849 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 38461355 ps |
| CPU time | 0.76 seconds |
| Started | Aug 27 07:03:41 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321456849 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.321456849 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.3329183351 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 42036813 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 07:03:42 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329183351 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3329183351 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3709597729 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 36795797 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 07:03:42 AM UTC 24 |
| Finished | Aug 27 07:04:04 AM UTC 24 |
| Peak memory | 224496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709597729 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3709597729 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1818520063 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 45011909 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 228660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1818520063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_ rw_with_rand_reset.1818520063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.2180613625 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 47394486 ps |
| CPU time | 1.5 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180613625 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2180613625 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1214317541 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 33927882 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214317541 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1214317541 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2247102955 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 89703769 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247102955 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.2247102955 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1933207406 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 482628331 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 07:02:57 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933207406 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1933207406 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1881079053 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 238639219 ps |
| CPU time | 4.01 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881079053 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1881079053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.157053003 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 304301275 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=157053003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_r w_with_rand_reset.157053003 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3252707237 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 82579841 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252707237 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3252707237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2144053126 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 41410759 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 224404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144053126 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2144053126 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.611111065 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 22693453 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 224632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611111065 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.611111065 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2654026303 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 33120231 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:01 AM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654026303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.2654026303 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.682940007 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 842544222 ps |
| CPU time | 2.47 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682940007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.68294 0007 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.225501367 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 82885305 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:02 AM UTC 24 |
| Peak memory | 224564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225501367 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.225501367 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.845793232 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 55502300 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 07:02:59 AM UTC 24 |
| Finished | Aug 27 07:03:03 AM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845793232 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.845793232 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.841231881 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 26664178 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=841231881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_r w_with_rand_reset.841231881 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3049947375 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 100663387 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:03 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049947375 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3049947375 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.470121472 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 12009297 ps |
| CPU time | 0.78 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:03 AM UTC 24 |
| Peak memory | 224224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470121472 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.470121472 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1547673862 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 367524329 ps |
| CPU time | 2.4 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547673862 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.1547673862 +enable_mas king=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2408393542 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 25661512 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:03 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408393542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2408393542 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2236895830 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 474357916 ps |
| CPU time | 1.95 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236895830 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.2236 895830 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.3664683440 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 314000672 ps |
| CPU time | 3.48 seconds |
| Started | Aug 27 07:03:00 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664683440 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3664683440 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.522494946 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 114411227 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=522494946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_r w_with_rand_reset.522494946 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.4133191097 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 38336376 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 224560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133191097 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.4133191097 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4178842204 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 37698149 ps |
| CPU time | 0.83 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178842204 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4178842204 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.513037092 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 285942193 ps |
| CPU time | 1.71 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 224628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513037092 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.513037092 +enable_maski ng=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2606622057 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 29792163 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:04 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606622057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.2606622057 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3982251304 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 203899684 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982251304 -asser t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.3982 251304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.3568282807 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 152120862 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:06 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568282807 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3568282807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.570228581 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 93282210 ps |
| CPU time | 2.29 seconds |
| Started | Aug 27 07:03:01 AM UTC 24 |
| Finished | Aug 27 07:03:05 AM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570228581 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.570228581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.382573727 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 462360762 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 226604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=382573727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_r w_with_rand_reset.382573727 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2482440919 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 92207662 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482440919 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2482440919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3770220046 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 27500809 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:15 AM UTC 24 |
| Peak memory | 224500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770220046 -assert nopostproc +UVM_TESTNAME=kma c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3770220046 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.59452559 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 57894917 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59452559 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.59452559 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2942286629 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 24182843 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:16 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942286629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.2942286629 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.506906238 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 90175513 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:03:02 AM UTC 24 |
| Finished | Aug 27 07:03:17 AM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506906238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.50690 6238 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.707052374 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 522424370 ps |
| CPU time | 2.13 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:33 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707052374 -assert nopostproc +UVM_TESTNAME=kmac _base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.707052374 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.1014319234 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 331869011 ps |
| CPU time | 2.62 seconds |
| Started | Aug 27 07:03:03 AM UTC 24 |
| Finished | Aug 27 07:03:07 AM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014319234 -assert nopostproc +UVM_ TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.1014319234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_app.4209159362 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10984128232 ps |
| CPU time | 282.02 seconds |
| Started | Aug 27 05:00:53 PM UTC 24 |
| Finished | Aug 27 05:05:39 PM UTC 24 |
| Peak memory | 454896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209159362 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4209159362 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.282524347 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 38842258721 ps |
| CPU time | 477.49 seconds |
| Started | Aug 27 05:00:53 PM UTC 24 |
| Finished | Aug 27 05:08:57 PM UTC 24 |
| Peak memory | 585972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282524347 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.282524347 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.1978947850 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 54621082161 ps |
| CPU time | 1272.36 seconds |
| Started | Aug 27 05:00:49 PM UTC 24 |
| Finished | Aug 27 05:22:17 PM UTC 24 |
| Peak memory | 254056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978947850 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1978947850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.206136899 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 24734750 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 05:00:54 PM UTC 24 |
| Finished | Aug 27 05:00:57 PM UTC 24 |
| Peak memory | 226784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206136899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.206136899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.1379375637 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 28296946967 ps |
| CPU time | 364.87 seconds |
| Started | Aug 27 05:00:53 PM UTC 24 |
| Finished | Aug 27 05:07:03 PM UTC 24 |
| Peak memory | 518392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379375637 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.1379375637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.107299013 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 7645304047 ps |
| CPU time | 804.34 seconds |
| Started | Aug 27 05:00:49 PM UTC 24 |
| Finished | Aug 27 05:14:24 PM UTC 24 |
| Peak memory | 674096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107299013 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.107299013 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.2136768198 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 234157149 ps |
| CPU time | 8.85 seconds |
| Started | Aug 27 05:00:53 PM UTC 24 |
| Finished | Aug 27 05:01:03 PM UTC 24 |
| Peak memory | 246348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136768198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2136768198 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1871620015 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 42875794612 ps |
| CPU time | 176.61 seconds |
| Started | Aug 27 05:00:56 PM UTC 24 |
| Finished | Aug 27 05:03:56 PM UTC 24 |
| Peak memory | 312896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871620015 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1871620015 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.2153965063 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4790779624 ps |
| CPU time | 115.35 seconds |
| Started | Aug 27 05:00:49 PM UTC 24 |
| Finished | Aug 27 05:02:47 PM UTC 24 |
| Peak memory | 266392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153965063 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2153965063 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.125658116 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4268303704 ps |
| CPU time | 84.38 seconds |
| Started | Aug 27 05:00:48 PM UTC 24 |
| Finished | Aug 27 05:02:14 PM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125658116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.125658116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.560232868 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 29226733095 ps |
| CPU time | 1129.61 seconds |
| Started | Aug 27 05:00:56 PM UTC 24 |
| Finished | Aug 27 05:19:59 PM UTC 24 |
| Peak memory | 1218912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560232868 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.560232868 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.3577723127 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 406171270 ps |
| CPU time | 4.19 seconds |
| Started | Aug 27 05:00:52 PM UTC 24 |
| Finished | Aug 27 05:00:57 PM UTC 24 |
| Peak memory | 235748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577723127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.3577723127 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.313346335 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 734674313 ps |
| CPU time | 4.14 seconds |
| Started | Aug 27 05:00:52 PM UTC 24 |
| Finished | Aug 27 05:00:57 PM UTC 24 |
| Peak memory | 235712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313346335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.313346335 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1348566204 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 18785396974 ps |
| CPU time | 2023.26 seconds |
| Started | Aug 27 05:00:50 PM UTC 24 |
| Finished | Aug 27 05:34:57 PM UTC 24 |
| Peak memory | 1184000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348566204 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1348566204 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.1209402106 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8798141437 ps |
| CPU time | 48.21 seconds |
| Started | Aug 27 05:00:51 PM UTC 24 |
| Finished | Aug 27 05:01:40 PM UTC 24 |
| Peak memory | 256244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209402106 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1209402106 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1626352213 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 177295569475 ps |
| CPU time | 1926.28 seconds |
| Started | Aug 27 05:00:51 PM UTC 24 |
| Finished | Aug 27 05:33:18 PM UTC 24 |
| Peak memory | 2338972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626352213 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1626352213 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.1495477740 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1163053308 ps |
| CPU time | 17.04 seconds |
| Started | Aug 27 05:00:51 PM UTC 24 |
| Finished | Aug 27 05:01:09 PM UTC 24 |
| Peak memory | 227660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495477740 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1495477740 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.801601393 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 55083314282 ps |
| CPU time | 224.04 seconds |
| Started | Aug 27 05:00:52 PM UTC 24 |
| Finished | Aug 27 05:04:39 PM UTC 24 |
| Peak memory | 442552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801601393 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.801601393 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1358966727 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5486145083 ps |
| CPU time | 146.85 seconds |
| Started | Aug 27 05:00:52 PM UTC 24 |
| Finished | Aug 27 05:03:21 PM UTC 24 |
| Peak memory | 268540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358966727 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1358966727 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.606075456 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 15132555 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:01:33 PM UTC 24 |
| Finished | Aug 27 05:01:36 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606075456 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.606075456 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_app.1956176749 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 26191425490 ps |
| CPU time | 366 seconds |
| Started | Aug 27 05:01:11 PM UTC 24 |
| Finished | Aug 27 05:07:22 PM UTC 24 |
| Peak memory | 497904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956176749 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1956176749 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.2365160176 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 26946846561 ps |
| CPU time | 673.15 seconds |
| Started | Aug 27 05:01:00 PM UTC 24 |
| Finished | Aug 27 05:12:22 PM UTC 24 |
| Peak memory | 256228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365160176 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2365160176 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.1000188440 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4417604415 ps |
| CPU time | 49.18 seconds |
| Started | Aug 27 05:01:17 PM UTC 24 |
| Finished | Aug 27 05:02:08 PM UTC 24 |
| Peak memory | 235592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000188440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1000188440 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2988985174 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 17201718 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:01:25 PM UTC 24 |
| Finished | Aug 27 05:01:28 PM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988985174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2988985174 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3174880923 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1864853150 ps |
| CPU time | 25.67 seconds |
| Started | Aug 27 05:01:25 PM UTC 24 |
| Finished | Aug 27 05:01:53 PM UTC 24 |
| Peak memory | 235760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174880923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3174880923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.27557061 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9774270438 ps |
| CPU time | 83.71 seconds |
| Started | Aug 27 05:01:14 PM UTC 24 |
| Finished | Aug 27 05:02:39 PM UTC 24 |
| Peak memory | 272664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27557061 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.27557061 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.2242990298 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2767307145 ps |
| CPU time | 8.5 seconds |
| Started | Aug 27 05:01:17 PM UTC 24 |
| Finished | Aug 27 05:01:27 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242990298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2242990298 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.3515816506 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 74116720 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 05:01:28 PM UTC 24 |
| Finished | Aug 27 05:01:31 PM UTC 24 |
| Peak memory | 231364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515816506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.3515816506 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.4064802615 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1055671996 ps |
| CPU time | 53.53 seconds |
| Started | Aug 27 05:00:58 PM UTC 24 |
| Finished | Aug 27 05:01:53 PM UTC 24 |
| Peak memory | 272684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064802615 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.4064802615 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.1977742000 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4473162919 ps |
| CPU time | 51.82 seconds |
| Started | Aug 27 05:01:32 PM UTC 24 |
| Finished | Aug 27 05:02:26 PM UTC 24 |
| Peak memory | 271872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977742000 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1977742000 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.4264268684 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1694978211 ps |
| CPU time | 17.23 seconds |
| Started | Aug 27 05:00:58 PM UTC 24 |
| Finished | Aug 27 05:01:16 PM UTC 24 |
| Peak memory | 235772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264268684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.4264268684 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.2355566200 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11233770089 ps |
| CPU time | 56.03 seconds |
| Started | Aug 27 05:01:29 PM UTC 24 |
| Finished | Aug 27 05:02:27 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355566200 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2355566200 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.412903476 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 213635874 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 05:01:09 PM UTC 24 |
| Finished | Aug 27 05:01:13 PM UTC 24 |
| Peak memory | 227708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412903476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.412903476 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1656435771 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 95319054 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 05:01:09 PM UTC 24 |
| Finished | Aug 27 05:01:14 PM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656435771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.1656435771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1642613328 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 91112251419 ps |
| CPU time | 2681.36 seconds |
| Started | Aug 27 05:01:00 PM UTC 24 |
| Finished | Aug 27 05:46:10 PM UTC 24 |
| Peak memory | 3107136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642613328 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1642613328 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.3174393838 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14187927010 ps |
| CPU time | 36.37 seconds |
| Started | Aug 27 05:01:02 PM UTC 24 |
| Finished | Aug 27 05:01:40 PM UTC 24 |
| Peak memory | 233972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174393838 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3174393838 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.4033823791 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 32090097094 ps |
| CPU time | 1389.73 seconds |
| Started | Aug 27 05:01:05 PM UTC 24 |
| Finished | Aug 27 05:24:31 PM UTC 24 |
| Peak memory | 1673376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033823791 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4033823791 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.824162819 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 31867126664 ps |
| CPU time | 162.66 seconds |
| Started | Aug 27 05:01:05 PM UTC 24 |
| Finished | Aug 27 05:03:50 PM UTC 24 |
| Peak memory | 290992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824162819 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.824162819 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.548273340 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 44644842686 ps |
| CPU time | 442.55 seconds |
| Started | Aug 27 05:01:09 PM UTC 24 |
| Finished | Aug 27 05:08:38 PM UTC 24 |
| Peak memory | 368804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548273340 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.548273340 +ena ble_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.1903893438 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 18672460 ps |
| CPU time | 1.34 seconds |
| Started | Aug 27 05:15:48 PM UTC 24 |
| Finished | Aug 27 05:15:51 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903893438 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1903893438 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_app.529674646 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6146860957 ps |
| CPU time | 329.77 seconds |
| Started | Aug 27 05:15:28 PM UTC 24 |
| Finished | Aug 27 05:21:02 PM UTC 24 |
| Peak memory | 344392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529674646 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.529674646 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.4044956995 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 13079338906 ps |
| CPU time | 1440.8 seconds |
| Started | Aug 27 05:14:54 PM UTC 24 |
| Finished | Aug 27 05:39:12 PM UTC 24 |
| Peak memory | 254188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044956995 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.4044956995 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1175302588 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 135699769 ps |
| CPU time | 5.36 seconds |
| Started | Aug 27 05:15:41 PM UTC 24 |
| Finished | Aug 27 05:15:48 PM UTC 24 |
| Peak memory | 233668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175302588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1175302588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.4240063844 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 33679615 ps |
| CPU time | 1.67 seconds |
| Started | Aug 27 05:15:46 PM UTC 24 |
| Finished | Aug 27 05:15:49 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240063844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4240063844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.1160777179 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 12686835228 ps |
| CPU time | 262.94 seconds |
| Started | Aug 27 05:15:33 PM UTC 24 |
| Finished | Aug 27 05:20:00 PM UTC 24 |
| Peak memory | 452848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160777179 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1160777179 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.1084800048 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1038492503 ps |
| CPU time | 4.56 seconds |
| Started | Aug 27 05:15:40 PM UTC 24 |
| Finished | Aug 27 05:15:46 PM UTC 24 |
| Peak memory | 227728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084800048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1084800048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2215968998 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 110205648886 ps |
| CPU time | 5007.95 seconds |
| Started | Aug 27 05:14:38 PM UTC 24 |
| Finished | Aug 27 06:39:03 PM UTC 24 |
| Peak memory | 4618592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215968998 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2215968998 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.485839819 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4316824357 ps |
| CPU time | 225.83 seconds |
| Started | Aug 27 05:14:47 PM UTC 24 |
| Finished | Aug 27 05:18:36 PM UTC 24 |
| Peak memory | 297332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485839819 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.485839819 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.1281756151 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4934187019 ps |
| CPU time | 49.06 seconds |
| Started | Aug 27 05:14:36 PM UTC 24 |
| Finished | Aug 27 05:15:27 PM UTC 24 |
| Peak memory | 235772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281756151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1281756151 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.3181126720 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 27480662655 ps |
| CPU time | 140.58 seconds |
| Started | Aug 27 05:15:47 PM UTC 24 |
| Finished | Aug 27 05:18:10 PM UTC 24 |
| Peak memory | 315696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181126720 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3181126720 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/10.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.3226297937 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 30145541 ps |
| CPU time | 1.34 seconds |
| Started | Aug 27 05:17:56 PM UTC 24 |
| Finished | Aug 27 05:17:58 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226297937 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3226297937 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_app.4005228113 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 54687685920 ps |
| CPU time | 444.16 seconds |
| Started | Aug 27 05:16:49 PM UTC 24 |
| Finished | Aug 27 05:24:19 PM UTC 24 |
| Peak memory | 469304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005228113 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.4005228113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.2147169933 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 25204655803 ps |
| CPU time | 131.05 seconds |
| Started | Aug 27 05:16:16 PM UTC 24 |
| Finished | Aug 27 05:18:29 PM UTC 24 |
| Peak memory | 235820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147169933 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2147169933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2111935185 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 461502313 ps |
| CPU time | 41.6 seconds |
| Started | Aug 27 05:17:12 PM UTC 24 |
| Finished | Aug 27 05:17:55 PM UTC 24 |
| Peak memory | 235472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111935185 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2111935185 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.1237588113 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 6707209110 ps |
| CPU time | 50.33 seconds |
| Started | Aug 27 05:17:24 PM UTC 24 |
| Finished | Aug 27 05:18:16 PM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237588113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1237588113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.3843409944 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 9693986741 ps |
| CPU time | 106.04 seconds |
| Started | Aug 27 05:16:51 PM UTC 24 |
| Finished | Aug 27 05:18:39 PM UTC 24 |
| Peak memory | 252216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843409944 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3843409944 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_error.3410375247 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2350054606 ps |
| CPU time | 108.53 seconds |
| Started | Aug 27 05:16:55 PM UTC 24 |
| Finished | Aug 27 05:18:46 PM UTC 24 |
| Peak memory | 311596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410375247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.3410375247 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.3294702335 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1714151851 ps |
| CPU time | 7.92 seconds |
| Started | Aug 27 05:17:02 PM UTC 24 |
| Finished | Aug 27 05:17:11 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294702335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3294702335 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1361822765 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 113449809662 ps |
| CPU time | 4360.76 seconds |
| Started | Aug 27 05:15:51 PM UTC 24 |
| Finished | Aug 27 06:29:19 PM UTC 24 |
| Peak memory | 4219148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361822765 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1361822765 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.2701811128 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 270198629242 ps |
| CPU time | 480.12 seconds |
| Started | Aug 27 05:15:52 PM UTC 24 |
| Finished | Aug 27 05:23:58 PM UTC 24 |
| Peak memory | 585972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701811128 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2701811128 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.672737014 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3617479238 ps |
| CPU time | 59.05 seconds |
| Started | Aug 27 05:15:50 PM UTC 24 |
| Finished | Aug 27 05:16:50 PM UTC 24 |
| Peak memory | 233996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672737014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.672737014 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.595311037 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 249449516909 ps |
| CPU time | 2584.23 seconds |
| Started | Aug 27 05:17:37 PM UTC 24 |
| Finished | Aug 27 06:01:10 PM UTC 24 |
| Peak memory | 1170272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595311037 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.595311037 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/11.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.3831865582 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 56620252 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:19:03 PM UTC 24 |
| Finished | Aug 27 05:19:06 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831865582 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3831865582 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_app.808193568 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11145594429 ps |
| CPU time | 326.12 seconds |
| Started | Aug 27 05:18:30 PM UTC 24 |
| Finished | Aug 27 05:24:01 PM UTC 24 |
| Peak memory | 510204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808193568 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.808193568 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.3056639 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 23074706224 ps |
| CPU time | 1317.21 seconds |
| Started | Aug 27 05:18:19 PM UTC 24 |
| Finished | Aug 27 05:40:32 PM UTC 24 |
| Peak memory | 266548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056639 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3056639 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2982262295 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 658522404 ps |
| CPU time | 36.57 seconds |
| Started | Aug 27 05:18:51 PM UTC 24 |
| Finished | Aug 27 05:19:30 PM UTC 24 |
| Peak memory | 245712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982262295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2982262295 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2033235123 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 53402267 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 05:18:56 PM UTC 24 |
| Finished | Aug 27 05:18:58 PM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033235123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2033235123 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2125053902 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 11839236742 ps |
| CPU time | 204.16 seconds |
| Started | Aug 27 05:18:37 PM UTC 24 |
| Finished | Aug 27 05:22:04 PM UTC 24 |
| Peak memory | 381244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125053902 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2125053902 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_error.3691473719 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6095638599 ps |
| CPU time | 191.19 seconds |
| Started | Aug 27 05:18:40 PM UTC 24 |
| Finished | Aug 27 05:21:55 PM UTC 24 |
| Peak memory | 379200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691473719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3691473719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.4022967992 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 429709085 ps |
| CPU time | 3.3 seconds |
| Started | Aug 27 05:18:46 PM UTC 24 |
| Finished | Aug 27 05:18:51 PM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022967992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.4022967992 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.2963540992 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 85936798 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 05:18:59 PM UTC 24 |
| Finished | Aug 27 05:19:02 PM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963540992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2963540992 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.300262277 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 46757238840 ps |
| CPU time | 1984.59 seconds |
| Started | Aug 27 05:18:11 PM UTC 24 |
| Finished | Aug 27 05:51:38 PM UTC 24 |
| Peak memory | 2320684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300262277 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.300262277 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.1555958463 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2204044045 ps |
| CPU time | 186.2 seconds |
| Started | Aug 27 05:18:17 PM UTC 24 |
| Finished | Aug 27 05:21:26 PM UTC 24 |
| Peak memory | 288992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555958463 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1555958463 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.3842037385 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 8696713822 ps |
| CPU time | 99.62 seconds |
| Started | Aug 27 05:17:59 PM UTC 24 |
| Finished | Aug 27 05:19:41 PM UTC 24 |
| Peak memory | 235820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842037385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3842037385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.2944008873 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 193907631715 ps |
| CPU time | 1778.69 seconds |
| Started | Aug 27 05:19:00 PM UTC 24 |
| Finished | Aug 27 05:48:59 PM UTC 24 |
| Peak memory | 1383040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944008873 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2944008873 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/12.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.1945097031 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 53915017 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:20:28 PM UTC 24 |
| Finished | Aug 27 05:20:30 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945097031 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.1945097031 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_app.2251062668 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 17203147296 ps |
| CPU time | 168.75 seconds |
| Started | Aug 27 05:19:41 PM UTC 24 |
| Finished | Aug 27 05:22:33 PM UTC 24 |
| Peak memory | 319856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251062668 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2251062668 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.919139809 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5503531824 ps |
| CPU time | 327.04 seconds |
| Started | Aug 27 05:19:40 PM UTC 24 |
| Finished | Aug 27 05:25:12 PM UTC 24 |
| Peak memory | 243996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919139809 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.919139809 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2811070330 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 83320823 ps |
| CPU time | 3.41 seconds |
| Started | Aug 27 05:20:14 PM UTC 24 |
| Finished | Aug 27 05:20:18 PM UTC 24 |
| Peak memory | 233748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811070330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2811070330 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.2956255253 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 16970297 ps |
| CPU time | 1.35 seconds |
| Started | Aug 27 05:20:19 PM UTC 24 |
| Finished | Aug 27 05:20:21 PM UTC 24 |
| Peak memory | 225092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956255253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2956255253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.3651319920 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 31304688582 ps |
| CPU time | 426.08 seconds |
| Started | Aug 27 05:19:52 PM UTC 24 |
| Finished | Aug 27 05:27:04 PM UTC 24 |
| Peak memory | 342260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651319920 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3651319920 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_error.4282915154 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 19848478817 ps |
| CPU time | 418.78 seconds |
| Started | Aug 27 05:20:00 PM UTC 24 |
| Finished | Aug 27 05:27:05 PM UTC 24 |
| Peak memory | 358648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282915154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.4282915154 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.467257424 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3701105328 ps |
| CPU time | 20.68 seconds |
| Started | Aug 27 05:20:01 PM UTC 24 |
| Finished | Aug 27 05:20:22 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467257424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.467257424 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.3117168742 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 707958165 ps |
| CPU time | 10.79 seconds |
| Started | Aug 27 05:20:24 PM UTC 24 |
| Finished | Aug 27 05:20:37 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117168742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3117168742 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3390858541 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5148126736 ps |
| CPU time | 318.75 seconds |
| Started | Aug 27 05:19:20 PM UTC 24 |
| Finished | Aug 27 05:24:44 PM UTC 24 |
| Peak memory | 379192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390858541 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3390858541 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1860789547 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8354682787 ps |
| CPU time | 230.35 seconds |
| Started | Aug 27 05:19:30 PM UTC 24 |
| Finished | Aug 27 05:23:24 PM UTC 24 |
| Peak memory | 293176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860789547 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1860789547 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.1915648089 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11865157099 ps |
| CPU time | 1051.78 seconds |
| Started | Aug 27 05:20:28 PM UTC 24 |
| Finished | Aug 27 05:38:12 PM UTC 24 |
| Peak memory | 754276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915648089 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1915648089 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/13.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.2406387086 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 12786611 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 05:21:27 PM UTC 24 |
| Finished | Aug 27 05:21:30 PM UTC 24 |
| Peak memory | 224972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406387086 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2406387086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_app.3231216111 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 45235634246 ps |
| CPU time | 275.89 seconds |
| Started | Aug 27 05:20:43 PM UTC 24 |
| Finished | Aug 27 05:25:23 PM UTC 24 |
| Peak memory | 407864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231216111 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3231216111 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.3970278017 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6735611077 ps |
| CPU time | 478.34 seconds |
| Started | Aug 27 05:20:40 PM UTC 24 |
| Finished | Aug 27 05:28:46 PM UTC 24 |
| Peak memory | 252204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970278017 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3970278017 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2896575506 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 20463027 ps |
| CPU time | 1.48 seconds |
| Started | Aug 27 05:21:11 PM UTC 24 |
| Finished | Aug 27 05:21:14 PM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896575506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2896575506 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.58836153 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 90157077 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 05:21:14 PM UTC 24 |
| Finished | Aug 27 05:21:17 PM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58836153 -assert nopostproc +UVM_TESTNAME=kmac_base_test + UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.58836153 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.2123015798 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 15591481487 ps |
| CPU time | 200.98 seconds |
| Started | Aug 27 05:20:49 PM UTC 24 |
| Finished | Aug 27 05:24:13 PM UTC 24 |
| Peak memory | 297280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123015798 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2123015798 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_error.30795324 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 13328219865 ps |
| CPU time | 67.33 seconds |
| Started | Aug 27 05:21:03 PM UTC 24 |
| Finished | Aug 27 05:22:12 PM UTC 24 |
| Peak memory | 262464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30795324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.30795324 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.551369483 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 382893456 ps |
| CPU time | 3.66 seconds |
| Started | Aug 27 05:21:06 PM UTC 24 |
| Finished | Aug 27 05:21:11 PM UTC 24 |
| Peak memory | 227508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551369483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.551369483 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.1113003560 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 110767739 ps |
| CPU time | 1.8 seconds |
| Started | Aug 27 05:21:17 PM UTC 24 |
| Finished | Aug 27 05:21:20 PM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113003560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1113003560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3301580642 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 58467552688 ps |
| CPU time | 3132.46 seconds |
| Started | Aug 27 05:20:31 PM UTC 24 |
| Finished | Aug 27 06:13:18 PM UTC 24 |
| Peak memory | 1775936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301580642 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3301580642 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.1399579421 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 96439266252 ps |
| CPU time | 595.71 seconds |
| Started | Aug 27 05:20:37 PM UTC 24 |
| Finished | Aug 27 05:30:41 PM UTC 24 |
| Peak memory | 588024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399579421 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1399579421 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.2837229925 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3567369172 ps |
| CPU time | 98.01 seconds |
| Started | Aug 27 05:20:28 PM UTC 24 |
| Finished | Aug 27 05:22:08 PM UTC 24 |
| Peak memory | 235836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837229925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2837229925 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.1542459824 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 148201850029 ps |
| CPU time | 3294.76 seconds |
| Started | Aug 27 05:21:21 PM UTC 24 |
| Finished | Aug 27 06:16:53 PM UTC 24 |
| Peak memory | 1852108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542459824 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1542459824 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/14.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.1923072263 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 25254870 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 05:23:13 PM UTC 24 |
| Finished | Aug 27 05:23:15 PM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923072263 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1923072263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3007859905 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2681279564 ps |
| CPU time | 163.15 seconds |
| Started | Aug 27 05:22:05 PM UTC 24 |
| Finished | Aug 27 05:24:51 PM UTC 24 |
| Peak memory | 276796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007859905 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3007859905 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.42632286 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3269109840 ps |
| CPU time | 359.48 seconds |
| Started | Aug 27 05:21:56 PM UTC 24 |
| Finished | Aug 27 05:28:01 PM UTC 24 |
| Peak memory | 239860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42632286 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.42632286 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.2342769151 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4280799271 ps |
| CPU time | 42.97 seconds |
| Started | Aug 27 05:22:29 PM UTC 24 |
| Finished | Aug 27 05:23:14 PM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342769151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2342769151 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.794838950 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3349142905 ps |
| CPU time | 51.91 seconds |
| Started | Aug 27 05:22:33 PM UTC 24 |
| Finished | Aug 27 05:23:27 PM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794838950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.794838950 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1602189214 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 15542034160 ps |
| CPU time | 343.32 seconds |
| Started | Aug 27 05:22:09 PM UTC 24 |
| Finished | Aug 27 05:27:57 PM UTC 24 |
| Peak memory | 500068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602189214 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1602189214 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_error.2675459836 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 29375397393 ps |
| CPU time | 163.08 seconds |
| Started | Aug 27 05:22:13 PM UTC 24 |
| Finished | Aug 27 05:24:59 PM UTC 24 |
| Peak memory | 285048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675459836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2675459836 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.959200894 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1513625777 ps |
| CPU time | 9.63 seconds |
| Started | Aug 27 05:22:18 PM UTC 24 |
| Finished | Aug 27 05:22:29 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959200894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.959200894 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.2916479865 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 118102734704 ps |
| CPU time | 3233.27 seconds |
| Started | Aug 27 05:21:43 PM UTC 24 |
| Finished | Aug 27 06:16:12 PM UTC 24 |
| Peak memory | 1956092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916479865 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.2916479865 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.1335852822 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3226958215 ps |
| CPU time | 205.79 seconds |
| Started | Aug 27 05:21:50 PM UTC 24 |
| Finished | Aug 27 05:25:19 PM UTC 24 |
| Peak memory | 301372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335852822 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1335852822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.1889386227 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 181120628 ps |
| CPU time | 9.55 seconds |
| Started | Aug 27 05:21:30 PM UTC 24 |
| Finished | Aug 27 05:21:41 PM UTC 24 |
| Peak memory | 235708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889386227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1889386227 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.3792515176 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 20749977961 ps |
| CPU time | 865.09 seconds |
| Started | Aug 27 05:23:06 PM UTC 24 |
| Finished | Aug 27 05:37:42 PM UTC 24 |
| Peak memory | 465612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792515176 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3792515176 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/15.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.3341790607 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 49276987 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 05:24:24 PM UTC 24 |
| Finished | Aug 27 05:24:26 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341790607 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3341790607 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_app.658507407 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 16643197130 ps |
| CPU time | 209.31 seconds |
| Started | Aug 27 05:23:59 PM UTC 24 |
| Finished | Aug 27 05:27:32 PM UTC 24 |
| Peak memory | 295212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658507407 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.658507407 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.3709834304 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 87184519546 ps |
| CPU time | 1455.63 seconds |
| Started | Aug 27 05:23:28 PM UTC 24 |
| Finished | Aug 27 05:48:00 PM UTC 24 |
| Peak memory | 258352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709834304 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3709834304 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3802192381 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 15205277 ps |
| CPU time | 1.34 seconds |
| Started | Aug 27 05:24:20 PM UTC 24 |
| Finished | Aug 27 05:24:22 PM UTC 24 |
| Peak memory | 225036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802192381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3802192381 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.4172640533 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 44209233 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 05:24:21 PM UTC 24 |
| Finished | Aug 27 05:24:23 PM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172640533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.4172640533 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.895871807 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 10539998586 ps |
| CPU time | 186.21 seconds |
| Started | Aug 27 05:24:01 PM UTC 24 |
| Finished | Aug 27 05:27:11 PM UTC 24 |
| Peak memory | 373112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895871807 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.895871807 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_error.1513143832 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 13523680835 ps |
| CPU time | 247.32 seconds |
| Started | Aug 27 05:24:13 PM UTC 24 |
| Finished | Aug 27 05:28:24 PM UTC 24 |
| Peak memory | 330020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513143832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1513143832 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.192531319 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1862388776 ps |
| CPU time | 6.08 seconds |
| Started | Aug 27 05:24:16 PM UTC 24 |
| Finished | Aug 27 05:24:23 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192531319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.192531319 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.2996051282 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 57881387 ps |
| CPU time | 2.31 seconds |
| Started | Aug 27 05:24:23 PM UTC 24 |
| Finished | Aug 27 05:24:26 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996051282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2996051282 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.572128540 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5959869843 ps |
| CPU time | 61.24 seconds |
| Started | Aug 27 05:23:16 PM UTC 24 |
| Finished | Aug 27 05:24:19 PM UTC 24 |
| Peak memory | 291112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572128540 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.572128540 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.1061531684 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 20040296856 ps |
| CPU time | 212.44 seconds |
| Started | Aug 27 05:23:25 PM UTC 24 |
| Finished | Aug 27 05:27:01 PM UTC 24 |
| Peak memory | 303356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061531684 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1061531684 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.608391618 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2178330051 ps |
| CPU time | 58.56 seconds |
| Started | Aug 27 05:23:15 PM UTC 24 |
| Finished | Aug 27 05:24:15 PM UTC 24 |
| Peak memory | 235828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608391618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.608391618 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.1068411219 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 9741697523 ps |
| CPU time | 250.19 seconds |
| Started | Aug 27 05:24:24 PM UTC 24 |
| Finished | Aug 27 05:28:38 PM UTC 24 |
| Peak memory | 352516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068411219 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1068411219 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/16.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.2754547567 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 17265891 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:25:19 PM UTC 24 |
| Finished | Aug 27 05:25:21 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754547567 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2754547567 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_app.2968305067 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 16614940635 ps |
| CPU time | 208.34 seconds |
| Started | Aug 27 05:24:44 PM UTC 24 |
| Finished | Aug 27 05:28:16 PM UTC 24 |
| Peak memory | 348408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968305067 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2968305067 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.1399252452 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5965696183 ps |
| CPU time | 339.09 seconds |
| Started | Aug 27 05:24:32 PM UTC 24 |
| Finished | Aug 27 05:30:17 PM UTC 24 |
| Peak memory | 252200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399252452 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1399252452 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.642588057 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 40387477 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 05:25:06 PM UTC 24 |
| Finished | Aug 27 05:25:08 PM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642588057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.642588057 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.2535140906 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 23755142 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 05:25:09 PM UTC 24 |
| Finished | Aug 27 05:25:11 PM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535140906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2535140906 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.1778871461 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1264559433 ps |
| CPU time | 38.55 seconds |
| Started | Aug 27 05:24:51 PM UTC 24 |
| Finished | Aug 27 05:25:32 PM UTC 24 |
| Peak memory | 258364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778871461 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.1778871461 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_error.3599605595 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 23863592020 ps |
| CPU time | 494.37 seconds |
| Started | Aug 27 05:24:59 PM UTC 24 |
| Finished | Aug 27 05:33:20 PM UTC 24 |
| Peak memory | 393440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599605595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3599605595 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.1438273389 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 266114707 ps |
| CPU time | 4.48 seconds |
| Started | Aug 27 05:25:00 PM UTC 24 |
| Finished | Aug 27 05:25:05 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438273389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1438273389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.3184378967 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11533405815 ps |
| CPU time | 57.18 seconds |
| Started | Aug 27 05:25:12 PM UTC 24 |
| Finished | Aug 27 05:26:11 PM UTC 24 |
| Peak memory | 262536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184378967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3184378967 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1976101454 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 12442749055 ps |
| CPU time | 312.27 seconds |
| Started | Aug 27 05:24:27 PM UTC 24 |
| Finished | Aug 27 05:29:44 PM UTC 24 |
| Peak memory | 399616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976101454 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1976101454 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.53754017 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 14279770316 ps |
| CPU time | 195.4 seconds |
| Started | Aug 27 05:24:27 PM UTC 24 |
| Finished | Aug 27 05:27:46 PM UTC 24 |
| Peak memory | 372980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53754017 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.53754017 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.1273906535 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 7951284627 ps |
| CPU time | 93.55 seconds |
| Started | Aug 27 05:24:25 PM UTC 24 |
| Finished | Aug 27 05:26:01 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273906535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1273906535 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.3185168051 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13168013221 ps |
| CPU time | 319.45 seconds |
| Started | Aug 27 05:25:13 PM UTC 24 |
| Finished | Aug 27 05:30:37 PM UTC 24 |
| Peak memory | 555652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185168051 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3185168051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/17.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.3997120739 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 29307364 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 05:27:06 PM UTC 24 |
| Finished | Aug 27 05:27:08 PM UTC 24 |
| Peak memory | 224492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997120739 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3997120739 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_app.124421743 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 11347428173 ps |
| CPU time | 343.12 seconds |
| Started | Aug 27 05:25:56 PM UTC 24 |
| Finished | Aug 27 05:31:43 PM UTC 24 |
| Peak memory | 487736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124421743 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.124421743 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.2760764274 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 17680502618 ps |
| CPU time | 922 seconds |
| Started | Aug 27 05:25:45 PM UTC 24 |
| Finished | Aug 27 05:41:18 PM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760764274 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2760764274 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2192642786 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3530267677 ps |
| CPU time | 38.34 seconds |
| Started | Aug 27 05:26:21 PM UTC 24 |
| Finished | Aug 27 05:27:01 PM UTC 24 |
| Peak memory | 245504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192642786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2192642786 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3280730352 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 44865562 ps |
| CPU time | 1.72 seconds |
| Started | Aug 27 05:27:02 PM UTC 24 |
| Finished | Aug 27 05:27:05 PM UTC 24 |
| Peak memory | 227460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280730352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3280730352 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3993514635 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 28554703142 ps |
| CPU time | 283.63 seconds |
| Started | Aug 27 05:26:02 PM UTC 24 |
| Finished | Aug 27 05:30:49 PM UTC 24 |
| Peak memory | 325948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993514635 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3993514635 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_error.4269996370 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1563529254 ps |
| CPU time | 142.79 seconds |
| Started | Aug 27 05:26:12 PM UTC 24 |
| Finished | Aug 27 05:28:37 PM UTC 24 |
| Peak memory | 295096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269996370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4269996370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.1426569716 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 81882098 ps |
| CPU time | 2.13 seconds |
| Started | Aug 27 05:26:17 PM UTC 24 |
| Finished | Aug 27 05:26:20 PM UTC 24 |
| Peak memory | 227364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426569716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1426569716 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.1030412696 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 246333828 ps |
| CPU time | 15.98 seconds |
| Started | Aug 27 05:27:02 PM UTC 24 |
| Finished | Aug 27 05:27:19 PM UTC 24 |
| Peak memory | 244252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030412696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1030412696 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1256074471 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 13728455431 ps |
| CPU time | 1587.56 seconds |
| Started | Aug 27 05:25:23 PM UTC 24 |
| Finished | Aug 27 05:52:10 PM UTC 24 |
| Peak memory | 1030400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256074471 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1256074471 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.2338482037 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 18748238222 ps |
| CPU time | 327.56 seconds |
| Started | Aug 27 05:25:32 PM UTC 24 |
| Finished | Aug 27 05:31:05 PM UTC 24 |
| Peak memory | 434492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338482037 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2338482037 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.323343878 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6576059456 ps |
| CPU time | 20.82 seconds |
| Started | Aug 27 05:25:22 PM UTC 24 |
| Finished | Aug 27 05:25:44 PM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323343878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.323343878 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.3971271506 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 62484239250 ps |
| CPU time | 2533.82 seconds |
| Started | Aug 27 05:27:06 PM UTC 24 |
| Finished | Aug 27 06:09:49 PM UTC 24 |
| Peak memory | 1274560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971271506 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3971271506 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/18.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.1700601938 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 29701482 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 05:28:06 PM UTC 24 |
| Finished | Aug 27 05:28:08 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700601938 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1700601938 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_app.3451486326 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 96405945454 ps |
| CPU time | 348.93 seconds |
| Started | Aug 27 05:27:33 PM UTC 24 |
| Finished | Aug 27 05:33:27 PM UTC 24 |
| Peak memory | 319800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451486326 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3451486326 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.2590873866 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 54565718115 ps |
| CPU time | 727.74 seconds |
| Started | Aug 27 05:27:20 PM UTC 24 |
| Finished | Aug 27 05:39:37 PM UTC 24 |
| Peak memory | 254328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590873866 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2590873866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.477804042 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 286990206 ps |
| CPU time | 10.11 seconds |
| Started | Aug 27 05:27:57 PM UTC 24 |
| Finished | Aug 27 05:28:09 PM UTC 24 |
| Peak memory | 233672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477804042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.477804042 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.779534560 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 149777158 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:28:01 PM UTC 24 |
| Finished | Aug 27 05:28:04 PM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779534560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.779534560 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1840076040 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6748573540 ps |
| CPU time | 303.6 seconds |
| Started | Aug 27 05:27:45 PM UTC 24 |
| Finished | Aug 27 05:32:53 PM UTC 24 |
| Peak memory | 311548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840076040 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1840076040 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2379880113 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 10053061805 ps |
| CPU time | 340.35 seconds |
| Started | Aug 27 05:27:46 PM UTC 24 |
| Finished | Aug 27 05:33:31 PM UTC 24 |
| Peak memory | 504056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379880113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2379880113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1330367694 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 855867128 ps |
| CPU time | 4.95 seconds |
| Started | Aug 27 05:27:54 PM UTC 24 |
| Finished | Aug 27 05:28:00 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330367694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1330367694 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.1537167303 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 121862037 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 05:28:01 PM UTC 24 |
| Finished | Aug 27 05:28:05 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537167303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1537167303 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.2338074525 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 77956225790 ps |
| CPU time | 2169.47 seconds |
| Started | Aug 27 05:27:09 PM UTC 24 |
| Finished | Aug 27 06:03:42 PM UTC 24 |
| Peak memory | 1388856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338074525 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.2338074525 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.3259501665 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 13443908428 ps |
| CPU time | 324.17 seconds |
| Started | Aug 27 05:27:12 PM UTC 24 |
| Finished | Aug 27 05:32:40 PM UTC 24 |
| Peak memory | 348480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259501665 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3259501665 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.1620340583 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2137958921 ps |
| CPU time | 46.31 seconds |
| Started | Aug 27 05:27:06 PM UTC 24 |
| Finished | Aug 27 05:27:53 PM UTC 24 |
| Peak memory | 235708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620340583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.1620340583 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.261615628 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 101362364647 ps |
| CPU time | 2315.29 seconds |
| Started | Aug 27 05:28:06 PM UTC 24 |
| Finished | Aug 27 06:07:09 PM UTC 24 |
| Peak memory | 1135304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261615628 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.261615628 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/19.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.2517594866 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 84208667 ps |
| CPU time | 1.32 seconds |
| Started | Aug 27 05:02:45 PM UTC 24 |
| Finished | Aug 27 05:02:47 PM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517594866 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2517594866 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_app.1952077834 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 40642608307 ps |
| CPU time | 92.5 seconds |
| Started | Aug 27 05:02:09 PM UTC 24 |
| Finished | Aug 27 05:03:43 PM UTC 24 |
| Peak memory | 303348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952077834 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1952077834 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.3915833402 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 24702699322 ps |
| CPU time | 333.85 seconds |
| Started | Aug 27 05:02:11 PM UTC 24 |
| Finished | Aug 27 05:07:49 PM UTC 24 |
| Peak memory | 502008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915833402 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3915833402 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.3462894795 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1893575489 ps |
| CPU time | 51.69 seconds |
| Started | Aug 27 05:02:32 PM UTC 24 |
| Finished | Aug 27 05:03:25 PM UTC 24 |
| Peak memory | 245740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462894795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3462894795 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.3290089056 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 371787491 ps |
| CPU time | 3.05 seconds |
| Started | Aug 27 05:02:39 PM UTC 24 |
| Finished | Aug 27 05:02:43 PM UTC 24 |
| Peak memory | 231920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290089056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3290089056 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_error.1980053293 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11831707970 ps |
| CPU time | 369.26 seconds |
| Started | Aug 27 05:02:27 PM UTC 24 |
| Finished | Aug 27 05:08:42 PM UTC 24 |
| Peak memory | 495924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980053293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1980053293 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.2858313800 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3712367951 ps |
| CPU time | 13.21 seconds |
| Started | Aug 27 05:02:28 PM UTC 24 |
| Finished | Aug 27 05:02:42 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858313800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2858313800 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.1022592217 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 45603661 ps |
| CPU time | 1.99 seconds |
| Started | Aug 27 05:02:40 PM UTC 24 |
| Finished | Aug 27 05:02:43 PM UTC 24 |
| Peak memory | 231364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022592217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1022592217 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.1351889614 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 35629705412 ps |
| CPU time | 1127.62 seconds |
| Started | Aug 27 05:01:41 PM UTC 24 |
| Finished | Aug 27 05:20:41 PM UTC 24 |
| Peak memory | 1603880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351889614 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.1351889614 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.53495684 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4571494709 ps |
| CPU time | 70.15 seconds |
| Started | Aug 27 05:02:45 PM UTC 24 |
| Finished | Aug 27 05:03:57 PM UTC 24 |
| Peak memory | 294460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53495684 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.53495684 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.3106098648 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2796789749 ps |
| CPU time | 21.21 seconds |
| Started | Aug 27 05:01:41 PM UTC 24 |
| Finished | Aug 27 05:02:03 PM UTC 24 |
| Peak memory | 239856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106098648 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3106098648 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.2720638515 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 645528297 ps |
| CPU time | 5.71 seconds |
| Started | Aug 27 05:01:36 PM UTC 24 |
| Finished | Aug 27 05:01:43 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720638515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2720638515 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.4079585972 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 232580988881 ps |
| CPU time | 1016.89 seconds |
| Started | Aug 27 05:02:43 PM UTC 24 |
| Finished | Aug 27 05:19:52 PM UTC 24 |
| Peak memory | 1155380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079585972 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4079585972 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.1686525275 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 32734301 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 05:02:05 PM UTC 24 |
| Finished | Aug 27 05:02:10 PM UTC 24 |
| Peak memory | 235716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686525275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.1686525275 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.4077036031 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 258533183 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 05:02:06 PM UTC 24 |
| Finished | Aug 27 05:02:11 PM UTC 24 |
| Peak memory | 227768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077036031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.4077036031 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3194380624 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4922757403 ps |
| CPU time | 52.62 seconds |
| Started | Aug 27 05:01:44 PM UTC 24 |
| Finished | Aug 27 05:02:38 PM UTC 24 |
| Peak memory | 235404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194380624 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3194380624 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3102186246 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 33679327504 ps |
| CPU time | 1933.45 seconds |
| Started | Aug 27 05:01:54 PM UTC 24 |
| Finished | Aug 27 05:34:29 PM UTC 24 |
| Peak memory | 1149092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102186246 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3102186246 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.2141747028 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 13056058942 ps |
| CPU time | 1424.86 seconds |
| Started | Aug 27 05:01:54 PM UTC 24 |
| Finished | Aug 27 05:25:55 PM UTC 24 |
| Peak memory | 903312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141747028 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2141747028 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.2053896538 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 56849026903 ps |
| CPU time | 1528.25 seconds |
| Started | Aug 27 05:01:58 PM UTC 24 |
| Finished | Aug 27 05:27:44 PM UTC 24 |
| Peak memory | 1695904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053896538 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.2053896538 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3514721116 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 21413628168 ps |
| CPU time | 2274.9 seconds |
| Started | Aug 27 05:01:59 PM UTC 24 |
| Finished | Aug 27 05:40:20 PM UTC 24 |
| Peak memory | 1327252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514721116 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3514721116 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.1585774531 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2791473325 ps |
| CPU time | 131.03 seconds |
| Started | Aug 27 05:02:04 PM UTC 24 |
| Finished | Aug 27 05:04:18 PM UTC 24 |
| Peak memory | 266428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585774531 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1585774531 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3635722113 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 13142095 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 05:29:00 PM UTC 24 |
| Finished | Aug 27 05:29:03 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635722113 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3635722113 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_app.998227482 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 316140423 ps |
| CPU time | 24.82 seconds |
| Started | Aug 27 05:28:30 PM UTC 24 |
| Finished | Aug 27 05:28:56 PM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998227482 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.998227482 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.4096511532 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 36765499773 ps |
| CPU time | 1005.52 seconds |
| Started | Aug 27 05:28:25 PM UTC 24 |
| Finished | Aug 27 05:45:23 PM UTC 24 |
| Peak memory | 262384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096511532 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4096511532 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2402823218 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4306567227 ps |
| CPU time | 83.71 seconds |
| Started | Aug 27 05:28:38 PM UTC 24 |
| Finished | Aug 27 05:30:04 PM UTC 24 |
| Peak memory | 278972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402823218 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2402823218 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_error.2342948278 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 10730224893 ps |
| CPU time | 112.71 seconds |
| Started | Aug 27 05:28:39 PM UTC 24 |
| Finished | Aug 27 05:30:34 PM UTC 24 |
| Peak memory | 311672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342948278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2342948278 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.136848596 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1643520983 ps |
| CPU time | 13.49 seconds |
| Started | Aug 27 05:28:48 PM UTC 24 |
| Finished | Aug 27 05:29:03 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136848596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.136848596 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.2315155386 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 110406192 ps |
| CPU time | 2.02 seconds |
| Started | Aug 27 05:28:56 PM UTC 24 |
| Finished | Aug 27 05:28:59 PM UTC 24 |
| Peak memory | 233876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315155386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2315155386 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3816238502 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 13131752354 ps |
| CPU time | 467.23 seconds |
| Started | Aug 27 05:28:10 PM UTC 24 |
| Finished | Aug 27 05:36:04 PM UTC 24 |
| Peak memory | 815424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816238502 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3816238502 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.3360384117 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 68140690755 ps |
| CPU time | 710.59 seconds |
| Started | Aug 27 05:28:17 PM UTC 24 |
| Finished | Aug 27 05:40:17 PM UTC 24 |
| Peak memory | 694584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360384117 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.3360384117 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.1795803445 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2060709096 ps |
| CPU time | 44.77 seconds |
| Started | Aug 27 05:28:09 PM UTC 24 |
| Finished | Aug 27 05:28:55 PM UTC 24 |
| Peak memory | 233868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795803445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1795803445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.492393590 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 63710601 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 05:28:58 PM UTC 24 |
| Finished | Aug 27 05:29:03 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492393590 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.492393590 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/20.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.1753386977 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 26292151 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:30:37 PM UTC 24 |
| Finished | Aug 27 05:30:39 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753386977 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1753386977 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_app.1668386222 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 51945253154 ps |
| CPU time | 240.4 seconds |
| Started | Aug 27 05:30:06 PM UTC 24 |
| Finished | Aug 27 05:34:10 PM UTC 24 |
| Peak memory | 395580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668386222 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.1668386222 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3058716646 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2900089750 ps |
| CPU time | 67.72 seconds |
| Started | Aug 27 05:29:45 PM UTC 24 |
| Finished | Aug 27 05:30:54 PM UTC 24 |
| Peak memory | 246056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058716646 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3058716646 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.922554654 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 15090412685 ps |
| CPU time | 336.07 seconds |
| Started | Aug 27 05:30:16 PM UTC 24 |
| Finished | Aug 27 05:35:57 PM UTC 24 |
| Peak memory | 459060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922554654 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.922554654 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_error.1535853385 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1034542389 ps |
| CPU time | 12.8 seconds |
| Started | Aug 27 05:30:17 PM UTC 24 |
| Finished | Aug 27 05:30:31 PM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535853385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1535853385 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2160380349 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1428703083 ps |
| CPU time | 17.19 seconds |
| Started | Aug 27 05:30:17 PM UTC 24 |
| Finished | Aug 27 05:30:36 PM UTC 24 |
| Peak memory | 227512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160380349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2160380349 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.1096194689 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 86292910 ps |
| CPU time | 6.46 seconds |
| Started | Aug 27 05:30:32 PM UTC 24 |
| Finished | Aug 27 05:30:40 PM UTC 24 |
| Peak memory | 235852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096194689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1096194689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.1362706657 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2784772854 ps |
| CPU time | 146.36 seconds |
| Started | Aug 27 05:29:05 PM UTC 24 |
| Finished | Aug 27 05:31:33 PM UTC 24 |
| Peak memory | 301328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362706657 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.1362706657 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.753514795 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 11291078107 ps |
| CPU time | 467.99 seconds |
| Started | Aug 27 05:29:05 PM UTC 24 |
| Finished | Aug 27 05:36:59 PM UTC 24 |
| Peak memory | 383288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753514795 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.753514795 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.341455302 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2458844438 ps |
| CPU time | 68.97 seconds |
| Started | Aug 27 05:29:04 PM UTC 24 |
| Finished | Aug 27 05:30:15 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341455302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.341455302 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.121989450 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 17356445318 ps |
| CPU time | 462.39 seconds |
| Started | Aug 27 05:30:35 PM UTC 24 |
| Finished | Aug 27 05:38:24 PM UTC 24 |
| Peak memory | 334696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121989450 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.121989450 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/21.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.3483500779 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 64098470 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 05:31:35 PM UTC 24 |
| Finished | Aug 27 05:31:37 PM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483500779 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3483500779 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_app.1896889298 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 5467571896 ps |
| CPU time | 377.62 seconds |
| Started | Aug 27 05:30:50 PM UTC 24 |
| Finished | Aug 27 05:37:14 PM UTC 24 |
| Peak memory | 346352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896889298 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1896889298 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.4172056069 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 89195211932 ps |
| CPU time | 1202.63 seconds |
| Started | Aug 27 05:30:42 PM UTC 24 |
| Finished | Aug 27 05:51:00 PM UTC 24 |
| Peak memory | 262452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172056069 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.4172056069 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.2144627203 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4085385767 ps |
| CPU time | 42.2 seconds |
| Started | Aug 27 05:30:55 PM UTC 24 |
| Finished | Aug 27 05:31:39 PM UTC 24 |
| Peak memory | 252156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144627203 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2144627203 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_error.1494046234 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9094337217 ps |
| CPU time | 302.05 seconds |
| Started | Aug 27 05:31:06 PM UTC 24 |
| Finished | Aug 27 05:36:13 PM UTC 24 |
| Peak memory | 473504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494046234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1494046234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.2315139048 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1078651453 ps |
| CPU time | 6.95 seconds |
| Started | Aug 27 05:31:24 PM UTC 24 |
| Finished | Aug 27 05:31:33 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315139048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2315139048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.3953678068 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 55264573 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 05:31:33 PM UTC 24 |
| Finished | Aug 27 05:31:37 PM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953678068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3953678068 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3196391893 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 94438595544 ps |
| CPU time | 4669.72 seconds |
| Started | Aug 27 05:30:40 PM UTC 24 |
| Finished | Aug 27 06:49:20 PM UTC 24 |
| Peak memory | 4501844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196391893 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3196391893 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3578935926 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 8199267989 ps |
| CPU time | 316.71 seconds |
| Started | Aug 27 05:30:41 PM UTC 24 |
| Finished | Aug 27 05:36:02 PM UTC 24 |
| Peak memory | 440640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578935926 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3578935926 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.4007514294 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6852335491 ps |
| CPU time | 53.42 seconds |
| Started | Aug 27 05:30:38 PM UTC 24 |
| Finished | Aug 27 05:31:33 PM UTC 24 |
| Peak memory | 235828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007514294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.4007514294 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.2546069533 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 268412978811 ps |
| CPU time | 1534.7 seconds |
| Started | Aug 27 05:31:34 PM UTC 24 |
| Finished | Aug 27 05:57:27 PM UTC 24 |
| Peak memory | 1000068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546069533 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2546069533 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/22.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.906215546 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 21618324 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 05:32:47 PM UTC 24 |
| Finished | Aug 27 05:32:49 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906215546 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.906215546 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_app.3604033383 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 17071153214 ps |
| CPU time | 401.72 seconds |
| Started | Aug 27 05:31:47 PM UTC 24 |
| Finished | Aug 27 05:38:34 PM UTC 24 |
| Peak memory | 522548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604033383 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3604033383 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.144782511 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 36541476441 ps |
| CPU time | 986.11 seconds |
| Started | Aug 27 05:31:44 PM UTC 24 |
| Finished | Aug 27 05:48:21 PM UTC 24 |
| Peak memory | 252160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144782511 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.144782511 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.3417368488 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 915989042 ps |
| CPU time | 43.33 seconds |
| Started | Aug 27 05:31:53 PM UTC 24 |
| Finished | Aug 27 05:32:38 PM UTC 24 |
| Peak memory | 241908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417368488 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3417368488 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_error.1354646779 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 20145684767 ps |
| CPU time | 211.18 seconds |
| Started | Aug 27 05:32:23 PM UTC 24 |
| Finished | Aug 27 05:35:58 PM UTC 24 |
| Peak memory | 366844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354646779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1354646779 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.1567073588 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1726603767 ps |
| CPU time | 6.66 seconds |
| Started | Aug 27 05:32:38 PM UTC 24 |
| Finished | Aug 27 05:32:46 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567073588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1567073588 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.3970527337 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 74823490 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:32:41 PM UTC 24 |
| Finished | Aug 27 05:32:44 PM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970527337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3970527337 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.2703925787 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 261317318643 ps |
| CPU time | 822.61 seconds |
| Started | Aug 27 05:31:38 PM UTC 24 |
| Finished | Aug 27 05:45:31 PM UTC 24 |
| Peak memory | 1081608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703925787 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.2703925787 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.2652936161 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 213311360 ps |
| CPU time | 11.37 seconds |
| Started | Aug 27 05:31:40 PM UTC 24 |
| Finished | Aug 27 05:31:52 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652936161 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2652936161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.217408469 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2036597883 ps |
| CPU time | 43.53 seconds |
| Started | Aug 27 05:31:38 PM UTC 24 |
| Finished | Aug 27 05:32:23 PM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217408469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.217408469 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.3143089244 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2331049155 ps |
| CPU time | 96.37 seconds |
| Started | Aug 27 05:32:45 PM UTC 24 |
| Finished | Aug 27 05:34:24 PM UTC 24 |
| Peak memory | 285008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143089244 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3143089244 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/23.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.1900936721 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 52292549 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:34:23 PM UTC 24 |
| Finished | Aug 27 05:34:25 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900936721 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1900936721 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_app.1131259663 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 12781256403 ps |
| CPU time | 497.11 seconds |
| Started | Aug 27 05:33:23 PM UTC 24 |
| Finished | Aug 27 05:41:47 PM UTC 24 |
| Peak memory | 508256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131259663 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1131259663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.1207357426 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3784441503 ps |
| CPU time | 439.54 seconds |
| Started | Aug 27 05:33:20 PM UTC 24 |
| Finished | Aug 27 05:40:46 PM UTC 24 |
| Peak memory | 241912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207357426 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.1207357426 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_error.1708509149 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 10410186521 ps |
| CPU time | 328.94 seconds |
| Started | Aug 27 05:33:32 PM UTC 24 |
| Finished | Aug 27 05:39:06 PM UTC 24 |
| Peak memory | 514360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708509149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1708509149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.1838256923 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1249491894 ps |
| CPU time | 15.96 seconds |
| Started | Aug 27 05:34:04 PM UTC 24 |
| Finished | Aug 27 05:34:22 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838256923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1838256923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.3497898251 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 119830352 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 05:34:11 PM UTC 24 |
| Finished | Aug 27 05:34:14 PM UTC 24 |
| Peak memory | 231244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497898251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3497898251 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.2732605037 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 79628326601 ps |
| CPU time | 2200.45 seconds |
| Started | Aug 27 05:32:54 PM UTC 24 |
| Finished | Aug 27 06:09:58 PM UTC 24 |
| Peak memory | 1395016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732605037 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.2732605037 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.4082533411 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2242260329 ps |
| CPU time | 105.53 seconds |
| Started | Aug 27 05:33:19 PM UTC 24 |
| Finished | Aug 27 05:35:07 PM UTC 24 |
| Peak memory | 264568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082533411 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.4082533411 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.1402697410 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 736522477 ps |
| CPU time | 31.1 seconds |
| Started | Aug 27 05:32:50 PM UTC 24 |
| Finished | Aug 27 05:33:22 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402697410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1402697410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.1390150410 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 9651354238 ps |
| CPU time | 556.73 seconds |
| Started | Aug 27 05:34:16 PM UTC 24 |
| Finished | Aug 27 05:43:39 PM UTC 24 |
| Peak memory | 314064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390150410 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1390150410 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/24.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.2939068225 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 36307466 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:36:06 PM UTC 24 |
| Finished | Aug 27 05:36:08 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939068225 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2939068225 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_app.2489439332 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 19521771567 ps |
| CPU time | 194.52 seconds |
| Started | Aug 27 05:35:07 PM UTC 24 |
| Finished | Aug 27 05:38:25 PM UTC 24 |
| Peak memory | 334056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489439332 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2489439332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.275928109 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 20243920333 ps |
| CPU time | 602.05 seconds |
| Started | Aug 27 05:34:58 PM UTC 24 |
| Finished | Aug 27 05:45:08 PM UTC 24 |
| Peak memory | 246120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275928109 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.275928109 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.4057229433 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 18083510642 ps |
| CPU time | 442.81 seconds |
| Started | Aug 27 05:35:49 PM UTC 24 |
| Finished | Aug 27 05:43:17 PM UTC 24 |
| Peak memory | 514296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057229433 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.4057229433 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_error.1217728279 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 11853576321 ps |
| CPU time | 434.31 seconds |
| Started | Aug 27 05:35:58 PM UTC 24 |
| Finished | Aug 27 05:43:18 PM UTC 24 |
| Peak memory | 549164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217728279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1217728279 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.1693306165 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1359441941 ps |
| CPU time | 14.75 seconds |
| Started | Aug 27 05:35:59 PM UTC 24 |
| Finished | Aug 27 05:36:15 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693306165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1693306165 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.3106953427 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 99236989 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 05:36:03 PM UTC 24 |
| Finished | Aug 27 05:36:06 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106953427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3106953427 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.4214478129 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 75580336094 ps |
| CPU time | 2222.5 seconds |
| Started | Aug 27 05:34:26 PM UTC 24 |
| Finished | Aug 27 06:11:52 PM UTC 24 |
| Peak memory | 2791732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214478129 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.4214478129 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.3659835048 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 13083415271 ps |
| CPU time | 296.77 seconds |
| Started | Aug 27 05:34:30 PM UTC 24 |
| Finished | Aug 27 05:39:31 PM UTC 24 |
| Peak memory | 495992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659835048 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3659835048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.2184263201 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3296576641 ps |
| CPU time | 80.33 seconds |
| Started | Aug 27 05:34:25 PM UTC 24 |
| Finished | Aug 27 05:35:47 PM UTC 24 |
| Peak memory | 235828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184263201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.2184263201 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.2050649133 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1399683802 ps |
| CPU time | 3.99 seconds |
| Started | Aug 27 05:36:04 PM UTC 24 |
| Finished | Aug 27 05:36:09 PM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050649133 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2050649133 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/25.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.708285906 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 23529143 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:37:13 PM UTC 24 |
| Finished | Aug 27 05:37:16 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708285906 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.708285906 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_app.862705797 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 35046433688 ps |
| CPU time | 216.12 seconds |
| Started | Aug 27 05:36:16 PM UTC 24 |
| Finished | Aug 27 05:39:55 PM UTC 24 |
| Peak memory | 358724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862705797 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.862705797 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.3708053171 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 26280075718 ps |
| CPU time | 1301.16 seconds |
| Started | Aug 27 05:36:14 PM UTC 24 |
| Finished | Aug 27 05:58:09 PM UTC 24 |
| Peak memory | 254276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708053171 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3708053171 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.429455619 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4878684508 ps |
| CPU time | 219.35 seconds |
| Started | Aug 27 05:36:30 PM UTC 24 |
| Finished | Aug 27 05:40:12 PM UTC 24 |
| Peak memory | 309564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429455619 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.429455619 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_error.2389699481 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3273920508 ps |
| CPU time | 256.67 seconds |
| Started | Aug 27 05:36:48 PM UTC 24 |
| Finished | Aug 27 05:41:09 PM UTC 24 |
| Peak memory | 334048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389699481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2389699481 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.540893096 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2370213681 ps |
| CPU time | 14.25 seconds |
| Started | Aug 27 05:36:57 PM UTC 24 |
| Finished | Aug 27 05:37:13 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540893096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.540893096 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.894368987 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3336711328 ps |
| CPU time | 45.14 seconds |
| Started | Aug 27 05:36:09 PM UTC 24 |
| Finished | Aug 27 05:36:56 PM UTC 24 |
| Peak memory | 266548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894368987 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.894368987 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.1144474785 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 21712381193 ps |
| CPU time | 407.22 seconds |
| Started | Aug 27 05:36:10 PM UTC 24 |
| Finished | Aug 27 05:43:03 PM UTC 24 |
| Peak memory | 375036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144474785 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1144474785 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.1495482073 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3868462023 ps |
| CPU time | 95.48 seconds |
| Started | Aug 27 05:36:07 PM UTC 24 |
| Finished | Aug 27 05:37:45 PM UTC 24 |
| Peak memory | 235828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495482073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1495482073 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2980291850 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 55837238410 ps |
| CPU time | 907.13 seconds |
| Started | Aug 27 05:37:04 PM UTC 24 |
| Finished | Aug 27 05:52:22 PM UTC 24 |
| Peak memory | 416460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980291850 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2980291850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/26.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.1123007644 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 18565638 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 05:38:43 PM UTC 24 |
| Finished | Aug 27 05:38:45 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123007644 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1123007644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_app.2803491653 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7393399801 ps |
| CPU time | 143.84 seconds |
| Started | Aug 27 05:38:13 PM UTC 24 |
| Finished | Aug 27 05:40:40 PM UTC 24 |
| Peak memory | 323892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803491653 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.2803491653 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.1346288093 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 9008000025 ps |
| CPU time | 98.37 seconds |
| Started | Aug 27 05:37:46 PM UTC 24 |
| Finished | Aug 27 05:39:26 PM UTC 24 |
| Peak memory | 252200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346288093 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1346288093 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.2022161253 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3404916328 ps |
| CPU time | 30.02 seconds |
| Started | Aug 27 05:38:13 PM UTC 24 |
| Finished | Aug 27 05:38:45 PM UTC 24 |
| Peak memory | 252216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022161253 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.2022161253 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_error.494900211 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3538200539 ps |
| CPU time | 130.13 seconds |
| Started | Aug 27 05:38:25 PM UTC 24 |
| Finished | Aug 27 05:40:38 PM UTC 24 |
| Peak memory | 324028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494900211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.494900211 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.2052869699 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4902122008 ps |
| CPU time | 14.6 seconds |
| Started | Aug 27 05:38:26 PM UTC 24 |
| Finished | Aug 27 05:38:42 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052869699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2052869699 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2739835178 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 79128717 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 05:38:35 PM UTC 24 |
| Finished | Aug 27 05:38:37 PM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739835178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2739835178 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.632168056 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 13773087234 ps |
| CPU time | 847.75 seconds |
| Started | Aug 27 05:37:17 PM UTC 24 |
| Finished | Aug 27 05:51:35 PM UTC 24 |
| Peak memory | 655660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632168056 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.632168056 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.1196656408 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 89999410982 ps |
| CPU time | 723.01 seconds |
| Started | Aug 27 05:37:43 PM UTC 24 |
| Finished | Aug 27 05:49:55 PM UTC 24 |
| Peak memory | 696628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196656408 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.1196656408 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.683018862 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 7242787006 ps |
| CPU time | 56.17 seconds |
| Started | Aug 27 05:37:15 PM UTC 24 |
| Finished | Aug 27 05:38:12 PM UTC 24 |
| Peak memory | 235836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683018862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.683018862 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.2308090976 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 24351088490 ps |
| CPU time | 1619.24 seconds |
| Started | Aug 27 05:38:39 PM UTC 24 |
| Finished | Aug 27 06:05:57 PM UTC 24 |
| Peak memory | 606852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308090976 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2308090976 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/27.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2476822164 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 16865888 ps |
| CPU time | 1.35 seconds |
| Started | Aug 27 05:39:56 PM UTC 24 |
| Finished | Aug 27 05:39:59 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476822164 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2476822164 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_app.3943264806 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3936748228 ps |
| CPU time | 97.15 seconds |
| Started | Aug 27 05:39:12 PM UTC 24 |
| Finished | Aug 27 05:40:52 PM UTC 24 |
| Peak memory | 287152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943264806 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3943264806 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.4138154480 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 55185766674 ps |
| CPU time | 824.2 seconds |
| Started | Aug 27 05:39:12 PM UTC 24 |
| Finished | Aug 27 05:53:07 PM UTC 24 |
| Peak memory | 256300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138154480 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.4138154480 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2210291048 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1250986795 ps |
| CPU time | 57.72 seconds |
| Started | Aug 27 05:39:28 PM UTC 24 |
| Finished | Aug 27 05:40:27 PM UTC 24 |
| Peak memory | 250012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210291048 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2210291048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_error.1222349412 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 22501154614 ps |
| CPU time | 407.5 seconds |
| Started | Aug 27 05:39:32 PM UTC 24 |
| Finished | Aug 27 05:46:25 PM UTC 24 |
| Peak memory | 389436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222349412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1222349412 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1830149983 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 4944975398 ps |
| CPU time | 11.44 seconds |
| Started | Aug 27 05:39:38 PM UTC 24 |
| Finished | Aug 27 05:39:51 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830149983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1830149983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.3643686803 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 40982850 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 05:39:52 PM UTC 24 |
| Finished | Aug 27 05:39:55 PM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643686803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3643686803 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.190438743 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 38207133538 ps |
| CPU time | 1089.88 seconds |
| Started | Aug 27 05:38:46 PM UTC 24 |
| Finished | Aug 27 05:57:08 PM UTC 24 |
| Peak memory | 1605932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190438743 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.190438743 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.1675354508 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 10097629933 ps |
| CPU time | 231.16 seconds |
| Started | Aug 27 05:39:06 PM UTC 24 |
| Finished | Aug 27 05:43:01 PM UTC 24 |
| Peak memory | 319868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675354508 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1675354508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.2450003219 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1856465885 ps |
| CPU time | 24.49 seconds |
| Started | Aug 27 05:38:46 PM UTC 24 |
| Finished | Aug 27 05:39:12 PM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450003219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2450003219 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.87857098 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 149269864 ps |
| CPU time | 4.96 seconds |
| Started | Aug 27 05:39:56 PM UTC 24 |
| Finished | Aug 27 05:40:02 PM UTC 24 |
| Peak memory | 235444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87857098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.87857098 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/28.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.377572784 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 14566879 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 05:40:39 PM UTC 24 |
| Finished | Aug 27 05:40:41 PM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377572784 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.377572784 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_app.1277847565 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1770543027 ps |
| CPU time | 31.31 seconds |
| Started | Aug 27 05:40:14 PM UTC 24 |
| Finished | Aug 27 05:40:46 PM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277847565 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1277847565 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.304547690 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 4905840672 ps |
| CPU time | 444.41 seconds |
| Started | Aug 27 05:40:14 PM UTC 24 |
| Finished | Aug 27 05:47:44 PM UTC 24 |
| Peak memory | 244028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304547690 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.304547690 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2116288499 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 24109411913 ps |
| CPU time | 230.02 seconds |
| Started | Aug 27 05:40:18 PM UTC 24 |
| Finished | Aug 27 05:44:11 PM UTC 24 |
| Peak memory | 315708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116288499 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2116288499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2083450556 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 15833845860 ps |
| CPU time | 434.16 seconds |
| Started | Aug 27 05:40:21 PM UTC 24 |
| Finished | Aug 27 05:47:41 PM UTC 24 |
| Peak memory | 565564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083450556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2083450556 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.947747592 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1649333986 ps |
| CPU time | 13.41 seconds |
| Started | Aug 27 05:40:28 PM UTC 24 |
| Finished | Aug 27 05:40:43 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947747592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.947747592 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.1892930907 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 61670447 ps |
| CPU time | 2.06 seconds |
| Started | Aug 27 05:40:33 PM UTC 24 |
| Finished | Aug 27 05:40:36 PM UTC 24 |
| Peak memory | 233812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892930907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.1892930907 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2819254918 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 151971710325 ps |
| CPU time | 3821.87 seconds |
| Started | Aug 27 05:40:03 PM UTC 24 |
| Finished | Aug 27 06:44:28 PM UTC 24 |
| Peak memory | 3705148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819254918 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2819254918 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.2588566933 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 25580684932 ps |
| CPU time | 196.43 seconds |
| Started | Aug 27 05:40:03 PM UTC 24 |
| Finished | Aug 27 05:43:23 PM UTC 24 |
| Peak memory | 387388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588566933 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2588566933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.2703380836 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 986491318 ps |
| CPU time | 12.21 seconds |
| Started | Aug 27 05:39:59 PM UTC 24 |
| Finished | Aug 27 05:40:13 PM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703380836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2703380836 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.2832745137 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 51307912843 ps |
| CPU time | 1907.82 seconds |
| Started | Aug 27 05:40:37 PM UTC 24 |
| Finished | Aug 27 06:12:47 PM UTC 24 |
| Peak memory | 506240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832745137 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2832745137 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/29.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.3370492094 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 20899212 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 05:04:33 PM UTC 24 |
| Finished | Aug 27 05:04:35 PM UTC 24 |
| Peak memory | 226296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370492094 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3370492094 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_app.863117149 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2137782464 ps |
| CPU time | 159.25 seconds |
| Started | Aug 27 05:03:51 PM UTC 24 |
| Finished | Aug 27 05:06:33 PM UTC 24 |
| Peak memory | 276664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863117149 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.863117149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1240792976 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 14824076771 ps |
| CPU time | 173.31 seconds |
| Started | Aug 27 05:03:55 PM UTC 24 |
| Finished | Aug 27 05:06:51 PM UTC 24 |
| Peak memory | 336244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240792976 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1240792976 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3355436332 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 6122363278 ps |
| CPU time | 660.23 seconds |
| Started | Aug 27 05:03:11 PM UTC 24 |
| Finished | Aug 27 05:14:20 PM UTC 24 |
| Peak memory | 246068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355436332 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3355436332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.2444679637 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1088411628 ps |
| CPU time | 17.82 seconds |
| Started | Aug 27 05:04:19 PM UTC 24 |
| Finished | Aug 27 05:04:38 PM UTC 24 |
| Peak memory | 234628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444679637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2444679637 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.4110589374 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2324530429 ps |
| CPU time | 47.16 seconds |
| Started | Aug 27 05:04:21 PM UTC 24 |
| Finished | Aug 27 05:05:10 PM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110589374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4110589374 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.2076950109 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 12886547901 ps |
| CPU time | 46.3 seconds |
| Started | Aug 27 05:04:21 PM UTC 24 |
| Finished | Aug 27 05:05:09 PM UTC 24 |
| Peak memory | 235900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076950109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2076950109 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3274401933 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 20739114090 ps |
| CPU time | 167.18 seconds |
| Started | Aug 27 05:03:56 PM UTC 24 |
| Finished | Aug 27 05:06:46 PM UTC 24 |
| Peak memory | 336176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274401933 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3274401933 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_error.2795673822 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5132507418 ps |
| CPU time | 116.7 seconds |
| Started | Aug 27 05:04:00 PM UTC 24 |
| Finished | Aug 27 05:05:59 PM UTC 24 |
| Peak memory | 285048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795673822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2795673822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.4164275017 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1783597115 ps |
| CPU time | 12.57 seconds |
| Started | Aug 27 05:04:06 PM UTC 24 |
| Finished | Aug 27 05:04:19 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164275017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.4164275017 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.490616165 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 93569930544 ps |
| CPU time | 4146.21 seconds |
| Started | Aug 27 05:02:48 PM UTC 24 |
| Finished | Aug 27 06:12:41 PM UTC 24 |
| Peak memory | 3895624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490616165 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.490616165 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.1412538464 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 9801217132 ps |
| CPU time | 176.99 seconds |
| Started | Aug 27 05:04:33 PM UTC 24 |
| Finished | Aug 27 05:07:33 PM UTC 24 |
| Peak memory | 333372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412538464 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1412538464 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.3457918447 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13338101054 ps |
| CPU time | 513.23 seconds |
| Started | Aug 27 05:02:55 PM UTC 24 |
| Finished | Aug 27 05:11:35 PM UTC 24 |
| Peak memory | 592180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457918447 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3457918447 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.3765776246 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1078574959 ps |
| CPU time | 27.52 seconds |
| Started | Aug 27 05:02:48 PM UTC 24 |
| Finished | Aug 27 05:03:17 PM UTC 24 |
| Peak memory | 235708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765776246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3765776246 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.2590806761 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 88520065212 ps |
| CPU time | 2355.56 seconds |
| Started | Aug 27 05:04:27 PM UTC 24 |
| Finished | Aug 27 05:44:10 PM UTC 24 |
| Peak memory | 987384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590806761 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2590806761 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.144941549 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 104133589 ps |
| CPU time | 4.4 seconds |
| Started | Aug 27 05:03:44 PM UTC 24 |
| Finished | Aug 27 05:03:49 PM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144941549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.144941549 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.4256183003 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 51574270 ps |
| CPU time | 3.33 seconds |
| Started | Aug 27 05:03:50 PM UTC 24 |
| Finished | Aug 27 05:03:54 PM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256183003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4256183003 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.332706219 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 16950337791 ps |
| CPU time | 68.66 seconds |
| Started | Aug 27 05:03:17 PM UTC 24 |
| Finished | Aug 27 05:04:28 PM UTC 24 |
| Peak memory | 262380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332706219 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.332706219 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.1343953415 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 8426720185 ps |
| CPU time | 61.63 seconds |
| Started | Aug 27 05:03:22 PM UTC 24 |
| Finished | Aug 27 05:04:26 PM UTC 24 |
| Peak memory | 256184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343953415 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1343953415 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3856799369 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 27661024579 ps |
| CPU time | 1354.83 seconds |
| Started | Aug 27 05:03:26 PM UTC 24 |
| Finished | Aug 27 05:26:16 PM UTC 24 |
| Peak memory | 940196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856799369 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3856799369 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.879524508 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4071098644 ps |
| CPU time | 26.14 seconds |
| Started | Aug 27 05:03:37 PM UTC 24 |
| Finished | Aug 27 05:04:05 PM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879524508 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.879524508 +enable _masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3801270216 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 255004424922 ps |
| CPU time | 2874.1 seconds |
| Started | Aug 27 05:03:40 PM UTC 24 |
| Finished | Aug 27 05:52:05 PM UTC 24 |
| Peak memory | 3639444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801270216 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3801270216 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.1157467364 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 344789821375 ps |
| CPU time | 2793.26 seconds |
| Started | Aug 27 05:03:41 PM UTC 24 |
| Finished | Aug 27 05:50:47 PM UTC 24 |
| Peak memory | 3027088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157467364 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.1157467364 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.3641414903 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 55909288 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 05:41:33 PM UTC 24 |
| Finished | Aug 27 05:41:35 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641414903 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3641414903 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_app.660833726 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 114272667043 ps |
| CPU time | 346.72 seconds |
| Started | Aug 27 05:40:47 PM UTC 24 |
| Finished | Aug 27 05:46:38 PM UTC 24 |
| Peak memory | 465140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660833726 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.660833726 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.3668737269 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 27417039594 ps |
| CPU time | 1478.31 seconds |
| Started | Aug 27 05:40:47 PM UTC 24 |
| Finished | Aug 27 06:05:43 PM UTC 24 |
| Peak memory | 256240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668737269 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3668737269 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.1216886330 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5745897501 ps |
| CPU time | 105.72 seconds |
| Started | Aug 27 05:40:53 PM UTC 24 |
| Finished | Aug 27 05:42:41 PM UTC 24 |
| Peak memory | 289080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216886330 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1216886330 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_error.2589220332 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3240395914 ps |
| CPU time | 289.63 seconds |
| Started | Aug 27 05:41:09 PM UTC 24 |
| Finished | Aug 27 05:46:03 PM UTC 24 |
| Peak memory | 334068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589220332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2589220332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3925100448 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 674249090 ps |
| CPU time | 11.05 seconds |
| Started | Aug 27 05:41:19 PM UTC 24 |
| Finished | Aug 27 05:41:32 PM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925100448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3925100448 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.341461999 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 198225377 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:41:28 PM UTC 24 |
| Finished | Aug 27 05:41:32 PM UTC 24 |
| Peak memory | 233848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341461999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.341461999 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.1918849546 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 24397655161 ps |
| CPU time | 2296.88 seconds |
| Started | Aug 27 05:40:42 PM UTC 24 |
| Finished | Aug 27 06:19:24 PM UTC 24 |
| Peak memory | 1403132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918849546 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.1918849546 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.3502001331 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 10114506353 ps |
| CPU time | 393.36 seconds |
| Started | Aug 27 05:40:44 PM UTC 24 |
| Finished | Aug 27 05:47:22 PM UTC 24 |
| Peak memory | 377140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502001331 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3502001331 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.1141625514 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3414826945 ps |
| CPU time | 45.59 seconds |
| Started | Aug 27 05:40:40 PM UTC 24 |
| Finished | Aug 27 05:41:27 PM UTC 24 |
| Peak memory | 235896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141625514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1141625514 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.1677170389 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 97420513531 ps |
| CPU time | 2271.61 seconds |
| Started | Aug 27 05:41:33 PM UTC 24 |
| Finished | Aug 27 06:19:49 PM UTC 24 |
| Peak memory | 993988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677170389 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1677170389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/30.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.1913836941 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 21335239 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 05:43:19 PM UTC 24 |
| Finished | Aug 27 05:43:21 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913836941 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1913836941 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_app.3167979564 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 25106154256 ps |
| CPU time | 341.02 seconds |
| Started | Aug 27 05:42:41 PM UTC 24 |
| Finished | Aug 27 05:48:27 PM UTC 24 |
| Peak memory | 327996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167979564 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3167979564 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.1712672809 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1015855022 ps |
| CPU time | 55.15 seconds |
| Started | Aug 27 05:42:11 PM UTC 24 |
| Finished | Aug 27 05:43:08 PM UTC 24 |
| Peak memory | 235752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712672809 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1712672809 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.818340905 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 65677982687 ps |
| CPU time | 383.64 seconds |
| Started | Aug 27 05:42:51 PM UTC 24 |
| Finished | Aug 27 05:49:20 PM UTC 24 |
| Peak memory | 532920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818340905 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.818340905 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_error.718406257 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 16406890770 ps |
| CPU time | 131.8 seconds |
| Started | Aug 27 05:43:02 PM UTC 24 |
| Finished | Aug 27 05:45:16 PM UTC 24 |
| Peak memory | 330040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718406257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.718406257 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.1728795021 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5948321487 ps |
| CPU time | 14.33 seconds |
| Started | Aug 27 05:43:04 PM UTC 24 |
| Finished | Aug 27 05:43:19 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728795021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1728795021 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.2437902518 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 369319698 ps |
| CPU time | 13.48 seconds |
| Started | Aug 27 05:43:09 PM UTC 24 |
| Finished | Aug 27 05:43:23 PM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437902518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2437902518 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.2716437376 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 20842045900 ps |
| CPU time | 2193.99 seconds |
| Started | Aug 27 05:41:48 PM UTC 24 |
| Finished | Aug 27 06:18:46 PM UTC 24 |
| Peak memory | 1413344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716437376 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.2716437376 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.3955985159 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 38832443586 ps |
| CPU time | 332.82 seconds |
| Started | Aug 27 05:41:52 PM UTC 24 |
| Finished | Aug 27 05:47:29 PM UTC 24 |
| Peak memory | 485676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955985159 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3955985159 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.1971190445 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 16210518767 ps |
| CPU time | 73.15 seconds |
| Started | Aug 27 05:41:36 PM UTC 24 |
| Finished | Aug 27 05:42:51 PM UTC 24 |
| Peak memory | 235744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971190445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1971190445 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.608090955 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4547443438 ps |
| CPU time | 121.05 seconds |
| Started | Aug 27 05:43:18 PM UTC 24 |
| Finished | Aug 27 05:45:21 PM UTC 24 |
| Peak memory | 330380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608090955 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.608090955 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/31.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.1079539805 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 102730920 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 05:45:06 PM UTC 24 |
| Finished | Aug 27 05:45:09 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079539805 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1079539805 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_app.1972768897 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1146351310 ps |
| CPU time | 97.95 seconds |
| Started | Aug 27 05:43:40 PM UTC 24 |
| Finished | Aug 27 05:45:20 PM UTC 24 |
| Peak memory | 258232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972768897 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1972768897 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.277829793 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 101039074285 ps |
| CPU time | 1205.95 seconds |
| Started | Aug 27 05:43:24 PM UTC 24 |
| Finished | Aug 27 06:03:44 PM UTC 24 |
| Peak memory | 272628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277829793 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.277829793 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2607210232 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 33457547586 ps |
| CPU time | 413.87 seconds |
| Started | Aug 27 05:44:11 PM UTC 24 |
| Finished | Aug 27 05:51:11 PM UTC 24 |
| Peak memory | 518524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607210232 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2607210232 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_error.111546553 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 579951055 ps |
| CPU time | 51.78 seconds |
| Started | Aug 27 05:44:12 PM UTC 24 |
| Finished | Aug 27 05:45:06 PM UTC 24 |
| Peak memory | 262332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111546553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.111546553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2031083579 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1699982442 ps |
| CPU time | 21.79 seconds |
| Started | Aug 27 05:44:22 PM UTC 24 |
| Finished | Aug 27 05:44:45 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031083579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2031083579 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.842854487 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 35963201 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 05:44:46 PM UTC 24 |
| Finished | Aug 27 05:44:49 PM UTC 24 |
| Peak memory | 231308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842854487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.842854487 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.574301862 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 53833504651 ps |
| CPU time | 3016.4 seconds |
| Started | Aug 27 05:43:22 PM UTC 24 |
| Finished | Aug 27 06:34:12 PM UTC 24 |
| Peak memory | 1816812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574301862 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.574301862 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.3492736249 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5130727711 ps |
| CPU time | 440.26 seconds |
| Started | Aug 27 05:43:24 PM UTC 24 |
| Finished | Aug 27 05:50:51 PM UTC 24 |
| Peak memory | 381172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492736249 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3492736249 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.2338606144 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2352674449 ps |
| CPU time | 59.66 seconds |
| Started | Aug 27 05:43:20 PM UTC 24 |
| Finished | Aug 27 05:44:22 PM UTC 24 |
| Peak memory | 235872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338606144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2338606144 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.74029721 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 30721672880 ps |
| CPU time | 628.1 seconds |
| Started | Aug 27 05:44:50 PM UTC 24 |
| Finished | Aug 27 05:55:26 PM UTC 24 |
| Peak memory | 592600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74029721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.74029721 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/32.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2006394644 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 131326917 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 05:46:04 PM UTC 24 |
| Finished | Aug 27 05:46:06 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006394644 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2006394644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_app.552795425 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 59658883727 ps |
| CPU time | 449.21 seconds |
| Started | Aug 27 05:45:22 PM UTC 24 |
| Finished | Aug 27 05:52:57 PM UTC 24 |
| Peak memory | 543160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552795425 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.552795425 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.3507903048 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 64332834358 ps |
| CPU time | 1083.62 seconds |
| Started | Aug 27 05:45:21 PM UTC 24 |
| Finished | Aug 27 06:03:37 PM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507903048 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3507903048 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.2029555770 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 38154478468 ps |
| CPU time | 291.47 seconds |
| Started | Aug 27 05:45:23 PM UTC 24 |
| Finished | Aug 27 05:50:19 PM UTC 24 |
| Peak memory | 450872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029555770 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.2029555770 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3578364823 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 6088667608 ps |
| CPU time | 127.5 seconds |
| Started | Aug 27 05:45:24 PM UTC 24 |
| Finished | Aug 27 05:47:34 PM UTC 24 |
| Peak memory | 317684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578364823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3578364823 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.1090807489 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3555265113 ps |
| CPU time | 8.06 seconds |
| Started | Aug 27 05:45:32 PM UTC 24 |
| Finished | Aug 27 05:45:42 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090807489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.1090807489 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.3749564144 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 35798416 ps |
| CPU time | 1.84 seconds |
| Started | Aug 27 05:45:42 PM UTC 24 |
| Finished | Aug 27 05:45:45 PM UTC 24 |
| Peak memory | 231284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749564144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.3749564144 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.339221219 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 112755716277 ps |
| CPU time | 4506.28 seconds |
| Started | Aug 27 05:45:10 PM UTC 24 |
| Finished | Aug 27 07:01:04 PM UTC 24 |
| Peak memory | 4407648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339221219 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.339221219 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.2656508049 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 4662222852 ps |
| CPU time | 194.44 seconds |
| Started | Aug 27 05:45:17 PM UTC 24 |
| Finished | Aug 27 05:48:34 PM UTC 24 |
| Peak memory | 293180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656508049 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2656508049 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.548083860 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 348836909 ps |
| CPU time | 12.66 seconds |
| Started | Aug 27 05:45:09 PM UTC 24 |
| Finished | Aug 27 05:45:22 PM UTC 24 |
| Peak memory | 235324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548083860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.548083860 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.3316881499 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 38807323450 ps |
| CPU time | 745.07 seconds |
| Started | Aug 27 05:45:47 PM UTC 24 |
| Finished | Aug 27 05:58:21 PM UTC 24 |
| Peak memory | 512784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316881499 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.3316881499 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/33.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3220148801 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 29707147 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 05:47:35 PM UTC 24 |
| Finished | Aug 27 05:47:38 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220148801 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3220148801 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_app.857564616 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 25173857452 ps |
| CPU time | 94.84 seconds |
| Started | Aug 27 05:46:38 PM UTC 24 |
| Finished | Aug 27 05:48:15 PM UTC 24 |
| Peak memory | 282972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857564616 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.857564616 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.2289595571 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 24739236660 ps |
| CPU time | 1421.89 seconds |
| Started | Aug 27 05:46:25 PM UTC 24 |
| Finished | Aug 27 06:10:25 PM UTC 24 |
| Peak memory | 268532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289595571 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2289595571 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.525731411 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 104701765104 ps |
| CPU time | 400.89 seconds |
| Started | Aug 27 05:46:40 PM UTC 24 |
| Finished | Aug 27 05:53:26 PM UTC 24 |
| Peak memory | 493884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525731411 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.525731411 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_error.1097707216 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1509012248 ps |
| CPU time | 77.25 seconds |
| Started | Aug 27 05:47:20 PM UTC 24 |
| Finished | Aug 27 05:48:39 PM UTC 24 |
| Peak memory | 264436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097707216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1097707216 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.1180912009 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1105446909 ps |
| CPU time | 12.48 seconds |
| Started | Aug 27 05:47:23 PM UTC 24 |
| Finished | Aug 27 05:47:37 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180912009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.1180912009 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.228129971 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 55479297 ps |
| CPU time | 1.94 seconds |
| Started | Aug 27 05:47:30 PM UTC 24 |
| Finished | Aug 27 05:47:33 PM UTC 24 |
| Peak memory | 233352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228129971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.228129971 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3684832035 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 515734083 ps |
| CPU time | 24.91 seconds |
| Started | Aug 27 05:46:11 PM UTC 24 |
| Finished | Aug 27 05:46:37 PM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684832035 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3684832035 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.3047597490 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4751297693 ps |
| CPU time | 163.13 seconds |
| Started | Aug 27 05:46:17 PM UTC 24 |
| Finished | Aug 27 05:49:03 PM UTC 24 |
| Peak memory | 340272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047597490 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3047597490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.50687400 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11060109581 ps |
| CPU time | 92.11 seconds |
| Started | Aug 27 05:46:07 PM UTC 24 |
| Finished | Aug 27 05:47:41 PM UTC 24 |
| Peak memory | 235836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50687400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.50687400 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.512740752 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 224746436093 ps |
| CPU time | 1331.47 seconds |
| Started | Aug 27 05:47:34 PM UTC 24 |
| Finished | Aug 27 06:10:00 PM UTC 24 |
| Peak memory | 1442040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512740752 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.512740752 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/34.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1326082540 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 43793504 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:48:22 PM UTC 24 |
| Finished | Aug 27 05:48:25 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326082540 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1326082540 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_app.2097953874 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 4054172840 ps |
| CPU time | 20.15 seconds |
| Started | Aug 27 05:47:44 PM UTC 24 |
| Finished | Aug 27 05:48:06 PM UTC 24 |
| Peak memory | 243988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097953874 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2097953874 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.1658135263 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 15560387606 ps |
| CPU time | 440.54 seconds |
| Started | Aug 27 05:47:42 PM UTC 24 |
| Finished | Aug 27 05:55:09 PM UTC 24 |
| Peak memory | 241976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658135263 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1658135263 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3255743490 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 724236392 ps |
| CPU time | 17.12 seconds |
| Started | Aug 27 05:47:49 PM UTC 24 |
| Finished | Aug 27 05:48:08 PM UTC 24 |
| Peak memory | 234680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255743490 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3255743490 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_error.1974130082 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 6284618819 ps |
| CPU time | 214.48 seconds |
| Started | Aug 27 05:48:02 PM UTC 24 |
| Finished | Aug 27 05:51:39 PM UTC 24 |
| Peak memory | 358696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974130082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.1974130082 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.3840654586 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3614300638 ps |
| CPU time | 22.65 seconds |
| Started | Aug 27 05:48:07 PM UTC 24 |
| Finished | Aug 27 05:48:31 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840654586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3840654586 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.4180305162 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 927808753 ps |
| CPU time | 32.41 seconds |
| Started | Aug 27 05:48:09 PM UTC 24 |
| Finished | Aug 27 05:48:43 PM UTC 24 |
| Peak memory | 256312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180305162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.4180305162 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.3062088916 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 61818805500 ps |
| CPU time | 1104.61 seconds |
| Started | Aug 27 05:47:39 PM UTC 24 |
| Finished | Aug 27 06:06:15 PM UTC 24 |
| Peak memory | 874748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062088916 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.3062088916 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.4075198145 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 16523323911 ps |
| CPU time | 496.51 seconds |
| Started | Aug 27 05:47:42 PM UTC 24 |
| Finished | Aug 27 05:56:05 PM UTC 24 |
| Peak memory | 577852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075198145 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.4075198145 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.4102171942 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 196424062 ps |
| CPU time | 9.59 seconds |
| Started | Aug 27 05:47:38 PM UTC 24 |
| Finished | Aug 27 05:47:48 PM UTC 24 |
| Peak memory | 235772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102171942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4102171942 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.2415170077 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2944657051 ps |
| CPU time | 20.27 seconds |
| Started | Aug 27 05:48:16 PM UTC 24 |
| Finished | Aug 27 05:48:37 PM UTC 24 |
| Peak memory | 252156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415170077 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.2415170077 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/35.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.2574771249 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 39220591 ps |
| CPU time | 1.34 seconds |
| Started | Aug 27 05:49:04 PM UTC 24 |
| Finished | Aug 27 05:49:06 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574771249 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2574771249 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2461594691 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3089424605 ps |
| CPU time | 111.18 seconds |
| Started | Aug 27 05:48:38 PM UTC 24 |
| Finished | Aug 27 05:50:32 PM UTC 24 |
| Peak memory | 260376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461594691 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2461594691 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.1537309612 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 239659844493 ps |
| CPU time | 1027.68 seconds |
| Started | Aug 27 05:48:36 PM UTC 24 |
| Finished | Aug 27 06:05:56 PM UTC 24 |
| Peak memory | 258336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537309612 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1537309612 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2181781454 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 372368958 ps |
| CPU time | 5.58 seconds |
| Started | Aug 27 05:48:40 PM UTC 24 |
| Finished | Aug 27 05:48:47 PM UTC 24 |
| Peak memory | 231852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181781454 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2181781454 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_error.303030689 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3249920706 ps |
| CPU time | 138.63 seconds |
| Started | Aug 27 05:48:43 PM UTC 24 |
| Finished | Aug 27 05:51:05 PM UTC 24 |
| Peak memory | 280884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303030689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.303030689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.3159496163 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1190550197 ps |
| CPU time | 14.83 seconds |
| Started | Aug 27 05:48:48 PM UTC 24 |
| Finished | Aug 27 05:49:04 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159496163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3159496163 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.4070785371 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 59663027 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 05:49:00 PM UTC 24 |
| Finished | Aug 27 05:49:02 PM UTC 24 |
| Peak memory | 231300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070785371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.4070785371 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.1737082291 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 407929095823 ps |
| CPU time | 3790.06 seconds |
| Started | Aug 27 05:48:29 PM UTC 24 |
| Finished | Aug 27 06:52:19 PM UTC 24 |
| Peak memory | 3807548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737082291 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.1737082291 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1929668045 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 61965922139 ps |
| CPU time | 541.69 seconds |
| Started | Aug 27 05:48:32 PM UTC 24 |
| Finished | Aug 27 05:57:40 PM UTC 24 |
| Peak memory | 680228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929668045 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1929668045 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3861801861 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 11072821022 ps |
| CPU time | 88.3 seconds |
| Started | Aug 27 05:48:26 PM UTC 24 |
| Finished | Aug 27 05:49:57 PM UTC 24 |
| Peak memory | 235688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861801861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3861801861 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.1477825086 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 35432922496 ps |
| CPU time | 807.25 seconds |
| Started | Aug 27 05:49:04 PM UTC 24 |
| Finished | Aug 27 06:02:41 PM UTC 24 |
| Peak memory | 439112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477825086 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1477825086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/36.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.532546044 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 15871570 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:50:05 PM UTC 24 |
| Finished | Aug 27 05:50:07 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532546044 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.532546044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_app.1197608549 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4621264502 ps |
| CPU time | 174.81 seconds |
| Started | Aug 27 05:49:21 PM UTC 24 |
| Finished | Aug 27 05:52:19 PM UTC 24 |
| Peak memory | 282844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197608549 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1197608549 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1913339386 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 50873813455 ps |
| CPU time | 1115.57 seconds |
| Started | Aug 27 05:49:21 PM UTC 24 |
| Finished | Aug 27 06:08:09 PM UTC 24 |
| Peak memory | 266520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913339386 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1913339386 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2275125475 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 35773876356 ps |
| CPU time | 196.33 seconds |
| Started | Aug 27 05:49:42 PM UTC 24 |
| Finished | Aug 27 05:53:01 PM UTC 24 |
| Peak memory | 375040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275125475 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2275125475 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_error.3856836027 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1572549539 ps |
| CPU time | 155.67 seconds |
| Started | Aug 27 05:49:45 PM UTC 24 |
| Finished | Aug 27 05:52:24 PM UTC 24 |
| Peak memory | 301300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856836027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3856836027 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1090692397 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 517164786 ps |
| CPU time | 6.08 seconds |
| Started | Aug 27 05:49:56 PM UTC 24 |
| Finished | Aug 27 05:50:04 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090692397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1090692397 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.2412804035 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 118975875 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 05:49:57 PM UTC 24 |
| Finished | Aug 27 05:50:01 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412804035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2412804035 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.3605427240 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 42640413765 ps |
| CPU time | 1521.02 seconds |
| Started | Aug 27 05:49:07 PM UTC 24 |
| Finished | Aug 27 06:14:45 PM UTC 24 |
| Peak memory | 1011972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605427240 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.3605427240 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.1867614014 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 794586120 ps |
| CPU time | 26.58 seconds |
| Started | Aug 27 05:49:13 PM UTC 24 |
| Finished | Aug 27 05:49:41 PM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867614014 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1867614014 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.244443352 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1805536225 ps |
| CPU time | 37.57 seconds |
| Started | Aug 27 05:49:05 PM UTC 24 |
| Finished | Aug 27 05:49:44 PM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244443352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.244443352 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.2016769021 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 20161844536 ps |
| CPU time | 767.53 seconds |
| Started | Aug 27 05:50:02 PM UTC 24 |
| Finished | Aug 27 06:02:58 PM UTC 24 |
| Peak memory | 768292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016769021 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2016769021 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/37.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.634689258 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 24750049 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 05:51:23 PM UTC 24 |
| Finished | Aug 27 05:51:25 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634689258 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.634689258 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_app.3795459116 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 8393106617 ps |
| CPU time | 202.12 seconds |
| Started | Aug 27 05:50:48 PM UTC 24 |
| Finished | Aug 27 05:54:13 PM UTC 24 |
| Peak memory | 307524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795459116 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3795459116 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2578552829 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3045869321 ps |
| CPU time | 73.09 seconds |
| Started | Aug 27 05:50:33 PM UTC 24 |
| Finished | Aug 27 05:51:48 PM UTC 24 |
| Peak memory | 244156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578552829 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2578552829 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.4274269261 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 51207650357 ps |
| CPU time | 243.62 seconds |
| Started | Aug 27 05:50:52 PM UTC 24 |
| Finished | Aug 27 05:54:59 PM UTC 24 |
| Peak memory | 366900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274269261 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.4274269261 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_error.279562697 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2912715118 ps |
| CPU time | 44.17 seconds |
| Started | Aug 27 05:51:00 PM UTC 24 |
| Finished | Aug 27 05:51:46 PM UTC 24 |
| Peak memory | 252224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279562697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.279562697 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.2534624221 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1258236400 ps |
| CPU time | 14.72 seconds |
| Started | Aug 27 05:51:06 PM UTC 24 |
| Finished | Aug 27 05:51:22 PM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534624221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2534624221 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.1998382591 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 53903419 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 05:51:11 PM UTC 24 |
| Finished | Aug 27 05:51:15 PM UTC 24 |
| Peak memory | 233916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998382591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.1998382591 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1208080685 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 53132344451 ps |
| CPU time | 1309.03 seconds |
| Started | Aug 27 05:50:15 PM UTC 24 |
| Finished | Aug 27 06:12:19 PM UTC 24 |
| Peak memory | 962804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208080685 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1208080685 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.154375053 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 21174821911 ps |
| CPU time | 498.57 seconds |
| Started | Aug 27 05:50:19 PM UTC 24 |
| Finished | Aug 27 05:58:44 PM UTC 24 |
| Peak memory | 372988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154375053 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.154375053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.1265741730 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 487635148 ps |
| CPU time | 5.54 seconds |
| Started | Aug 27 05:50:08 PM UTC 24 |
| Finished | Aug 27 05:50:14 PM UTC 24 |
| Peak memory | 231924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265741730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1265741730 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.352941821 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 94783870 ps |
| CPU time | 5.5 seconds |
| Started | Aug 27 05:51:16 PM UTC 24 |
| Finished | Aug 27 05:51:22 PM UTC 24 |
| Peak memory | 233960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352941821 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.352941821 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/38.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.2975662172 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 71397607 ps |
| CPU time | 1.35 seconds |
| Started | Aug 27 05:52:10 PM UTC 24 |
| Finished | Aug 27 05:52:13 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975662172 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2975662172 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_app.2394951923 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6402882323 ps |
| CPU time | 201.47 seconds |
| Started | Aug 27 05:51:38 PM UTC 24 |
| Finished | Aug 27 05:55:03 PM UTC 24 |
| Peak memory | 282876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394951923 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2394951923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.1094394320 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 22796550615 ps |
| CPU time | 900.97 seconds |
| Started | Aug 27 05:51:36 PM UTC 24 |
| Finished | Aug 27 06:06:48 PM UTC 24 |
| Peak memory | 262360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094394320 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1094394320 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.2829571292 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2109794220 ps |
| CPU time | 39.37 seconds |
| Started | Aug 27 05:51:41 PM UTC 24 |
| Finished | Aug 27 05:52:21 PM UTC 24 |
| Peak memory | 260288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829571292 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2829571292 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_error.1219311822 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 57742251516 ps |
| CPU time | 403.34 seconds |
| Started | Aug 27 05:51:47 PM UTC 24 |
| Finished | Aug 27 05:58:35 PM UTC 24 |
| Peak memory | 588084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219311822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1219311822 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.3052742161 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2201723517 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 05:51:49 PM UTC 24 |
| Finished | Aug 27 05:51:52 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052742161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3052742161 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.2874813444 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1032379090 ps |
| CPU time | 33.52 seconds |
| Started | Aug 27 05:51:53 PM UTC 24 |
| Finished | Aug 27 05:52:28 PM UTC 24 |
| Peak memory | 250116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874813444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2874813444 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3062370552 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 38859840252 ps |
| CPU time | 2303.39 seconds |
| Started | Aug 27 05:51:26 PM UTC 24 |
| Finished | Aug 27 06:30:15 PM UTC 24 |
| Peak memory | 1354032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062370552 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3062370552 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.782329771 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2608641008 ps |
| CPU time | 252.04 seconds |
| Started | Aug 27 05:51:32 PM UTC 24 |
| Finished | Aug 27 05:55:48 PM UTC 24 |
| Peak memory | 297272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782329771 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.782329771 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.326744143 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1399087034 ps |
| CPU time | 7.52 seconds |
| Started | Aug 27 05:51:23 PM UTC 24 |
| Finished | Aug 27 05:51:32 PM UTC 24 |
| Peak memory | 235484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326744143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.326744143 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.497440708 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 41338062366 ps |
| CPU time | 470.34 seconds |
| Started | Aug 27 05:52:06 PM UTC 24 |
| Finished | Aug 27 06:00:02 PM UTC 24 |
| Peak memory | 774468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497440708 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.497440708 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/39.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.924350004 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 22162701 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 05:06:43 PM UTC 24 |
| Finished | Aug 27 05:06:45 PM UTC 24 |
| Peak memory | 226048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924350004 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.924350004 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_app.1297513010 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4828375213 ps |
| CPU time | 315.42 seconds |
| Started | Aug 27 05:05:45 PM UTC 24 |
| Finished | Aug 27 05:11:05 PM UTC 24 |
| Peak memory | 307592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297513010 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1297513010 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.632110185 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 34034612271 ps |
| CPU time | 1409.34 seconds |
| Started | Aug 27 05:04:43 PM UTC 24 |
| Finished | Aug 27 05:28:29 PM UTC 24 |
| Peak memory | 270644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632110185 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.632110185 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3202854876 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 533136359 ps |
| CPU time | 19.33 seconds |
| Started | Aug 27 05:06:21 PM UTC 24 |
| Finished | Aug 27 05:06:42 PM UTC 24 |
| Peak memory | 231696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202854876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3202854876 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.3755463581 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 72902196 ps |
| CPU time | 1.5 seconds |
| Started | Aug 27 05:06:35 PM UTC 24 |
| Finished | Aug 27 05:06:38 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755463581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3755463581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.61809270 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2381927703 ps |
| CPU time | 16.71 seconds |
| Started | Aug 27 05:06:39 PM UTC 24 |
| Finished | Aug 27 05:06:57 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61809270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_mask ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.61809270 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.4266832683 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6549783435 ps |
| CPU time | 73.59 seconds |
| Started | Aug 27 05:05:49 PM UTC 24 |
| Finished | Aug 27 05:07:05 PM UTC 24 |
| Peak memory | 278812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266832683 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.4266832683 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_error.2628008599 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 41567935717 ps |
| CPU time | 271.7 seconds |
| Started | Aug 27 05:06:02 PM UTC 24 |
| Finished | Aug 27 05:10:37 PM UTC 24 |
| Peak memory | 452864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628008599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2628008599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.3909396590 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1495012994 ps |
| CPU time | 18.37 seconds |
| Started | Aug 27 05:06:17 PM UTC 24 |
| Finished | Aug 27 05:06:37 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909396590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3909396590 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.2694323388 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 281380321 ps |
| CPU time | 2.15 seconds |
| Started | Aug 27 05:06:39 PM UTC 24 |
| Finished | Aug 27 05:06:42 PM UTC 24 |
| Peak memory | 233808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694323388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2694323388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2227169906 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 134396472136 ps |
| CPU time | 2227.76 seconds |
| Started | Aug 27 05:04:38 PM UTC 24 |
| Finished | Aug 27 05:42:10 PM UTC 24 |
| Peak memory | 2883880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227169906 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2227169906 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.1155927606 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8526494108 ps |
| CPU time | 218.64 seconds |
| Started | Aug 27 05:05:59 PM UTC 24 |
| Finished | Aug 27 05:09:41 PM UTC 24 |
| Peak memory | 301864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155927606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1155927606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.69797175 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4861516960 ps |
| CPU time | 150.72 seconds |
| Started | Aug 27 05:04:40 PM UTC 24 |
| Finished | Aug 27 05:07:14 PM UTC 24 |
| Peak memory | 352636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69797175 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.69797175 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.3462440689 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 933788436 ps |
| CPU time | 25.13 seconds |
| Started | Aug 27 05:04:36 PM UTC 24 |
| Finished | Aug 27 05:05:03 PM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462440689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3462440689 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.973737121 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 790423739099 ps |
| CPU time | 2346.81 seconds |
| Started | Aug 27 05:06:41 PM UTC 24 |
| Finished | Aug 27 05:46:16 PM UTC 24 |
| Peak memory | 2013440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973737121 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.973737121 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.515148813 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 36777634 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 05:05:40 PM UTC 24 |
| Finished | Aug 27 05:05:44 PM UTC 24 |
| Peak memory | 235752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515148813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.515148813 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1899176625 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 279259341 ps |
| CPU time | 3.8 seconds |
| Started | Aug 27 05:05:43 PM UTC 24 |
| Finished | Aug 27 05:05:47 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899176625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1899176625 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.4193121813 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 60563343581 ps |
| CPU time | 2526.51 seconds |
| Started | Aug 27 05:04:45 PM UTC 24 |
| Finished | Aug 27 05:47:19 PM UTC 24 |
| Peak memory | 3074208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193121813 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4193121813 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1216591466 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 61408149967 ps |
| CPU time | 2959.88 seconds |
| Started | Aug 27 05:05:04 PM UTC 24 |
| Finished | Aug 27 05:54:58 PM UTC 24 |
| Peak memory | 3053728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216591466 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1216591466 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2709727621 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 55268116720 ps |
| CPU time | 1581.53 seconds |
| Started | Aug 27 05:05:06 PM UTC 24 |
| Finished | Aug 27 05:31:46 PM UTC 24 |
| Peak memory | 886936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709727621 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2709727621 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.2581807615 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 166824890265 ps |
| CPU time | 1555.46 seconds |
| Started | Aug 27 05:05:10 PM UTC 24 |
| Finished | Aug 27 05:31:24 PM UTC 24 |
| Peak memory | 1730720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581807615 -assert nopostp roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2581807615 +enab le_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2068079120 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 19364265437 ps |
| CPU time | 221.62 seconds |
| Started | Aug 27 05:05:11 PM UTC 24 |
| Finished | Aug 27 05:08:56 PM UTC 24 |
| Peak memory | 440688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068079120 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2068079120 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.3849679056 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 74167592757 ps |
| CPU time | 1818.59 seconds |
| Started | Aug 27 05:05:26 PM UTC 24 |
| Finished | Aug 27 05:36:06 PM UTC 24 |
| Peak memory | 1136796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849679056 -assert nopost proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3849679056 +e nable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.3807812202 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 14976643 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 05:53:12 PM UTC 24 |
| Finished | Aug 27 05:53:15 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807812202 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3807812202 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_app.319301279 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 29355058069 ps |
| CPU time | 323.72 seconds |
| Started | Aug 27 05:52:24 PM UTC 24 |
| Finished | Aug 27 05:57:52 PM UTC 24 |
| Peak memory | 493872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319301279 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.319301279 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.3971561810 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 8997582590 ps |
| CPU time | 857.71 seconds |
| Started | Aug 27 05:52:23 PM UTC 24 |
| Finished | Aug 27 06:06:52 PM UTC 24 |
| Peak memory | 252276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971561810 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.3971561810 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.2408871128 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 54034709948 ps |
| CPU time | 194.72 seconds |
| Started | Aug 27 05:52:29 PM UTC 24 |
| Finished | Aug 27 05:55:47 PM UTC 24 |
| Peak memory | 350584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408871128 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.2408871128 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_error.1705309512 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 261042603 ps |
| CPU time | 11.67 seconds |
| Started | Aug 27 05:52:57 PM UTC 24 |
| Finished | Aug 27 05:53:10 PM UTC 24 |
| Peak memory | 249084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705309512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1705309512 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.3296484802 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3500058494 ps |
| CPU time | 11.5 seconds |
| Started | Aug 27 05:53:03 PM UTC 24 |
| Finished | Aug 27 05:53:15 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296484802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.3296484802 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.117035961 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 48625351 ps |
| CPU time | 2.15 seconds |
| Started | Aug 27 05:53:08 PM UTC 24 |
| Finished | Aug 27 05:53:11 PM UTC 24 |
| Peak memory | 233932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117035961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.117035961 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2613654730 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 35343322318 ps |
| CPU time | 2298.81 seconds |
| Started | Aug 27 05:52:20 PM UTC 24 |
| Finished | Aug 27 06:31:06 PM UTC 24 |
| Peak memory | 1245592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613654730 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2613654730 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.1307684553 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 701711459 ps |
| CPU time | 46.17 seconds |
| Started | Aug 27 05:52:23 PM UTC 24 |
| Finished | Aug 27 05:53:11 PM UTC 24 |
| Peak memory | 245988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307684553 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1307684553 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.139287053 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 45254435377 ps |
| CPU time | 136.58 seconds |
| Started | Aug 27 05:52:13 PM UTC 24 |
| Finished | Aug 27 05:54:33 PM UTC 24 |
| Peak memory | 237884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139287053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.139287053 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.282909332 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 249129415705 ps |
| CPU time | 2383.67 seconds |
| Started | Aug 27 05:53:11 PM UTC 24 |
| Finished | Aug 27 06:33:21 PM UTC 24 |
| Peak memory | 1454740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282909332 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.282909332 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/40.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.758116249 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 33500457 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 05:55:04 PM UTC 24 |
| Finished | Aug 27 05:55:06 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758116249 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.758116249 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_app.1184929290 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 46086095813 ps |
| CPU time | 341.04 seconds |
| Started | Aug 27 05:54:14 PM UTC 24 |
| Finished | Aug 27 06:00:00 PM UTC 24 |
| Peak memory | 411892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184929290 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1184929290 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.3157375155 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 47847739860 ps |
| CPU time | 1108.43 seconds |
| Started | Aug 27 05:53:27 PM UTC 24 |
| Finished | Aug 27 06:12:08 PM UTC 24 |
| Peak memory | 266548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157375155 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3157375155 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.3539409898 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 13454142867 ps |
| CPU time | 25.09 seconds |
| Started | Aug 27 05:54:33 PM UTC 24 |
| Finished | Aug 27 05:55:00 PM UTC 24 |
| Peak memory | 252208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539409898 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3539409898 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_error.2452762359 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1258631065 ps |
| CPU time | 61.75 seconds |
| Started | Aug 27 05:54:39 PM UTC 24 |
| Finished | Aug 27 05:55:43 PM UTC 24 |
| Peak memory | 262332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452762359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2452762359 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.3836823370 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 6210239915 ps |
| CPU time | 19.28 seconds |
| Started | Aug 27 05:54:59 PM UTC 24 |
| Finished | Aug 27 05:55:20 PM UTC 24 |
| Peak memory | 227656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836823370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3836823370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.3285511754 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 101701914 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 05:55:01 PM UTC 24 |
| Finished | Aug 27 05:55:04 PM UTC 24 |
| Peak memory | 229324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285511754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3285511754 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.4259144926 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 50770660189 ps |
| CPU time | 2288.99 seconds |
| Started | Aug 27 05:53:15 PM UTC 24 |
| Finished | Aug 27 06:31:50 PM UTC 24 |
| Peak memory | 2537796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259144926 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.4259144926 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.699839719 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 65193754338 ps |
| CPU time | 542.73 seconds |
| Started | Aug 27 05:53:16 PM UTC 24 |
| Finished | Aug 27 06:02:26 PM UTC 24 |
| Peak memory | 655672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699839719 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.699839719 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2410047311 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 10204813095 ps |
| CPU time | 84.2 seconds |
| Started | Aug 27 05:53:12 PM UTC 24 |
| Finished | Aug 27 05:54:39 PM UTC 24 |
| Peak memory | 235772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410047311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2410047311 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.1043632117 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 33040032462 ps |
| CPU time | 627.25 seconds |
| Started | Aug 27 05:55:01 PM UTC 24 |
| Finished | Aug 27 06:05:36 PM UTC 24 |
| Peak memory | 334472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043632117 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1043632117 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/41.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.3610043091 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 42410836 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:56:11 PM UTC 24 |
| Finished | Aug 27 05:56:13 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610043091 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.3610043091 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_app.1674904991 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 7124438441 ps |
| CPU time | 184.37 seconds |
| Started | Aug 27 05:55:27 PM UTC 24 |
| Finished | Aug 27 05:58:34 PM UTC 24 |
| Peak memory | 336152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674904991 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1674904991 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.872821530 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 32092464874 ps |
| CPU time | 442.81 seconds |
| Started | Aug 27 05:55:21 PM UTC 24 |
| Finished | Aug 27 06:02:50 PM UTC 24 |
| Peak memory | 252152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872821530 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.872821530 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.520989110 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3348095472 ps |
| CPU time | 34.93 seconds |
| Started | Aug 27 05:55:44 PM UTC 24 |
| Finished | Aug 27 05:56:20 PM UTC 24 |
| Peak memory | 252212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520989110 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.520989110 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_error.2508150658 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4478872342 ps |
| CPU time | 159.97 seconds |
| Started | Aug 27 05:55:48 PM UTC 24 |
| Finished | Aug 27 05:58:31 PM UTC 24 |
| Peak memory | 295212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508150658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2508150658 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.1520105865 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3054195162 ps |
| CPU time | 19.12 seconds |
| Started | Aug 27 05:55:49 PM UTC 24 |
| Finished | Aug 27 05:56:10 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520105865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1520105865 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.530972277 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 43948459 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 05:56:06 PM UTC 24 |
| Finished | Aug 27 05:56:10 PM UTC 24 |
| Peak memory | 231820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530972277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.530972277 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.243820443 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 150733770184 ps |
| CPU time | 1767.48 seconds |
| Started | Aug 27 05:55:07 PM UTC 24 |
| Finished | Aug 27 06:24:53 PM UTC 24 |
| Peak memory | 2251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243820443 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.243820443 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.898865389 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 6389184224 ps |
| CPU time | 151.86 seconds |
| Started | Aug 27 05:55:09 PM UTC 24 |
| Finished | Aug 27 05:57:44 PM UTC 24 |
| Peak memory | 274736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898865389 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.898865389 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.1622922539 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 7753405302 ps |
| CPU time | 84.05 seconds |
| Started | Aug 27 05:55:04 PM UTC 24 |
| Finished | Aug 27 05:56:30 PM UTC 24 |
| Peak memory | 235876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622922539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1622922539 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.1550726328 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 46256252251 ps |
| CPU time | 1531.32 seconds |
| Started | Aug 27 05:56:11 PM UTC 24 |
| Finished | Aug 27 06:22:00 PM UTC 24 |
| Peak memory | 711344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550726328 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1550726328 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/42.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.244053930 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 14175502 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:58:02 PM UTC 24 |
| Finished | Aug 27 05:58:04 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244053930 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.244053930 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_app.4068852700 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2623684296 ps |
| CPU time | 146.36 seconds |
| Started | Aug 27 05:57:09 PM UTC 24 |
| Finished | Aug 27 05:59:38 PM UTC 24 |
| Peak memory | 281032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068852700 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.4068852700 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.930367419 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 26469980510 ps |
| CPU time | 1321.83 seconds |
| Started | Aug 27 05:56:31 PM UTC 24 |
| Finished | Aug 27 06:18:49 PM UTC 24 |
| Peak memory | 256244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930367419 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.930367419 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2079732539 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6177857767 ps |
| CPU time | 432.42 seconds |
| Started | Aug 27 05:57:28 PM UTC 24 |
| Finished | Aug 27 06:04:47 PM UTC 24 |
| Peak memory | 358844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079732539 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2079732539 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_error.980302474 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 6607494378 ps |
| CPU time | 201.3 seconds |
| Started | Aug 27 05:57:41 PM UTC 24 |
| Finished | Aug 27 06:01:06 PM UTC 24 |
| Peak memory | 405820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980302474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.980302474 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.2615527909 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 6787120832 ps |
| CPU time | 14.11 seconds |
| Started | Aug 27 05:57:45 PM UTC 24 |
| Finished | Aug 27 05:58:01 PM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615527909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2615527909 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.2911170297 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 91669240 ps |
| CPU time | 2.34 seconds |
| Started | Aug 27 05:57:53 PM UTC 24 |
| Finished | Aug 27 05:57:57 PM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911170297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2911170297 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.4124543936 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 419740662078 ps |
| CPU time | 4638.92 seconds |
| Started | Aug 27 05:56:21 PM UTC 24 |
| Finished | Aug 27 07:14:30 PM UTC 24 |
| Peak memory | 4454752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124543936 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.4124543936 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.3476218323 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 24281411634 ps |
| CPU time | 384.19 seconds |
| Started | Aug 27 05:56:28 PM UTC 24 |
| Finished | Aug 27 06:02:58 PM UTC 24 |
| Peak memory | 479480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476218323 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3476218323 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.1128026664 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 362791956 ps |
| CPU time | 12.5 seconds |
| Started | Aug 27 05:56:14 PM UTC 24 |
| Finished | Aug 27 05:56:27 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128026664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1128026664 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.1100116195 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 13452116756 ps |
| CPU time | 509.1 seconds |
| Started | Aug 27 05:57:58 PM UTC 24 |
| Finished | Aug 27 06:06:33 PM UTC 24 |
| Peak memory | 412292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100116195 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.1100116195 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/43.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3549273638 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 58769200 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 05:58:48 PM UTC 24 |
| Finished | Aug 27 05:58:50 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549273638 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3549273638 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.17128812 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 13692276011 ps |
| CPU time | 699.32 seconds |
| Started | Aug 27 05:58:18 PM UTC 24 |
| Finished | Aug 27 06:10:06 PM UTC 24 |
| Peak memory | 254256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17128812 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.17128812 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.2740977806 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 19445530565 ps |
| CPU time | 508.96 seconds |
| Started | Aug 27 05:58:32 PM UTC 24 |
| Finished | Aug 27 06:07:08 PM UTC 24 |
| Peak memory | 512280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740977806 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2740977806 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_error.1020278711 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 45939009675 ps |
| CPU time | 413.52 seconds |
| Started | Aug 27 05:58:35 PM UTC 24 |
| Finished | Aug 27 06:05:34 PM UTC 24 |
| Peak memory | 538880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020278711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1020278711 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.2588785455 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 648040383 ps |
| CPU time | 5.32 seconds |
| Started | Aug 27 05:58:36 PM UTC 24 |
| Finished | Aug 27 05:58:42 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588785455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2588785455 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.3851647606 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 56075361 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 05:58:43 PM UTC 24 |
| Finished | Aug 27 05:58:47 PM UTC 24 |
| Peak memory | 233808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851647606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3851647606 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.44230921 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 30008170812 ps |
| CPU time | 1214.54 seconds |
| Started | Aug 27 05:58:10 PM UTC 24 |
| Finished | Aug 27 06:18:40 PM UTC 24 |
| Peak memory | 1587448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44230921 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.44230921 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.3549098105 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 33624173586 ps |
| CPU time | 416.78 seconds |
| Started | Aug 27 05:58:17 PM UTC 24 |
| Finished | Aug 27 06:05:20 PM UTC 24 |
| Peak memory | 497976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549098105 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3549098105 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.557677949 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1101746508 ps |
| CPU time | 9.93 seconds |
| Started | Aug 27 05:58:05 PM UTC 24 |
| Finished | Aug 27 05:58:16 PM UTC 24 |
| Peak memory | 235712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557677949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.557677949 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.1613286051 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 27396966946 ps |
| CPU time | 850.29 seconds |
| Started | Aug 27 05:58:45 PM UTC 24 |
| Finished | Aug 27 06:13:06 PM UTC 24 |
| Peak memory | 367280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613286051 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1613286051 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.1563497825 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 28013081 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 06:01:22 PM UTC 24 |
| Finished | Aug 27 06:01:24 PM UTC 24 |
| Peak memory | 226292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563497825 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1563497825 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_app.1061920237 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1346556463 ps |
| CPU time | 34.42 seconds |
| Started | Aug 27 06:00:02 PM UTC 24 |
| Finished | Aug 27 06:00:40 PM UTC 24 |
| Peak memory | 237752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061920237 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1061920237 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.4106825170 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 5623475893 ps |
| CPU time | 610.63 seconds |
| Started | Aug 27 06:00:00 PM UTC 24 |
| Finished | Aug 27 06:10:22 PM UTC 24 |
| Peak memory | 244008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106825170 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.4106825170 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.306859168 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 17220588847 ps |
| CPU time | 291.73 seconds |
| Started | Aug 27 06:00:06 PM UTC 24 |
| Finished | Aug 27 06:05:01 PM UTC 24 |
| Peak memory | 473400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306859168 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.306859168 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_error.1588179366 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 18399993429 ps |
| CPU time | 427.9 seconds |
| Started | Aug 27 06:00:41 PM UTC 24 |
| Finished | Aug 27 06:07:55 PM UTC 24 |
| Peak memory | 356660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588179366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1588179366 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.1309619603 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1164786158 ps |
| CPU time | 13.71 seconds |
| Started | Aug 27 06:01:06 PM UTC 24 |
| Finished | Aug 27 06:01:21 PM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309619603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1309619603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.1587670044 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 165809126 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 06:01:11 PM UTC 24 |
| Finished | Aug 27 06:01:14 PM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587670044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1587670044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3192877846 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 6587690368 ps |
| CPU time | 597.84 seconds |
| Started | Aug 27 05:59:39 PM UTC 24 |
| Finished | Aug 27 06:09:44 PM UTC 24 |
| Peak memory | 583996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192877846 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3192877846 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.1118774044 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 9672512107 ps |
| CPU time | 276.67 seconds |
| Started | Aug 27 05:59:43 PM UTC 24 |
| Finished | Aug 27 06:04:24 PM UTC 24 |
| Peak memory | 416036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118774044 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1118774044 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2553725663 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7113139360 ps |
| CPU time | 68.1 seconds |
| Started | Aug 27 05:58:51 PM UTC 24 |
| Finished | Aug 27 06:00:00 PM UTC 24 |
| Peak memory | 235836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553725663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2553725663 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.1541239006 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 7174317239 ps |
| CPU time | 219.95 seconds |
| Started | Aug 27 06:01:16 PM UTC 24 |
| Finished | Aug 27 06:04:59 PM UTC 24 |
| Peak memory | 346368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541239006 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1541239006 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/45.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.3939433473 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 59506594 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 06:03:49 PM UTC 24 |
| Finished | Aug 27 06:03:51 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939433473 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3939433473 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_app.584946878 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 58246099051 ps |
| CPU time | 297.89 seconds |
| Started | Aug 27 06:02:51 PM UTC 24 |
| Finished | Aug 27 06:07:53 PM UTC 24 |
| Peak memory | 346356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584946878 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.584946878 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.3598427952 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 28341913055 ps |
| CPU time | 816.78 seconds |
| Started | Aug 27 06:02:42 PM UTC 24 |
| Finished | Aug 27 06:16:29 PM UTC 24 |
| Peak memory | 248112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598427952 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3598427952 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.623955065 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 68584234283 ps |
| CPU time | 260.74 seconds |
| Started | Aug 27 06:02:59 PM UTC 24 |
| Finished | Aug 27 06:07:24 PM UTC 24 |
| Peak memory | 354552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623955065 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.623955065 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_error.2390111300 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 5283516124 ps |
| CPU time | 103.15 seconds |
| Started | Aug 27 06:02:59 PM UTC 24 |
| Finished | Aug 27 06:04:44 PM UTC 24 |
| Peak memory | 278776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390111300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2390111300 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.1841248082 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1841106683 ps |
| CPU time | 8.91 seconds |
| Started | Aug 27 06:03:38 PM UTC 24 |
| Finished | Aug 27 06:03:48 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841248082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1841248082 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.3079234433 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2375633598 ps |
| CPU time | 18.59 seconds |
| Started | Aug 27 06:03:43 PM UTC 24 |
| Finished | Aug 27 06:04:02 PM UTC 24 |
| Peak memory | 246092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079234433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3079234433 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2788964439 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 17825552186 ps |
| CPU time | 208.22 seconds |
| Started | Aug 27 06:02:22 PM UTC 24 |
| Finished | Aug 27 06:05:54 PM UTC 24 |
| Peak memory | 420180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788964439 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2788964439 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.321228919 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 9314631071 ps |
| CPU time | 147.87 seconds |
| Started | Aug 27 06:02:27 PM UTC 24 |
| Finished | Aug 27 06:04:58 PM UTC 24 |
| Peak memory | 274744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321228919 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.321228919 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2597821845 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 12523890425 ps |
| CPU time | 53.32 seconds |
| Started | Aug 27 06:01:26 PM UTC 24 |
| Finished | Aug 27 06:02:21 PM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597821845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2597821845 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.3207509856 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 30318535334 ps |
| CPU time | 397.54 seconds |
| Started | Aug 27 06:03:45 PM UTC 24 |
| Finished | Aug 27 06:10:28 PM UTC 24 |
| Peak memory | 465648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207509856 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3207509856 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/46.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.2029843644 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 32984439 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 06:05:19 PM UTC 24 |
| Finished | Aug 27 06:05:21 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029843644 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.2029843644 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_app.945130378 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 28855849938 ps |
| CPU time | 427.01 seconds |
| Started | Aug 27 06:04:48 PM UTC 24 |
| Finished | Aug 27 06:12:00 PM UTC 24 |
| Peak memory | 350528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945130378 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.945130378 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.2901960620 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 129740025128 ps |
| CPU time | 1148.76 seconds |
| Started | Aug 27 06:04:46 PM UTC 24 |
| Finished | Aug 27 06:24:08 PM UTC 24 |
| Peak memory | 264496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901960620 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2901960620 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1809138280 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5852526790 ps |
| CPU time | 152.22 seconds |
| Started | Aug 27 06:04:59 PM UTC 24 |
| Finished | Aug 27 06:07:34 PM UTC 24 |
| Peak memory | 289100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809138280 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1809138280 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_error.200798888 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 14798919477 ps |
| CPU time | 406.63 seconds |
| Started | Aug 27 06:05:00 PM UTC 24 |
| Finished | Aug 27 06:11:52 PM UTC 24 |
| Peak memory | 342268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200798888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.200798888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2943199463 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1443655372 ps |
| CPU time | 14.59 seconds |
| Started | Aug 27 06:05:02 PM UTC 24 |
| Finished | Aug 27 06:05:18 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943199463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2943199463 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.101597287 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 83306022 ps |
| CPU time | 1.94 seconds |
| Started | Aug 27 06:05:05 PM UTC 24 |
| Finished | Aug 27 06:05:08 PM UTC 24 |
| Peak memory | 233352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101597287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.101597287 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.941025472 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 55098862222 ps |
| CPU time | 1925.23 seconds |
| Started | Aug 27 06:04:03 PM UTC 24 |
| Finished | Aug 27 06:36:31 PM UTC 24 |
| Peak memory | 1192232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941025472 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.941025472 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.3816045370 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 51585984409 ps |
| CPU time | 419.05 seconds |
| Started | Aug 27 06:04:25 PM UTC 24 |
| Finished | Aug 27 06:11:30 PM UTC 24 |
| Peak memory | 487800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816045370 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3816045370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.2956560405 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 10580915887 ps |
| CPU time | 71.1 seconds |
| Started | Aug 27 06:03:52 PM UTC 24 |
| Finished | Aug 27 06:05:05 PM UTC 24 |
| Peak memory | 235872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956560405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2956560405 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.1827773095 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 38109433374 ps |
| CPU time | 1299.62 seconds |
| Started | Aug 27 06:05:10 PM UTC 24 |
| Finished | Aug 27 06:27:04 PM UTC 24 |
| Peak memory | 797452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827773095 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1827773095 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/47.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.4013181031 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 12657067 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 06:06:15 PM UTC 24 |
| Finished | Aug 27 06:06:18 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013181031 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.4013181031 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_app.2140048141 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2433496712 ps |
| CPU time | 56.9 seconds |
| Started | Aug 27 06:05:43 PM UTC 24 |
| Finished | Aug 27 06:06:42 PM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140048141 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2140048141 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.2805880581 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 11247967882 ps |
| CPU time | 981.65 seconds |
| Started | Aug 27 06:05:37 PM UTC 24 |
| Finished | Aug 27 06:22:10 PM UTC 24 |
| Peak memory | 252204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805880581 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2805880581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.4049679359 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 40092354871 ps |
| CPU time | 311.8 seconds |
| Started | Aug 27 06:05:54 PM UTC 24 |
| Finished | Aug 27 06:11:10 PM UTC 24 |
| Peak memory | 323840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049679359 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.4049679359 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1625092075 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 7737296863 ps |
| CPU time | 297.84 seconds |
| Started | Aug 27 06:05:55 PM UTC 24 |
| Finished | Aug 27 06:10:57 PM UTC 24 |
| Peak memory | 350460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625092075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1625092075 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.1297964690 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2463450402 ps |
| CPU time | 16.43 seconds |
| Started | Aug 27 06:05:57 PM UTC 24 |
| Finished | Aug 27 06:06:15 PM UTC 24 |
| Peak memory | 227664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297964690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1297964690 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.3507493850 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 43757545 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 06:05:58 PM UTC 24 |
| Finished | Aug 27 06:06:01 PM UTC 24 |
| Peak memory | 233344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507493850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3507493850 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1326415480 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 18929273307 ps |
| CPU time | 1990.22 seconds |
| Started | Aug 27 06:05:22 PM UTC 24 |
| Finished | Aug 27 06:38:54 PM UTC 24 |
| Peak memory | 1341772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326415480 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1326415480 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.490944727 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3627987512 ps |
| CPU time | 242.3 seconds |
| Started | Aug 27 06:05:35 PM UTC 24 |
| Finished | Aug 27 06:09:41 PM UTC 24 |
| Peak memory | 305456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490944727 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.490944727 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.4027519348 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2536763753 ps |
| CPU time | 30.66 seconds |
| Started | Aug 27 06:05:21 PM UTC 24 |
| Finished | Aug 27 06:05:53 PM UTC 24 |
| Peak memory | 235960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027519348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4027519348 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.1613521486 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 19861389401 ps |
| CPU time | 664.31 seconds |
| Started | Aug 27 06:06:02 PM UTC 24 |
| Finished | Aug 27 06:17:15 PM UTC 24 |
| Peak memory | 422148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613521486 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1613521486 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/48.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3471002833 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 107247991 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 06:07:25 PM UTC 24 |
| Finished | Aug 27 06:07:28 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471002833 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3471002833 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_app.190677928 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 10274107186 ps |
| CPU time | 367.74 seconds |
| Started | Aug 27 06:06:48 PM UTC 24 |
| Finished | Aug 27 06:13:01 PM UTC 24 |
| Peak memory | 346464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190677928 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.190677928 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.1254896982 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 33177815528 ps |
| CPU time | 325.19 seconds |
| Started | Aug 27 06:06:43 PM UTC 24 |
| Finished | Aug 27 06:12:13 PM UTC 24 |
| Peak memory | 243952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254896982 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1254896982 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3678416923 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 6677336710 ps |
| CPU time | 68.1 seconds |
| Started | Aug 27 06:06:52 PM UTC 24 |
| Finished | Aug 27 06:08:02 PM UTC 24 |
| Peak memory | 250160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678416923 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3678416923 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_error.4203889124 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 22631053683 ps |
| CPU time | 175.6 seconds |
| Started | Aug 27 06:07:09 PM UTC 24 |
| Finished | Aug 27 06:10:08 PM UTC 24 |
| Peak memory | 375096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203889124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.4203889124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.3478274538 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2292326054 ps |
| CPU time | 8.98 seconds |
| Started | Aug 27 06:07:10 PM UTC 24 |
| Finished | Aug 27 06:07:20 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478274538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3478274538 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.2623041124 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 52960880 ps |
| CPU time | 2.19 seconds |
| Started | Aug 27 06:07:21 PM UTC 24 |
| Finished | Aug 27 06:07:24 PM UTC 24 |
| Peak memory | 233808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623041124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2623041124 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1281224107 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 42315043799 ps |
| CPU time | 1412.68 seconds |
| Started | Aug 27 06:06:19 PM UTC 24 |
| Finished | Aug 27 06:30:08 PM UTC 24 |
| Peak memory | 1810748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281224107 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1281224107 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2733581370 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 86726974783 ps |
| CPU time | 563.16 seconds |
| Started | Aug 27 06:06:34 PM UTC 24 |
| Finished | Aug 27 06:16:04 PM UTC 24 |
| Peak memory | 629040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733581370 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2733581370 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.2220450388 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2941112045 ps |
| CPU time | 72.25 seconds |
| Started | Aug 27 06:06:17 PM UTC 24 |
| Finished | Aug 27 06:07:31 PM UTC 24 |
| Peak memory | 233928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220450388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2220450388 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.1909400036 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 266262348188 ps |
| CPU time | 1946.42 seconds |
| Started | Aug 27 06:07:25 PM UTC 24 |
| Finished | Aug 27 06:40:13 PM UTC 24 |
| Peak memory | 1606324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909400036 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1909400036 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/49.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3812267318 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 14726324 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:07:48 PM UTC 24 |
| Finished | Aug 27 05:07:50 PM UTC 24 |
| Peak memory | 226296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812267318 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3812267318 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_app.931160489 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 17316330431 ps |
| CPU time | 306.82 seconds |
| Started | Aug 27 05:06:53 PM UTC 24 |
| Finished | Aug 27 05:12:05 PM UTC 24 |
| Peak memory | 434480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931160489 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.931160489 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.188389505 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 29786771515 ps |
| CPU time | 510.7 seconds |
| Started | Aug 27 05:06:54 PM UTC 24 |
| Finished | Aug 27 05:15:32 PM UTC 24 |
| Peak memory | 540984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188389505 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.188389505 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.1034653234 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 84365441259 ps |
| CPU time | 966.6 seconds |
| Started | Aug 27 05:06:53 PM UTC 24 |
| Finished | Aug 27 05:23:12 PM UTC 24 |
| Peak memory | 260380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034653234 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1034653234 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.4121612055 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 20392090 ps |
| CPU time | 1.4 seconds |
| Started | Aug 27 05:07:21 PM UTC 24 |
| Finished | Aug 27 05:07:23 PM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121612055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.4121612055 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.3805274666 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 44832223 ps |
| CPU time | 1.63 seconds |
| Started | Aug 27 05:07:23 PM UTC 24 |
| Finished | Aug 27 05:07:25 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805274666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.3805274666 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.3315078700 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3896002085 ps |
| CPU time | 32.04 seconds |
| Started | Aug 27 05:07:25 PM UTC 24 |
| Finished | Aug 27 05:07:58 PM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315078700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3315078700 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1445100422 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 7022685763 ps |
| CPU time | 134.42 seconds |
| Started | Aug 27 05:06:58 PM UTC 24 |
| Finished | Aug 27 05:09:15 PM UTC 24 |
| Peak memory | 336164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445100422 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1445100422 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_error.3604482206 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3215647609 ps |
| CPU time | 292.6 seconds |
| Started | Aug 27 05:07:06 PM UTC 24 |
| Finished | Aug 27 05:12:04 PM UTC 24 |
| Peak memory | 317748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604482206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3604482206 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.1568159135 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 185468381 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 05:07:15 PM UTC 24 |
| Finished | Aug 27 05:07:19 PM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568159135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1568159135 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.865525940 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 101904338 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 05:07:27 PM UTC 24 |
| Finished | Aug 27 05:07:30 PM UTC 24 |
| Peak memory | 231304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865525940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.865525940 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.4265909440 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2603289089 ps |
| CPU time | 131.3 seconds |
| Started | Aug 27 05:06:47 PM UTC 24 |
| Finished | Aug 27 05:09:01 PM UTC 24 |
| Peak memory | 344340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265909440 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.4265909440 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.650459070 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3904573017 ps |
| CPU time | 126.93 seconds |
| Started | Aug 27 05:07:04 PM UTC 24 |
| Finished | Aug 27 05:09:14 PM UTC 24 |
| Peak memory | 279228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650459070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.650459070 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.2102065114 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 6818183529 ps |
| CPU time | 458.79 seconds |
| Started | Aug 27 05:06:49 PM UTC 24 |
| Finished | Aug 27 05:14:35 PM UTC 24 |
| Peak memory | 366836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102065114 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2102065114 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.796315673 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 10346516722 ps |
| CPU time | 65.51 seconds |
| Started | Aug 27 05:06:47 PM UTC 24 |
| Finished | Aug 27 05:07:54 PM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796315673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.796315673 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.706132190 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 16600161535 ps |
| CPU time | 698.68 seconds |
| Started | Aug 27 05:07:31 PM UTC 24 |
| Finished | Aug 27 05:19:19 PM UTC 24 |
| Peak memory | 557700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706132190 -assert nopostpro c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.706132190 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/5.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.4051844899 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 25600402 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 05:09:17 PM UTC 24 |
| Finished | Aug 27 05:09:19 PM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051844899 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.4051844899 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_app.2841270146 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5512363108 ps |
| CPU time | 324.05 seconds |
| Started | Aug 27 05:08:03 PM UTC 24 |
| Finished | Aug 27 05:13:31 PM UTC 24 |
| Peak memory | 336092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841270146 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2841270146 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.3073886981 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 50371696115 ps |
| CPU time | 313.38 seconds |
| Started | Aug 27 05:08:38 PM UTC 24 |
| Finished | Aug 27 05:13:56 PM UTC 24 |
| Peak memory | 422168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073886981 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3073886981 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.1198103555 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 32265527258 ps |
| CPU time | 818.61 seconds |
| Started | Aug 27 05:07:59 PM UTC 24 |
| Finished | Aug 27 05:21:49 PM UTC 24 |
| Peak memory | 248056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198103555 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1198103555 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.2534051508 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 741343824 ps |
| CPU time | 24.91 seconds |
| Started | Aug 27 05:08:57 PM UTC 24 |
| Finished | Aug 27 05:09:23 PM UTC 24 |
| Peak memory | 235556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534051508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2534051508 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3479906066 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 43893668 ps |
| CPU time | 1.91 seconds |
| Started | Aug 27 05:09:02 PM UTC 24 |
| Finished | Aug 27 05:09:05 PM UTC 24 |
| Peak memory | 227532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479906066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3479906066 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3043754939 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3999281254 ps |
| CPU time | 32.9 seconds |
| Started | Aug 27 05:09:06 PM UTC 24 |
| Finished | Aug 27 05:09:41 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043754939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3043754939 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3494575252 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 17414567076 ps |
| CPU time | 183.25 seconds |
| Started | Aug 27 05:08:39 PM UTC 24 |
| Finished | Aug 27 05:11:45 PM UTC 24 |
| Peak memory | 383256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494575252 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3494575252 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_error.354294118 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8788698654 ps |
| CPU time | 401.86 seconds |
| Started | Aug 27 05:08:52 PM UTC 24 |
| Finished | Aug 27 05:15:39 PM UTC 24 |
| Peak memory | 362752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354294118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.354294118 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.4174432256 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2527645721 ps |
| CPU time | 17.55 seconds |
| Started | Aug 27 05:08:57 PM UTC 24 |
| Finished | Aug 27 05:09:16 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174432256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4174432256 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2378850449 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2070815672 ps |
| CPU time | 25.73 seconds |
| Started | Aug 27 05:09:08 PM UTC 24 |
| Finished | Aug 27 05:09:35 PM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378850449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2378850449 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1902769283 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 25568804870 ps |
| CPU time | 2990.6 seconds |
| Started | Aug 27 05:07:51 PM UTC 24 |
| Finished | Aug 27 05:58:17 PM UTC 24 |
| Peak memory | 1663344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902769283 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1902769283 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3886168033 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2645894437 ps |
| CPU time | 22.63 seconds |
| Started | Aug 27 05:08:43 PM UTC 24 |
| Finished | Aug 27 05:09:07 PM UTC 24 |
| Peak memory | 236136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886168033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3886168033 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.2773948262 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 33957527160 ps |
| CPU time | 567.85 seconds |
| Started | Aug 27 05:07:55 PM UTC 24 |
| Finished | Aug 27 05:17:31 PM UTC 24 |
| Peak memory | 649436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773948262 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2773948262 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.3078108471 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 6456459625 ps |
| CPU time | 59.5 seconds |
| Started | Aug 27 05:07:50 PM UTC 24 |
| Finished | Aug 27 05:08:51 PM UTC 24 |
| Peak memory | 234608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078108471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3078108471 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.1370310581 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 83129175653 ps |
| CPU time | 1615.51 seconds |
| Started | Aug 27 05:09:15 PM UTC 24 |
| Finished | Aug 27 05:36:29 PM UTC 24 |
| Peak memory | 344780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370310581 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1370310581 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/6.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.2935713603 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 58004885 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 05:11:27 PM UTC 24 |
| Finished | Aug 27 05:11:29 PM UTC 24 |
| Peak memory | 226056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935713603 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2935713603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_app.2671797661 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8185710683 ps |
| CPU time | 188.89 seconds |
| Started | Aug 27 05:09:37 PM UTC 24 |
| Finished | Aug 27 05:12:49 PM UTC 24 |
| Peak memory | 389416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671797661 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2671797661 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.521381659 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8538222985 ps |
| CPU time | 189.07 seconds |
| Started | Aug 27 05:09:42 PM UTC 24 |
| Finished | Aug 27 05:12:54 PM UTC 24 |
| Peak memory | 350424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521381659 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.521381659 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.1484431248 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 9462438196 ps |
| CPU time | 595.2 seconds |
| Started | Aug 27 05:09:36 PM UTC 24 |
| Finished | Aug 27 05:19:40 PM UTC 24 |
| Peak memory | 250116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484431248 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1484431248 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2259536645 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 636245417 ps |
| CPU time | 23.12 seconds |
| Started | Aug 27 05:11:02 PM UTC 24 |
| Finished | Aug 27 05:11:26 PM UTC 24 |
| Peak memory | 245112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259536645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2259536645 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.349624455 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 30722297 ps |
| CPU time | 1.7 seconds |
| Started | Aug 27 05:11:03 PM UTC 24 |
| Finished | Aug 27 05:11:06 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349624455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.349624455 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.2238300726 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1132912439 ps |
| CPU time | 26.13 seconds |
| Started | Aug 27 05:11:06 PM UTC 24 |
| Finished | Aug 27 05:11:34 PM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238300726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.2238300726 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.509839548 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8755164345 ps |
| CPU time | 272.71 seconds |
| Started | Aug 27 05:09:42 PM UTC 24 |
| Finished | Aug 27 05:14:19 PM UTC 24 |
| Peak memory | 430392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509839548 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.509839548 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_error.3918964983 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9589164499 ps |
| CPU time | 303.07 seconds |
| Started | Aug 27 05:10:38 PM UTC 24 |
| Finished | Aug 27 05:15:46 PM UTC 24 |
| Peak memory | 332032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918964983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.3918964983 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.1591472931 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3073293917 ps |
| CPU time | 14.88 seconds |
| Started | Aug 27 05:10:46 PM UTC 24 |
| Finished | Aug 27 05:11:02 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591472931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1591472931 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1624985566 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 113571862 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 05:11:06 PM UTC 24 |
| Finished | Aug 27 05:11:09 PM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624985566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1624985566 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3627231659 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 31257119201 ps |
| CPU time | 1463.8 seconds |
| Started | Aug 27 05:09:24 PM UTC 24 |
| Finished | Aug 27 05:34:04 PM UTC 24 |
| Peak memory | 1079596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627231659 -assert nopostproc +UVM_T ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3627231659 +enable_masking =1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.1139631984 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 69743451009 ps |
| CPU time | 512.29 seconds |
| Started | Aug 27 05:10:19 PM UTC 24 |
| Finished | Aug 27 05:18:58 PM UTC 24 |
| Peak memory | 600760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139631984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1139631984 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.103904149 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4493934438 ps |
| CPU time | 375.55 seconds |
| Started | Aug 27 05:09:25 PM UTC 24 |
| Finished | Aug 27 05:15:46 PM UTC 24 |
| Peak memory | 358708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103904149 -assert nopostproc +UVM_TES TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.103904149 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.3133883369 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 81502167 ps |
| CPU time | 3.14 seconds |
| Started | Aug 27 05:09:20 PM UTC 24 |
| Finished | Aug 27 05:09:24 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133883369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3133883369 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.4281381752 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 189376665920 ps |
| CPU time | 1518.42 seconds |
| Started | Aug 27 05:11:10 PM UTC 24 |
| Finished | Aug 27 05:36:46 PM UTC 24 |
| Peak memory | 1172164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281381752 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.4281381752 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/7.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.2136482844 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 19484815 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 05:12:44 PM UTC 24 |
| Finished | Aug 27 05:12:46 PM UTC 24 |
| Peak memory | 225996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136482844 -assert nopostproc +UVM_TESTNAM E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2136482844 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_app.4180095468 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 12891913677 ps |
| CPU time | 185.9 seconds |
| Started | Aug 27 05:11:37 PM UTC 24 |
| Finished | Aug 27 05:14:46 PM UTC 24 |
| Peak memory | 346488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180095468 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.4180095468 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.1828641003 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 9694914270 ps |
| CPU time | 151.7 seconds |
| Started | Aug 27 05:11:44 PM UTC 24 |
| Finished | Aug 27 05:14:19 PM UTC 24 |
| Peak memory | 325936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828641003 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1828641003 +enable_maskin g=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.685753603 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 14085228076 ps |
| CPU time | 342.03 seconds |
| Started | Aug 27 05:11:37 PM UTC 24 |
| Finished | Aug 27 05:17:24 PM UTC 24 |
| Peak memory | 252212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685753603 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.685753603 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.3000889729 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 49856474 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 05:12:06 PM UTC 24 |
| Finished | Aug 27 05:12:09 PM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000889729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3000889729 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.152886997 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 56377113 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 05:12:09 PM UTC 24 |
| Finished | Aug 27 05:12:12 PM UTC 24 |
| Peak memory | 224432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152886997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.152886997 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.4205017125 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5473105581 ps |
| CPU time | 62.42 seconds |
| Started | Aug 27 05:12:13 PM UTC 24 |
| Finished | Aug 27 05:13:17 PM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205017125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.4205017125 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3847250735 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 768688800 ps |
| CPU time | 55.32 seconds |
| Started | Aug 27 05:11:46 PM UTC 24 |
| Finished | Aug 27 05:12:43 PM UTC 24 |
| Peak memory | 252172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847250735 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3847250735 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_error.4080197686 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1910263954 ps |
| CPU time | 148.41 seconds |
| Started | Aug 27 05:12:04 PM UTC 24 |
| Finished | Aug 27 05:14:35 PM UTC 24 |
| Peak memory | 295164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080197686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.4080197686 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.1723665464 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3452674911 ps |
| CPU time | 13.87 seconds |
| Started | Aug 27 05:12:05 PM UTC 24 |
| Finished | Aug 27 05:12:20 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723665464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1723665464 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.124422070 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 108647084874 ps |
| CPU time | 1796.01 seconds |
| Started | Aug 27 05:11:36 PM UTC 24 |
| Finished | Aug 27 05:41:51 PM UTC 24 |
| Peak memory | 2251040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124422070 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.124422070 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.591898681 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 12220795969 ps |
| CPU time | 118.06 seconds |
| Started | Aug 27 05:11:51 PM UTC 24 |
| Finished | Aug 27 05:13:52 PM UTC 24 |
| Peak memory | 301700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591898681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.591898681 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.1691216888 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 331092698755 ps |
| CPU time | 544.51 seconds |
| Started | Aug 27 05:11:36 PM UTC 24 |
| Finished | Aug 27 05:20:47 PM UTC 24 |
| Peak memory | 618824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691216888 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1691216888 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.1605310713 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 216077811 ps |
| CPU time | 11.75 seconds |
| Started | Aug 27 05:11:30 PM UTC 24 |
| Finished | Aug 27 05:11:43 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605310713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1605310713 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.1417350746 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 54903650832 ps |
| CPU time | 2184.73 seconds |
| Started | Aug 27 05:12:23 PM UTC 24 |
| Finished | Aug 27 05:49:13 PM UTC 24 |
| Peak memory | 1147596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417350746 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1417350746 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/8.kmac_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.797053086 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 10914751 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 05:14:35 PM UTC 24 |
| Finished | Aug 27 05:14:37 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797053086 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.797053086 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_app.33696736 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 202920584010 ps |
| CPU time | 409.96 seconds |
| Started | Aug 27 05:13:17 PM UTC 24 |
| Finished | Aug 27 05:20:13 PM UTC 24 |
| Peak memory | 444728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33696736 -assert nopostproc +UVM_TESTNA ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.33696736 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_app/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.760179397 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 33668417730 ps |
| CPU time | 281.39 seconds |
| Started | Aug 27 05:13:32 PM UTC 24 |
| Finished | Aug 27 05:18:18 PM UTC 24 |
| Peak memory | 319800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760179397 -assert nopostproc +UVM_TESTN AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.760179397 +enable_masking= 1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.2545327298 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 24103744078 ps |
| CPU time | 658.62 seconds |
| Started | Aug 27 05:13:17 PM UTC 24 |
| Finished | Aug 27 05:24:24 PM UTC 24 |
| Peak memory | 252156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545327298 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2545327298 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_burst_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.1145813935 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 720241843 ps |
| CPU time | 31.88 seconds |
| Started | Aug 27 05:14:20 PM UTC 24 |
| Finished | Aug 27 05:14:53 PM UTC 24 |
| Peak memory | 235496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145813935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1145813935 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3214545527 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 177100801 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 05:14:21 PM UTC 24 |
| Finished | Aug 27 05:14:23 PM UTC 24 |
| Peak memory | 225152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214545527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3214545527 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.1626277924 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8804624352 ps |
| CPU time | 68.49 seconds |
| Started | Aug 27 05:14:24 PM UTC 24 |
| Finished | Aug 27 05:15:34 PM UTC 24 |
| Peak memory | 235744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626277924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_ma sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1626277924 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2598381744 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 18153253684 ps |
| CPU time | 183.03 seconds |
| Started | Aug 27 05:13:47 PM UTC 24 |
| Finished | Aug 27 05:16:54 PM UTC 24 |
| Peak memory | 346368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598381744 -assert nopostproc +UVM_TEST NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2598381744 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_error.1490959969 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5810479857 ps |
| CPU time | 181.14 seconds |
| Started | Aug 27 05:13:57 PM UTC 24 |
| Finished | Aug 27 05:17:01 PM UTC 24 |
| Peak memory | 389372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490959969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.1490959969 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.4244534593 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5189121034 ps |
| CPU time | 9.27 seconds |
| Started | Aug 27 05:14:20 PM UTC 24 |
| Finished | Aug 27 05:14:30 PM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244534593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.4244534593 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_key_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.3675820599 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 44863252 ps |
| CPU time | 2.17 seconds |
| Started | Aug 27 05:14:24 PM UTC 24 |
| Finished | Aug 27 05:14:27 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675820599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3675820599 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.968441584 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 102190525763 ps |
| CPU time | 3699.3 seconds |
| Started | Aug 27 05:12:50 PM UTC 24 |
| Finished | Aug 27 06:15:08 PM UTC 24 |
| Peak memory | 3985808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968441584 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.968441584 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.4179695245 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 35332175877 ps |
| CPU time | 354.48 seconds |
| Started | Aug 27 05:12:55 PM UTC 24 |
| Finished | Aug 27 05:18:55 PM UTC 24 |
| Peak memory | 354572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179695245 -assert nopostproc +UVM_TE STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.4179695245 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.1030217229 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 953167129 ps |
| CPU time | 28.44 seconds |
| Started | Aug 27 05:12:47 PM UTC 24 |
| Finished | Aug 27 05:13:17 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030217229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST _SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1030217229 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.2497616791 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 24764946643 ps |
| CPU time | 2068.09 seconds |
| Started | Aug 27 05:14:28 PM UTC 24 |
| Finished | Aug 27 05:49:20 PM UTC 24 |
| Peak memory | 791248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/ scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497616791 -assert nopostpr oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2497616791 +enable_masking=1 +sw_key_masked=0 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/9.kmac_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |