Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15432487	1			T1	91		T2	68		T17	118
all_values[1]	15432487	1			T1	91		T2	68		T17	118
all_values[2]	15432487	1			T1	91		T2	68		T17	118

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570015

1

T1

17

T2

92

T17

14

auto[1]

45727446

1

T1

256

T2

112

T17

340

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46079223

1

T1

264

T2

186

T17

342

auto[1]

218238

1

T1

9

T2

18

T17

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	210041	1			T2	62		T44	1		T5	1
all_values[0]	auto[0]	auto[1]	1296	1			T2	6		T44	2		T53	4
all_values[0]	auto[1]	auto[0]	15149700	1			T1	88		T17	114		T49	145
all_values[0]	auto[1]	auto[1]	71450	1			T1	3		T17	4		T49	5
all_values[1]	auto[0]	auto[0]	159326	1			T2	8		T17	6		T94	10
all_values[1]	auto[0]	auto[1]	1024	1			T2	4		T17	1		T94	3
all_values[1]	auto[1]	auto[0]	15200415	1			T1	88		T2	54		T17	108
all_values[1]	auto[1]	auto[1]	71722	1			T1	3		T2	2		T17	3
all_values[2]	auto[0]	auto[0]	197344	1			T1	15		T2	8		T17	6
all_values[2]	auto[0]	auto[1]	984	1			T1	2		T2	4		T17	1
all_values[2]	auto[1]	auto[0]	15162397	1			T1	73		T2	54		T17	108
all_values[2]	auto[1]	auto[1]	71762	1			T1	1		T2	2		T17	3