Group : kmac_env_pkg::kmac_env_cov::entropy_timer_cg
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Summary for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
entropy_edn_mode_enabled 2 0 2 100.00 100 1 1 2
prescaler_val 3 0 3 100.00 100 1 1 0
wait_timer_val 3 0 3 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::entropy_timer_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
entropy_timer_cross 18 0 18 100.00 100 1 1 0


Summary for Variable entropy_edn_mode_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for entropy_edn_mode_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 58858 1 T1 6 T2 2 T10 2
auto[1] 51270 1 T2 4 T52 4 T53 208



Summary for Variable prescaler_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for prescaler_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 27115 1 T17 2 T49 2 T44 35
lower_val 27184 1 T1 2 T2 3 T9 1
zero_val 844 1 T1 1 T2 1 T10 1



Summary for Variable wait_timer_val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for wait_timer_val

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val 41986 1 T1 4 T2 2 T17 2
lower_val 42392 1 T1 2 T17 4 T49 6
zero_val 25750 1 T2 4 T10 2 T9 2



Summary for Cross entropy_timer_cross

Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for entropy_timer_cross

Bins
prescaler_valwait_timer_valentropy_edn_mode_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
higher_val higher_val auto[0] 7054 1 T17 1 T44 18 T4 13
higher_val higher_val auto[1] 3233 1 T53 13 T102 10 T60 10
higher_val lower_val auto[0] 7116 1 T17 1 T49 2 T44 17
higher_val lower_val auto[1] 3278 1 T53 20 T102 5 T60 5
higher_val zero_val auto[0] 44 1 T11 1 T12 1 T84 1
higher_val zero_val auto[1] 6390 1 T53 11 T102 33 T60 32
lower_val higher_val auto[0] 7119 1 T1 2 T51 2 T44 14
lower_val higher_val auto[1] 3153 1 T2 2 T53 7 T102 15
lower_val lower_val auto[0] 7385 1 T51 2 T44 16 T4 10
lower_val lower_val auto[1] 3195 1 T52 2 T53 20 T102 18
lower_val zero_val auto[0] 55 1 T9 1 T52 1 T38 1
lower_val zero_val auto[1] 6277 1 T2 1 T52 1 T53 24
zero_val higher_val auto[0] 288 1 T1 1 T17 1 T4 1
zero_val higher_val auto[1] 57 1 T65 2 T186 2 T66 3
zero_val lower_val auto[0] 253 1 T49 1 T51 1 T44 1
zero_val lower_val auto[1] 56 1 T202 2 T16 1 T66 1
zero_val zero_val auto[0] 132 1 T2 1 T10 1 T9 1
zero_val zero_val auto[1] 58 1 T65 1 T202 2 T66 1

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