Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15432487	1			T1	91		T2	68		T17	118
all_pins[1]	15432487	1			T1	91		T2	68		T17	118
all_pins[2]	15432487	1			T1	91		T2	68		T17	118

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45960538	1			T1	270		T2	204		T17	350
values[0x1]	336923	1			T1	3		T17	4		T49	5
transitions[0x0=>0x1]	335172	1			T1	3		T17	4		T49	5
transitions[0x1=>0x0]	335194	1			T1	3		T17	4		T49	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15361037	1			T1	88		T2	68		T17	114
all_pins[0]	values[0x1]	71450	1			T1	3		T17	4		T49	5
all_pins[0]	transitions[0x0=>0x1]	71442	1			T1	3		T17	4		T49	5
all_pins[0]	transitions[0x1=>0x0]	5687	1			T56	1		T11	2		T12	2
all_pins[1]	values[0x0]	15426792	1			T1	91		T2	68		T17	118
all_pins[1]	values[0x1]	5695	1			T56	1		T11	2		T12	2
all_pins[1]	transitions[0x0=>0x1]	5521	1			T56	1		T11	2		T12	2
all_pins[1]	transitions[0x1=>0x0]	259604	1			T57	208		T32	683		T14	4303
all_pins[2]	values[0x0]	15172709	1			T1	91		T2	68		T17	118
all_pins[2]	values[0x1]	259778	1			T57	208		T32	683		T14	4312
all_pins[2]	transitions[0x0=>0x1]	258209	1			T57	208		T32	680		T14	4285
all_pins[2]	transitions[0x1=>0x0]	69903	1			T1	3		T17	4		T49	5