Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	629	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5266	1			T11	3		T12	2		T65	1
len_601_800	11965	1			T12	2		T57	5		T65	2
len_401_600	8058	1			T11	2		T57	3		T13	5
len_201_400	4009	1			T11	1		T12	2		T65	1
len_65_200	7810	1			T60	37		T62	43		T91	77
len_min_for_xof_require_squeeze	79	1			T91	2		T156	1		T96	1
len_keccak_block_sizes[72]	79	1			T62	1		T91	1		T206	1
len_keccak_block_sizes[104]	65	1			T60	2		T156	1		T206	1
len_keccak_block_sizes[136]	67	1			T62	1		T206	2		T207	9
len_keccak_block_sizes[144]	33	1			T60	2		T208	1		T77	1
len_keccak_block_sizes[168]	30	1			T209	1		T210	5		T211	1
len_datapath_width	1019	1			T17	3		T49	3		T44	73
len_2_63	14594	1			T1	3		T2	3		T51	3
len_1	60	1			T62	1		T91	2		T156	1