Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T141 7 T143 4 T178 7
all_values[1] 275 1 T141 7 T143 4 T178 7
all_values[2] 275 1 T141 7 T143 4 T178 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 444 1 T141 12 T143 4 T178 9
auto[1] 381 1 T141 9 T143 8 T178 12


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 392 1 T141 7 T143 6 T178 9
auto[1] 433 1 T141 14 T143 6 T178 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 494 1 T141 9 T143 6 T178 12
auto[1] 331 1 T141 12 T143 6 T178 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T141 1 T178 3 T173 1
all_values[0] auto[0] auto[0] auto[1] 19 1 T141 1 T179 1 T180 1
all_values[0] auto[0] auto[1] auto[0] 50 1 T143 2 T178 2 T173 1
all_values[0] auto[0] auto[1] auto[1] 28 1 T173 3 T181 2 T179 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T141 2 T143 2 T182 2
all_values[0] auto[1] auto[1] auto[1] 46 1 T141 3 T178 2 T173 2
all_values[1] auto[0] auto[0] auto[0] 89 1 T141 2 T143 1 T178 2
all_values[1] auto[0] auto[1] auto[0] 71 1 T141 1 T143 1 T178 1
all_values[1] auto[1] auto[0] auto[1] 70 1 T141 3 T178 3 T173 2
all_values[1] auto[1] auto[1] auto[1] 45 1 T141 1 T143 2 T178 1
all_values[2] auto[0] auto[0] auto[0] 55 1 T141 1 T143 1 T173 2
all_values[2] auto[0] auto[0] auto[1] 24 1 T178 1 T173 2 T183 1
all_values[2] auto[0] auto[1] auto[0] 64 1 T141 2 T143 1 T178 1
all_values[2] auto[0] auto[1] auto[1] 31 1 T141 1 T178 2 T181 2
all_values[2] auto[1] auto[0] auto[1] 55 1 T141 2 T173 3 T183 1
all_values[2] auto[1] auto[1] auto[1] 46 1 T141 1 T143 2 T178 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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