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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.14 97.91 92.62 99.89 76.06 95.59 99.05 97.88


Total test records in report: 880
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T762 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2343424807 Sep 01 02:43:56 PM UTC 24 Sep 01 02:43:59 PM UTC 24 31858568 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3287695544 Sep 01 02:43:55 PM UTC 24 Sep 01 02:43:59 PM UTC 24 105604217 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2875325038 Sep 01 02:43:54 PM UTC 24 Sep 01 02:44:01 PM UTC 24 260452769 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3489939786 Sep 01 02:43:59 PM UTC 24 Sep 01 02:44:01 PM UTC 24 42501308 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3785181165 Sep 01 02:43:56 PM UTC 24 Sep 01 02:44:01 PM UTC 24 39814296 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.386717179 Sep 01 02:43:58 PM UTC 24 Sep 01 02:44:01 PM UTC 24 245257869 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2986627928 Sep 01 02:44:00 PM UTC 24 Sep 01 02:44:02 PM UTC 24 24873208 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2867070496 Sep 01 02:44:00 PM UTC 24 Sep 01 02:44:03 PM UTC 24 343380554 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2061377463 Sep 01 02:43:59 PM UTC 24 Sep 01 02:44:05 PM UTC 24 869312026 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.353618631 Sep 01 02:44:02 PM UTC 24 Sep 01 02:44:05 PM UTC 24 49706258 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3625950066 Sep 01 02:44:04 PM UTC 24 Sep 01 02:44:06 PM UTC 24 16570374 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.761316089 Sep 01 02:43:59 PM UTC 24 Sep 01 02:44:07 PM UTC 24 675494006 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1641450883 Sep 01 02:44:02 PM UTC 24 Sep 01 02:44:07 PM UTC 24 339483282 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1804471516 Sep 01 02:44:02 PM UTC 24 Sep 01 02:44:07 PM UTC 24 121536089 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2788269645 Sep 01 02:43:38 PM UTC 24 Sep 01 02:44:07 PM UTC 24 993868486 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1434915179 Sep 01 02:44:05 PM UTC 24 Sep 01 02:44:08 PM UTC 24 22033430 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3090829124 Sep 01 02:44:02 PM UTC 24 Sep 01 02:44:08 PM UTC 24 213136256 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2938611636 Sep 01 02:44:07 PM UTC 24 Sep 01 02:44:10 PM UTC 24 80898127 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3318524970 Sep 01 02:44:05 PM UTC 24 Sep 01 02:44:10 PM UTC 24 151064929 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.4235923271 Sep 01 02:44:03 PM UTC 24 Sep 01 02:44:10 PM UTC 24 99404091 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4239525649 Sep 01 02:44:07 PM UTC 24 Sep 01 02:44:11 PM UTC 24 28852336 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2086691517 Sep 01 02:44:09 PM UTC 24 Sep 01 02:44:11 PM UTC 24 26643615 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2856555610 Sep 01 02:44:09 PM UTC 24 Sep 01 02:44:11 PM UTC 24 112373088 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3373267202 Sep 01 02:44:07 PM UTC 24 Sep 01 02:44:12 PM UTC 24 147846370 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1293111179 Sep 01 02:44:09 PM UTC 24 Sep 01 02:44:13 PM UTC 24 163110033 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2475570230 Sep 01 02:44:11 PM UTC 24 Sep 01 02:44:13 PM UTC 24 77112523 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.518467426 Sep 01 02:44:12 PM UTC 24 Sep 01 02:44:14 PM UTC 24 17041133 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3449282728 Sep 01 02:44:09 PM UTC 24 Sep 01 02:44:15 PM UTC 24 231257214 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3576989561 Sep 01 02:44:13 PM UTC 24 Sep 01 02:44:16 PM UTC 24 119962282 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3241223579 Sep 01 02:44:11 PM UTC 24 Sep 01 02:44:16 PM UTC 24 76737285 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.4053445764 Sep 01 02:44:11 PM UTC 24 Sep 01 02:44:16 PM UTC 24 112793128 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.327153319 Sep 01 02:44:12 PM UTC 24 Sep 01 02:44:17 PM UTC 24 464103269 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.292685019 Sep 01 02:44:12 PM UTC 24 Sep 01 02:44:17 PM UTC 24 478150264 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1451307019 Sep 01 02:44:12 PM UTC 24 Sep 01 02:44:18 PM UTC 24 180794969 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1865155328 Sep 01 02:44:14 PM UTC 24 Sep 01 02:44:18 PM UTC 24 76657697 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.253727285 Sep 01 02:44:15 PM UTC 24 Sep 01 02:44:18 PM UTC 24 136121881 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2296421118 Sep 01 02:44:14 PM UTC 24 Sep 01 02:44:19 PM UTC 24 123190141 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2906447193 Sep 01 02:44:17 PM UTC 24 Sep 01 02:44:19 PM UTC 24 13641773 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.4294511552 Sep 01 02:44:17 PM UTC 24 Sep 01 02:44:21 PM UTC 24 67056037 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3373114952 Sep 01 02:44:18 PM UTC 24 Sep 01 02:44:21 PM UTC 24 76232444 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2165588165 Sep 01 02:44:19 PM UTC 24 Sep 01 02:44:21 PM UTC 24 27286578 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.872934663 Sep 01 02:44:16 PM UTC 24 Sep 01 02:44:21 PM UTC 24 151150705 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3156846444 Sep 01 02:44:18 PM UTC 24 Sep 01 02:44:22 PM UTC 24 161540250 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3534930315 Sep 01 02:44:20 PM UTC 24 Sep 01 02:44:23 PM UTC 24 12502626 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2654941911 Sep 01 02:44:19 PM UTC 24 Sep 01 02:44:23 PM UTC 24 20754929 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3853687540 Sep 01 02:44:21 PM UTC 24 Sep 01 02:44:24 PM UTC 24 19025436 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1170201102 Sep 01 02:44:20 PM UTC 24 Sep 01 02:44:24 PM UTC 24 89269554 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1192960691 Sep 01 02:44:17 PM UTC 24 Sep 01 02:44:24 PM UTC 24 379503428 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3819472776 Sep 01 02:44:20 PM UTC 24 Sep 01 02:44:25 PM UTC 24 198227187 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3514576860 Sep 01 02:44:20 PM UTC 24 Sep 01 02:44:25 PM UTC 24 301244827 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1942253134 Sep 01 02:44:22 PM UTC 24 Sep 01 02:44:25 PM UTC 24 116103452 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3431060674 Sep 01 02:44:22 PM UTC 24 Sep 01 02:44:26 PM UTC 24 32244351 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1814588210 Sep 01 02:44:22 PM UTC 24 Sep 01 02:44:26 PM UTC 24 88838566 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.598837659 Sep 01 02:44:25 PM UTC 24 Sep 01 02:44:27 PM UTC 24 15614145 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.3582220633 Sep 01 02:44:25 PM UTC 24 Sep 01 02:44:27 PM UTC 24 61425480 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2266378079 Sep 01 02:44:26 PM UTC 24 Sep 01 02:44:28 PM UTC 24 88088592 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2080289709 Sep 01 02:44:24 PM UTC 24 Sep 01 02:44:29 PM UTC 24 383305211 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2066475886 Sep 01 02:44:26 PM UTC 24 Sep 01 02:44:29 PM UTC 24 189838760 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4130073024 Sep 01 02:44:23 PM UTC 24 Sep 01 02:44:29 PM UTC 24 319388044 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2315760387 Sep 01 02:44:23 PM UTC 24 Sep 01 02:44:30 PM UTC 24 159865334 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2131483206 Sep 01 02:44:26 PM UTC 24 Sep 01 02:44:30 PM UTC 24 596562877 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1549171824 Sep 01 02:44:28 PM UTC 24 Sep 01 02:44:31 PM UTC 24 60955747 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1068725455 Sep 01 02:44:28 PM UTC 24 Sep 01 02:44:31 PM UTC 24 40046561 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2141970997 Sep 01 02:44:27 PM UTC 24 Sep 01 02:44:31 PM UTC 24 98384637 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.50566602 Sep 01 02:44:28 PM UTC 24 Sep 01 02:44:32 PM UTC 24 209684351 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3746739038 Sep 01 02:44:27 PM UTC 24 Sep 01 02:44:33 PM UTC 24 349321815 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.421917247 Sep 01 02:44:30 PM UTC 24 Sep 01 02:44:33 PM UTC 24 156749728 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1389574803 Sep 01 02:44:29 PM UTC 24 Sep 01 02:44:34 PM UTC 24 339987479 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.716208111 Sep 01 02:44:32 PM UTC 24 Sep 01 02:44:34 PM UTC 24 14398043 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2809714636 Sep 01 02:44:32 PM UTC 24 Sep 01 02:44:34 PM UTC 24 56806596 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.717912069 Sep 01 02:44:27 PM UTC 24 Sep 01 02:44:34 PM UTC 24 684055548 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1239520312 Sep 01 02:44:30 PM UTC 24 Sep 01 02:44:34 PM UTC 24 203842217 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1743083244 Sep 01 02:44:32 PM UTC 24 Sep 01 02:44:34 PM UTC 24 75389169 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2081805855 Sep 01 02:44:30 PM UTC 24 Sep 01 02:44:35 PM UTC 24 237109809 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4107516510 Sep 01 02:44:33 PM UTC 24 Sep 01 02:44:36 PM UTC 24 45096503 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4224986917 Sep 01 02:44:32 PM UTC 24 Sep 01 02:44:36 PM UTC 24 142161151 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1239772844 Sep 01 02:44:33 PM UTC 24 Sep 01 02:44:36 PM UTC 24 64191133 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.887158479 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:38 PM UTC 24 11708091 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1717540799 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:38 PM UTC 24 64732888 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.4033863521 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:38 PM UTC 24 98782016 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1786217878 Sep 01 02:44:32 PM UTC 24 Sep 01 02:44:39 PM UTC 24 358959323 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3344905149 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:39 PM UTC 24 186545414 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.544767171 Sep 01 02:44:36 PM UTC 24 Sep 01 02:44:39 PM UTC 24 29235893 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2530363189 Sep 01 02:44:34 PM UTC 24 Sep 01 02:44:39 PM UTC 24 153740798 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.319027770 Sep 01 02:44:34 PM UTC 24 Sep 01 02:44:40 PM UTC 24 330532750 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.824670243 Sep 01 02:44:38 PM UTC 24 Sep 01 02:44:40 PM UTC 24 115338381 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1708843966 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:40 PM UTC 24 38278240 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.44033818 Sep 01 02:44:35 PM UTC 24 Sep 01 02:44:41 PM UTC 24 481634229 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.767824814 Sep 01 02:44:36 PM UTC 24 Sep 01 02:44:41 PM UTC 24 206575739 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3310258097 Sep 01 02:44:39 PM UTC 24 Sep 01 02:44:41 PM UTC 24 109171434 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.88009672 Sep 01 02:44:38 PM UTC 24 Sep 01 02:44:42 PM UTC 24 70451145 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1737154501 Sep 01 02:44:36 PM UTC 24 Sep 01 02:44:42 PM UTC 24 438293096 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1830214414 Sep 01 02:44:39 PM UTC 24 Sep 01 02:44:42 PM UTC 24 40831987 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4069664448 Sep 01 02:44:40 PM UTC 24 Sep 01 02:44:42 PM UTC 24 24076883 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2717141914 Sep 01 02:44:39 PM UTC 24 Sep 01 02:44:42 PM UTC 24 83760261 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.182395256 Sep 01 02:44:40 PM UTC 24 Sep 01 02:44:43 PM UTC 24 39939009 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4056962780 Sep 01 02:44:41 PM UTC 24 Sep 01 02:44:43 PM UTC 24 14387007 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3830346112 Sep 01 02:44:42 PM UTC 24 Sep 01 02:44:45 PM UTC 24 47918613 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3287124636 Sep 01 02:44:42 PM UTC 24 Sep 01 02:44:45 PM UTC 24 15880335 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3300451515 Sep 01 02:44:42 PM UTC 24 Sep 01 02:44:45 PM UTC 24 41620831 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2231572332 Sep 01 02:44:42 PM UTC 24 Sep 01 02:44:45 PM UTC 24 12002723 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3742456018 Sep 01 02:44:41 PM UTC 24 Sep 01 02:44:45 PM UTC 24 82578314 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3592104022 Sep 01 02:44:40 PM UTC 24 Sep 01 02:44:45 PM UTC 24 340426423 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1680498474 Sep 01 02:44:41 PM UTC 24 Sep 01 02:44:45 PM UTC 24 497675947 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2836923804 Sep 01 02:44:40 PM UTC 24 Sep 01 02:44:46 PM UTC 24 192080233 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.120702984 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 34448337 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1948461974 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 41704684 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3560140537 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 13389747 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.73381786 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 34057803 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2999884672 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 14696815 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1497364929 Sep 01 02:44:44 PM UTC 24 Sep 01 02:44:46 PM UTC 24 44589213 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.143884702 Sep 01 02:44:45 PM UTC 24 Sep 01 02:44:47 PM UTC 24 30737867 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1055361984 Sep 01 02:44:45 PM UTC 24 Sep 01 02:44:47 PM UTC 24 49404513 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3978831323 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:48 PM UTC 24 28575463 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2717761667 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:48 PM UTC 24 45698770 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2180142238 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:48 PM UTC 24 40759151 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.4208175450 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:48 PM UTC 24 48139310 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1360371022 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:48 PM UTC 24 19060344 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1265497847 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:49 PM UTC 24 48291550 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1134290587 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:49 PM UTC 24 16783762 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.455851045 Sep 01 02:44:46 PM UTC 24 Sep 01 02:44:49 PM UTC 24 39201603 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.833072496 Sep 01 02:44:47 PM UTC 24 Sep 01 02:44:50 PM UTC 24 21523681 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4143567465 Sep 01 02:44:47 PM UTC 24 Sep 01 02:44:50 PM UTC 24 18733442 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4109754331 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 43950949 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.372415620 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 31766212 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.130359483 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 56104376 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3293047852 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 14351152 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3142998529 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 45051602 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.570991329 Sep 01 02:44:48 PM UTC 24 Sep 01 02:44:50 PM UTC 24 23782670 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2543102656 Sep 01 02:44:49 PM UTC 24 Sep 01 02:44:51 PM UTC 24 42042542 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.4281510972
Short name T49
Test name
Test status
Simulation time 112099686 ps
CPU time 2.79 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:18 PM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281510972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.4281510972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.2011472906
Short name T4
Test name
Test status
Simulation time 4609459726 ps
CPU time 13.67 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:29 PM UTC 24
Peak memory 229676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011472906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.2011472906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.3947874914
Short name T16
Test name
Test status
Simulation time 4280383177 ps
CPU time 117.79 seconds
Started Sep 01 01:47:51 PM UTC 24
Finished Sep 01 01:49:51 PM UTC 24
Peak memory 281588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3947874914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_r
and_reset.3947874914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.1812847005
Short name T9
Test name
Test status
Simulation time 46213170 ps
CPU time 1.23 seconds
Started Sep 01 01:47:16 PM UTC 24
Finished Sep 01 01:47:19 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812847005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1812847005 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3309486235
Short name T110
Test name
Test status
Simulation time 442712548 ps
CPU time 3.7 seconds
Started Sep 01 02:42:40 PM UTC 24
Finished Sep 01 02:42:45 PM UTC 24
Peak memory 230000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309486235 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.3309
486235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_app.174569197
Short name T12
Test name
Test status
Simulation time 241387160 ps
CPU time 19.27 seconds
Started Sep 01 01:47:38 PM UTC 24
Finished Sep 01 01:47:58 PM UTC 24
Peak memory 236036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174569197 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.174569197 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.940138913
Short name T40
Test name
Test status
Simulation time 9960979929 ps
CPU time 40.05 seconds
Started Sep 01 01:47:18 PM UTC 24
Finished Sep 01 01:48:00 PM UTC 24
Peak memory 276932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940138913 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.940138913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.2854985686
Short name T8
Test name
Test status
Simulation time 647569317 ps
CPU time 5.23 seconds
Started Sep 01 01:47:15 PM UTC 24
Finished Sep 01 01:47:22 PM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854985686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.2854985686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.2603737934
Short name T43
Test name
Test status
Simulation time 63344315 ps
CPU time 2.36 seconds
Started Sep 01 01:50:34 PM UTC 24
Finished Sep 01 01:50:37 PM UTC 24
Peak memory 234040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603737934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2603737934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_error.730006784
Short name T20
Test name
Test status
Simulation time 18434648226 ps
CPU time 156.32 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:49:51 PM UTC 24
Peak memory 367148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730006784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.730006784 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.3713013621
Short name T62
Test name
Test status
Simulation time 2216243371 ps
CPU time 40.96 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:56 PM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713013621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.3713013621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1595338361
Short name T115
Test name
Test status
Simulation time 190412956 ps
CPU time 1.76 seconds
Started Sep 01 02:43:40 PM UTC 24
Finished Sep 01 02:43:43 PM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595338361 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1595338361 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.1940050118
Short name T3
Test name
Test status
Simulation time 13738913 ps
CPU time 0.72 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:47:14 PM UTC 24
Peak memory 227216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940050118 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1940050118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.895899887
Short name T141
Test name
Test status
Simulation time 11655365 ps
CPU time 1.21 seconds
Started Sep 01 02:42:46 PM UTC 24
Finished Sep 01 02:42:49 PM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895899887 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.895899887 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.1352692741
Short name T67
Test name
Test status
Simulation time 41304283 ps
CPU time 2.17 seconds
Started Sep 01 01:55:51 PM UTC 24
Finished Sep 01 01:55:54 PM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352692741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1352692741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.4235923271
Short name T199
Test name
Test status
Simulation time 99404091 ps
CPU time 6.02 seconds
Started Sep 01 02:44:03 PM UTC 24
Finished Sep 01 02:44:10 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235923271 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.4235923271 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.2227860780
Short name T63
Test name
Test status
Simulation time 215279457 ps
CPU time 7.38 seconds
Started Sep 01 01:55:25 PM UTC 24
Finished Sep 01 01:55:33 PM UTC 24
Peak memory 242428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227860780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2227860780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.512815915
Short name T96
Test name
Test status
Simulation time 30316190424 ps
CPU time 205.99 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:50:44 PM UTC 24
Peak memory 375464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512815915 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.512815915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.2853439196
Short name T47
Test name
Test status
Simulation time 33257129 ps
CPU time 0.84 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:16 PM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853439196 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2853439196 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.2215970653
Short name T157
Test name
Test status
Simulation time 149562095 ps
CPU time 2.14 seconds
Started Sep 01 02:42:58 PM UTC 24
Finished Sep 01 02:43:01 PM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215970653 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.2215970653 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2900688838
Short name T10
Test name
Test status
Simulation time 106108661 ps
CPU time 1.1 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:16 PM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900688838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2900688838 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.3748394192
Short name T71
Test name
Test status
Simulation time 258416938 ps
CPU time 2.09 seconds
Started Sep 01 01:56:38 PM UTC 24
Finished Sep 01 01:56:41 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748394192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3748394192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.2152904052
Short name T72
Test name
Test status
Simulation time 48129504 ps
CPU time 2.85 seconds
Started Sep 01 02:03:05 PM UTC 24
Finished Sep 01 02:03:09 PM UTC 24
Peak memory 234096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152904052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2152904052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.4192634214
Short name T93
Test name
Test status
Simulation time 52537979 ps
CPU time 1.99 seconds
Started Sep 01 02:35:51 PM UTC 24
Finished Sep 01 02:35:54 PM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192634214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.4192634214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_error.3403628455
Short name T177
Test name
Test status
Simulation time 18245484017 ps
CPU time 561.04 seconds
Started Sep 01 01:47:15 PM UTC 24
Finished Sep 01 01:56:44 PM UTC 24
Peak memory 627248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403628455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3403628455 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.3894286668
Short name T46
Test name
Test status
Simulation time 45454545 ps
CPU time 0.72 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:16 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894286668 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3894286668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.4268917667
Short name T82
Test name
Test status
Simulation time 17818682262 ps
CPU time 466.81 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:55:07 PM UTC 24
Peak memory 514336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268917667 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4268917667 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_error.4219019191
Short name T57
Test name
Test status
Simulation time 1241934082 ps
CPU time 30.37 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:48:00 PM UTC 24
Peak memory 266732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219019191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.4219019191 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1638912155
Short name T53
Test name
Test status
Simulation time 801905864 ps
CPU time 20.63 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:47:31 PM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638912155 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1638912155 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2836923804
Short name T191
Test name
Test status
Simulation time 192080233 ps
CPU time 4.48 seconds
Started Sep 01 02:44:40 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 225152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836923804 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2836923804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3175331444
Short name T173
Test name
Test status
Simulation time 55781019 ps
CPU time 1.23 seconds
Started Sep 01 02:43:14 PM UTC 24
Finished Sep 01 02:43:16 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175331444 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3175331444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.4228744628
Short name T99
Test name
Test status
Simulation time 6045437224 ps
CPU time 361.35 seconds
Started Sep 01 01:54:56 PM UTC 24
Finished Sep 01 02:01:03 PM UTC 24
Peak memory 330280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228744628 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.4228744628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1942253134
Short name T806
Test name
Test status
Simulation time 116103452 ps
CPU time 1.97 seconds
Started Sep 01 02:44:22 PM UTC 24
Finished Sep 01 02:44:25 PM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942253134 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.1942253134 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.757784149
Short name T124
Test name
Test status
Simulation time 6242530516 ps
CPU time 19.45 seconds
Started Sep 01 02:14:07 PM UTC 24
Finished Sep 01 02:14:28 PM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757784149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.757784149 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.2001530624
Short name T210
Test name
Test status
Simulation time 22188528808 ps
CPU time 425.8 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:54:26 PM UTC 24
Peak memory 272832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001530624 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2001530624 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.3977317395
Short name T261
Test name
Test status
Simulation time 29628458142 ps
CPU time 331.23 seconds
Started Sep 01 01:50:14 PM UTC 24
Finished Sep 01 01:55:50 PM UTC 24
Peak memory 346812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977317395 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3977317395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2692435894
Short name T275
Test name
Test status
Simulation time 89558032790 ps
CPU time 263.77 seconds
Started Sep 01 01:52:20 PM UTC 24
Finished Sep 01 01:56:47 PM UTC 24
Peak memory 406372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692435894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2692435894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3449282728
Short name T195
Test name
Test status
Simulation time 231257214 ps
CPU time 5.84 seconds
Started Sep 01 02:44:09 PM UTC 24
Finished Sep 01 02:44:15 PM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449282728 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3449282728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1708390388
Short name T193
Test name
Test status
Simulation time 109631336 ps
CPU time 4.11 seconds
Started Sep 01 02:43:26 PM UTC 24
Finished Sep 01 02:43:31 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708390388 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1708390388 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2655831991
Short name T106
Test name
Test status
Simulation time 25661517772 ps
CPU time 264.48 seconds
Started Sep 01 02:21:14 PM UTC 24
Finished Sep 01 02:25:42 PM UTC 24
Peak memory 440932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655831991 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2655831991 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2579216926
Short name T111
Test name
Test status
Simulation time 136452598 ps
CPU time 1.95 seconds
Started Sep 01 02:42:53 PM UTC 24
Finished Sep 01 02:42:56 PM UTC 24
Peak memory 226428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579216926 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.2579216926 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_error.3719066877
Short name T35
Test name
Test status
Simulation time 17222851674 ps
CPU time 353.9 seconds
Started Sep 01 01:55:04 PM UTC 24
Finished Sep 01 02:01:04 PM UTC 24
Peak memory 469604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719066877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3719066877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.919973521
Short name T729
Test name
Test status
Simulation time 143650522 ps
CPU time 10.7 seconds
Started Sep 01 02:42:50 PM UTC 24
Finished Sep 01 02:43:02 PM UTC 24
Peak memory 225484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919973521 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.919973521 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.1113104579
Short name T732
Test name
Test status
Simulation time 489271617 ps
CPU time 15.78 seconds
Started Sep 01 02:42:49 PM UTC 24
Finished Sep 01 02:43:07 PM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113104579 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1113104579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2352929857
Short name T142
Test name
Test status
Simulation time 24632419 ps
CPU time 1.49 seconds
Started Sep 01 02:42:47 PM UTC 24
Finished Sep 01 02:42:50 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352929857 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2352929857 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1200284367
Short name T146
Test name
Test status
Simulation time 246444908 ps
CPU time 3.52 seconds
Started Sep 01 02:42:53 PM UTC 24
Finished Sep 01 02:42:57 PM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1200284367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_
rw_with_rand_reset.1200284367 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.1741805913
Short name T201
Test name
Test status
Simulation time 27277616 ps
CPU time 1.84 seconds
Started Sep 01 02:42:48 PM UTC 24
Finished Sep 01 02:42:51 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741805913 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1741805913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1914967615
Short name T726
Test name
Test status
Simulation time 92514446 ps
CPU time 1.85 seconds
Started Sep 01 02:42:44 PM UTC 24
Finished Sep 01 02:42:47 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914967615 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1914967615 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.1764815839
Short name T725
Test name
Test status
Simulation time 28022712 ps
CPU time 1.17 seconds
Started Sep 01 02:42:41 PM UTC 24
Finished Sep 01 02:42:43 PM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764815839 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1764815839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.34882863
Short name T727
Test name
Test status
Simulation time 121693600 ps
CPU time 2.13 seconds
Started Sep 01 02:42:51 PM UTC 24
Finished Sep 01 02:42:54 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34882863 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.34882863 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1106061505
Short name T113
Test name
Test status
Simulation time 67873115 ps
CPU time 1.64 seconds
Started Sep 01 02:42:37 PM UTC 24
Finished Sep 01 02:42:39 PM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106061505 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1106061505 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3234591760
Short name T145
Test name
Test status
Simulation time 69559180 ps
CPU time 3.15 seconds
Started Sep 01 02:42:44 PM UTC 24
Finished Sep 01 02:42:48 PM UTC 24
Peak memory 225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234591760 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3234591760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.1487355500
Short name T138
Test name
Test status
Simulation time 432204796 ps
CPU time 4.37 seconds
Started Sep 01 02:42:45 PM UTC 24
Finished Sep 01 02:42:51 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487355500 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.1487355500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.448975827
Short name T737
Test name
Test status
Simulation time 2113074053 ps
CPU time 13.26 seconds
Started Sep 01 02:43:05 PM UTC 24
Finished Sep 01 02:43:20 PM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448975827 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.448975827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.1053634871
Short name T738
Test name
Test status
Simulation time 4022533094 ps
CPU time 13.38 seconds
Started Sep 01 02:43:05 PM UTC 24
Finished Sep 01 02:43:20 PM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053634871 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1053634871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.1152328253
Short name T731
Test name
Test status
Simulation time 142083356 ps
CPU time 1.64 seconds
Started Sep 01 02:43:02 PM UTC 24
Finished Sep 01 02:43:05 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152328253 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1152328253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.920062903
Short name T148
Test name
Test status
Simulation time 201165946 ps
CPU time 2.09 seconds
Started Sep 01 02:43:06 PM UTC 24
Finished Sep 01 02:43:10 PM UTC 24
Peak memory 231816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=920062903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_r
w_with_rand_reset.920062903 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.3513362214
Short name T730
Test name
Test status
Simulation time 32551604 ps
CPU time 1.34 seconds
Started Sep 01 02:43:02 PM UTC 24
Finished Sep 01 02:43:05 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513362214 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3513362214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.855956493
Short name T178
Test name
Test status
Simulation time 43622148 ps
CPU time 1.2 seconds
Started Sep 01 02:43:02 PM UTC 24
Finished Sep 01 02:43:04 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855956493 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.855956493 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1357809223
Short name T728
Test name
Test status
Simulation time 38974050 ps
CPU time 1.15 seconds
Started Sep 01 02:42:57 PM UTC 24
Finished Sep 01 02:42:59 PM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357809223 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1357809223 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.710994511
Short name T733
Test name
Test status
Simulation time 140202164 ps
CPU time 2.04 seconds
Started Sep 01 02:43:05 PM UTC 24
Finished Sep 01 02:43:09 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710994511 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.710994511 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1366429503
Short name T112
Test name
Test status
Simulation time 56525514 ps
CPU time 2.77 seconds
Started Sep 01 02:42:55 PM UTC 24
Finished Sep 01 02:42:59 PM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366429503 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1366
429503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3129092966
Short name T147
Test name
Test status
Simulation time 104484222 ps
CPU time 5.04 seconds
Started Sep 01 02:42:59 PM UTC 24
Finished Sep 01 02:43:05 PM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129092966 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3129092966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1854242948
Short name T139
Test name
Test status
Simulation time 1069772820 ps
CPU time 6.19 seconds
Started Sep 01 02:43:00 PM UTC 24
Finished Sep 01 02:43:07 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854242948 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1854242948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3241223579
Short name T786
Test name
Test status
Simulation time 76737285 ps
CPU time 3.91 seconds
Started Sep 01 02:44:11 PM UTC 24
Finished Sep 01 02:44:16 PM UTC 24
Peak memory 231700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3241223579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem
_rw_with_rand_reset.3241223579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2856555610
Short name T781
Test name
Test status
Simulation time 112373088 ps
CPU time 1.79 seconds
Started Sep 01 02:44:09 PM UTC 24
Finished Sep 01 02:44:11 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856555610 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2856555610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2086691517
Short name T780
Test name
Test status
Simulation time 26643615 ps
CPU time 1.32 seconds
Started Sep 01 02:44:09 PM UTC 24
Finished Sep 01 02:44:11 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086691517 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2086691517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.4053445764
Short name T787
Test name
Test status
Simulation time 112793128 ps
CPU time 3.88 seconds
Started Sep 01 02:44:11 PM UTC 24
Finished Sep 01 02:44:16 PM UTC 24
Peak memory 225480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053445764 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.4053445764 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2938611636
Short name T777
Test name
Test status
Simulation time 80898127 ps
CPU time 1.35 seconds
Started Sep 01 02:44:07 PM UTC 24
Finished Sep 01 02:44:10 PM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938611636 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.2938611636 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3373267202
Short name T117
Test name
Test status
Simulation time 147846370 ps
CPU time 3.42 seconds
Started Sep 01 02:44:07 PM UTC 24
Finished Sep 01 02:44:12 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373267202 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.337
3267202 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1293111179
Short name T782
Test name
Test status
Simulation time 163110033 ps
CPU time 3.47 seconds
Started Sep 01 02:44:09 PM UTC 24
Finished Sep 01 02:44:13 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293111179 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1293111179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1865155328
Short name T791
Test name
Test status
Simulation time 76657697 ps
CPU time 2.16 seconds
Started Sep 01 02:44:14 PM UTC 24
Finished Sep 01 02:44:18 PM UTC 24
Peak memory 229184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1865155328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem
_rw_with_rand_reset.1865155328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3576989561
Short name T785
Test name
Test status
Simulation time 119962282 ps
CPU time 1.42 seconds
Started Sep 01 02:44:13 PM UTC 24
Finished Sep 01 02:44:16 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576989561 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3576989561 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.518467426
Short name T784
Test name
Test status
Simulation time 17041133 ps
CPU time 1.26 seconds
Started Sep 01 02:44:12 PM UTC 24
Finished Sep 01 02:44:14 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518467426 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.518467426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2296421118
Short name T793
Test name
Test status
Simulation time 123190141 ps
CPU time 2.75 seconds
Started Sep 01 02:44:14 PM UTC 24
Finished Sep 01 02:44:19 PM UTC 24
Peak memory 224892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296421118 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.2296421118 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2475570230
Short name T783
Test name
Test status
Simulation time 77112523 ps
CPU time 1.56 seconds
Started Sep 01 02:44:11 PM UTC 24
Finished Sep 01 02:44:13 PM UTC 24
Peak memory 224432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475570230 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.2475570230 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.292685019
Short name T789
Test name
Test status
Simulation time 478150264 ps
CPU time 4.2 seconds
Started Sep 01 02:44:12 PM UTC 24
Finished Sep 01 02:44:17 PM UTC 24
Peak memory 230148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292685019 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.2926
85019 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.1451307019
Short name T790
Test name
Test status
Simulation time 180794969 ps
CPU time 4.66 seconds
Started Sep 01 02:44:12 PM UTC 24
Finished Sep 01 02:44:18 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451307019 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1451307019 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.327153319
Short name T788
Test name
Test status
Simulation time 464103269 ps
CPU time 3.55 seconds
Started Sep 01 02:44:12 PM UTC 24
Finished Sep 01 02:44:17 PM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327153319 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.327153319 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2654941911
Short name T800
Test name
Test status
Simulation time 20754929 ps
CPU time 2.41 seconds
Started Sep 01 02:44:19 PM UTC 24
Finished Sep 01 02:44:23 PM UTC 24
Peak memory 227640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2654941911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem
_rw_with_rand_reset.2654941911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3373114952
Short name T796
Test name
Test status
Simulation time 76232444 ps
CPU time 1.87 seconds
Started Sep 01 02:44:18 PM UTC 24
Finished Sep 01 02:44:21 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373114952 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3373114952 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2906447193
Short name T794
Test name
Test status
Simulation time 13641773 ps
CPU time 1.17 seconds
Started Sep 01 02:44:17 PM UTC 24
Finished Sep 01 02:44:19 PM UTC 24
Peak memory 224184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906447193 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2906447193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3156846444
Short name T799
Test name
Test status
Simulation time 161540250 ps
CPU time 2.93 seconds
Started Sep 01 02:44:18 PM UTC 24
Finished Sep 01 02:44:22 PM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156846444 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3156846444 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.253727285
Short name T792
Test name
Test status
Simulation time 136121881 ps
CPU time 1.92 seconds
Started Sep 01 02:44:15 PM UTC 24
Finished Sep 01 02:44:18 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253727285 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.253727285 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.872934663
Short name T798
Test name
Test status
Simulation time 151150705 ps
CPU time 3.81 seconds
Started Sep 01 02:44:16 PM UTC 24
Finished Sep 01 02:44:21 PM UTC 24
Peak memory 229988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872934663 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.8729
34663 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.4294511552
Short name T795
Test name
Test status
Simulation time 67056037 ps
CPU time 3.18 seconds
Started Sep 01 02:44:17 PM UTC 24
Finished Sep 01 02:44:21 PM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294511552 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.4294511552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1192960691
Short name T803
Test name
Test status
Simulation time 379503428 ps
CPU time 6.69 seconds
Started Sep 01 02:44:17 PM UTC 24
Finished Sep 01 02:44:24 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192960691 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1192960691 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1814588210
Short name T808
Test name
Test status
Simulation time 88838566 ps
CPU time 2.45 seconds
Started Sep 01 02:44:22 PM UTC 24
Finished Sep 01 02:44:26 PM UTC 24
Peak memory 227592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1814588210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem
_rw_with_rand_reset.1814588210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3853687540
Short name T801
Test name
Test status
Simulation time 19025436 ps
CPU time 1.43 seconds
Started Sep 01 02:44:21 PM UTC 24
Finished Sep 01 02:44:24 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853687540 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3853687540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3534930315
Short name T180
Test name
Test status
Simulation time 12502626 ps
CPU time 1.23 seconds
Started Sep 01 02:44:20 PM UTC 24
Finished Sep 01 02:44:23 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534930315 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3534930315 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3431060674
Short name T807
Test name
Test status
Simulation time 32244351 ps
CPU time 2.12 seconds
Started Sep 01 02:44:22 PM UTC 24
Finished Sep 01 02:44:26 PM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431060674 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3431060674 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2165588165
Short name T797
Test name
Test status
Simulation time 27286578 ps
CPU time 1.27 seconds
Started Sep 01 02:44:19 PM UTC 24
Finished Sep 01 02:44:21 PM UTC 24
Peak memory 224432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165588165 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.2165588165 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1170201102
Short name T802
Test name
Test status
Simulation time 89269554 ps
CPU time 2.56 seconds
Started Sep 01 02:44:20 PM UTC 24
Finished Sep 01 02:44:24 PM UTC 24
Peak memory 225572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170201102 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.117
0201102 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3514576860
Short name T805
Test name
Test status
Simulation time 301244827 ps
CPU time 3.77 seconds
Started Sep 01 02:44:20 PM UTC 24
Finished Sep 01 02:44:25 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514576860 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3514576860 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3819472776
Short name T804
Test name
Test status
Simulation time 198227187 ps
CPU time 3.56 seconds
Started Sep 01 02:44:20 PM UTC 24
Finished Sep 01 02:44:25 PM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819472776 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3819472776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2131483206
Short name T815
Test name
Test status
Simulation time 596562877 ps
CPU time 3.59 seconds
Started Sep 01 02:44:26 PM UTC 24
Finished Sep 01 02:44:30 PM UTC 24
Peak memory 231540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2131483206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem
_rw_with_rand_reset.2131483206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.3582220633
Short name T810
Test name
Test status
Simulation time 61425480 ps
CPU time 1.45 seconds
Started Sep 01 02:44:25 PM UTC 24
Finished Sep 01 02:44:27 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582220633 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3582220633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.598837659
Short name T809
Test name
Test status
Simulation time 15614145 ps
CPU time 1.23 seconds
Started Sep 01 02:44:25 PM UTC 24
Finished Sep 01 02:44:27 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598837659 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.598837659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2066475886
Short name T812
Test name
Test status
Simulation time 189838760 ps
CPU time 2.47 seconds
Started Sep 01 02:44:26 PM UTC 24
Finished Sep 01 02:44:29 PM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066475886 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2066475886 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4130073024
Short name T813
Test name
Test status
Simulation time 319388044 ps
CPU time 4.85 seconds
Started Sep 01 02:44:23 PM UTC 24
Finished Sep 01 02:44:29 PM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130073024 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.413
0073024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2315760387
Short name T814
Test name
Test status
Simulation time 159865334 ps
CPU time 5.6 seconds
Started Sep 01 02:44:23 PM UTC 24
Finished Sep 01 02:44:30 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315760387 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2315760387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.2080289709
Short name T811
Test name
Test status
Simulation time 383305211 ps
CPU time 4.48 seconds
Started Sep 01 02:44:24 PM UTC 24
Finished Sep 01 02:44:29 PM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080289709 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2080289709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1389574803
Short name T821
Test name
Test status
Simulation time 339987479 ps
CPU time 3.3 seconds
Started Sep 01 02:44:29 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 231820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1389574803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem
_rw_with_rand_reset.1389574803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.1068725455
Short name T817
Test name
Test status
Simulation time 40046561 ps
CPU time 1.44 seconds
Started Sep 01 02:44:28 PM UTC 24
Finished Sep 01 02:44:31 PM UTC 24
Peak memory 224416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068725455 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1068725455 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1549171824
Short name T816
Test name
Test status
Simulation time 60955747 ps
CPU time 1.29 seconds
Started Sep 01 02:44:28 PM UTC 24
Finished Sep 01 02:44:31 PM UTC 24
Peak memory 224780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549171824 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1549171824 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.50566602
Short name T819
Test name
Test status
Simulation time 209684351 ps
CPU time 2.94 seconds
Started Sep 01 02:44:28 PM UTC 24
Finished Sep 01 02:44:32 PM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50566602 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.50566602 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2266378079
Short name T120
Test name
Test status
Simulation time 88088592 ps
CPU time 1.32 seconds
Started Sep 01 02:44:26 PM UTC 24
Finished Sep 01 02:44:28 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266378079 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2266378079 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2141970997
Short name T818
Test name
Test status
Simulation time 98384637 ps
CPU time 3.51 seconds
Started Sep 01 02:44:27 PM UTC 24
Finished Sep 01 02:44:31 PM UTC 24
Peak memory 230000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141970997 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.214
1970997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.717912069
Short name T824
Test name
Test status
Simulation time 684055548 ps
CPU time 6.23 seconds
Started Sep 01 02:44:27 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 225432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717912069 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.717912069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3746739038
Short name T198
Test name
Test status
Simulation time 349321815 ps
CPU time 5.11 seconds
Started Sep 01 02:44:27 PM UTC 24
Finished Sep 01 02:44:33 PM UTC 24
Peak memory 225484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746739038 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3746739038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1743083244
Short name T826
Test name
Test status
Simulation time 75389169 ps
CPU time 1.72 seconds
Started Sep 01 02:44:32 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1743083244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem
_rw_with_rand_reset.1743083244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2809714636
Short name T823
Test name
Test status
Simulation time 56806596 ps
CPU time 1.4 seconds
Started Sep 01 02:44:32 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809714636 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2809714636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.716208111
Short name T822
Test name
Test status
Simulation time 14398043 ps
CPU time 1.25 seconds
Started Sep 01 02:44:32 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716208111 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.716208111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4224986917
Short name T829
Test name
Test status
Simulation time 142161151 ps
CPU time 3.58 seconds
Started Sep 01 02:44:32 PM UTC 24
Finished Sep 01 02:44:36 PM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224986917 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.4224986917 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.421917247
Short name T820
Test name
Test status
Simulation time 156749728 ps
CPU time 2.06 seconds
Started Sep 01 02:44:30 PM UTC 24
Finished Sep 01 02:44:33 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421917247 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.421917247 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2081805855
Short name T827
Test name
Test status
Simulation time 237109809 ps
CPU time 3.43 seconds
Started Sep 01 02:44:30 PM UTC 24
Finished Sep 01 02:44:35 PM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081805855 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.208
1805855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1239520312
Short name T825
Test name
Test status
Simulation time 203842217 ps
CPU time 2.78 seconds
Started Sep 01 02:44:30 PM UTC 24
Finished Sep 01 02:44:34 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239520312 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1239520312 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1786217878
Short name T196
Test name
Test status
Simulation time 358959323 ps
CPU time 5.95 seconds
Started Sep 01 02:44:32 PM UTC 24
Finished Sep 01 02:44:39 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786217878 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1786217878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1708843966
Short name T838
Test name
Test status
Simulation time 38278240 ps
CPU time 3.56 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:40 PM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1708843966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem
_rw_with_rand_reset.1708843966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.4033863521
Short name T833
Test name
Test status
Simulation time 98782016 ps
CPU time 1.8 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:38 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033863521 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4033863521 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.887158479
Short name T831
Test name
Test status
Simulation time 11708091 ps
CPU time 1.17 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:38 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887158479 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.887158479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3344905149
Short name T834
Test name
Test status
Simulation time 186545414 ps
CPU time 2.13 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:39 PM UTC 24
Peak memory 225524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344905149 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.3344905149 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4107516510
Short name T828
Test name
Test status
Simulation time 45096503 ps
CPU time 1.62 seconds
Started Sep 01 02:44:33 PM UTC 24
Finished Sep 01 02:44:36 PM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107516510 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.4107516510 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1239772844
Short name T830
Test name
Test status
Simulation time 64191133 ps
CPU time 2.16 seconds
Started Sep 01 02:44:33 PM UTC 24
Finished Sep 01 02:44:36 PM UTC 24
Peak memory 225908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239772844 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.123
9772844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2530363189
Short name T836
Test name
Test status
Simulation time 153740798 ps
CPU time 4.01 seconds
Started Sep 01 02:44:34 PM UTC 24
Finished Sep 01 02:44:39 PM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530363189 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2530363189 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.319027770
Short name T190
Test name
Test status
Simulation time 330532750 ps
CPU time 4.59 seconds
Started Sep 01 02:44:34 PM UTC 24
Finished Sep 01 02:44:40 PM UTC 24
Peak memory 225484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319027770 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.319027770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1830214414
Short name T844
Test name
Test status
Simulation time 40831987 ps
CPU time 2.31 seconds
Started Sep 01 02:44:39 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830214414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem
_rw_with_rand_reset.1830214414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.824670243
Short name T837
Test name
Test status
Simulation time 115338381 ps
CPU time 1.4 seconds
Started Sep 01 02:44:38 PM UTC 24
Finished Sep 01 02:44:40 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824670243 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.824670243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.544767171
Short name T835
Test name
Test status
Simulation time 29235893 ps
CPU time 1.12 seconds
Started Sep 01 02:44:36 PM UTC 24
Finished Sep 01 02:44:39 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544767171 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.544767171 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.88009672
Short name T842
Test name
Test status
Simulation time 70451145 ps
CPU time 2.61 seconds
Started Sep 01 02:44:38 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 225604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88009672 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.88009672 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1717540799
Short name T832
Test name
Test status
Simulation time 64732888 ps
CPU time 1.52 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:38 PM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717540799 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1717540799 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.44033818
Short name T839
Test name
Test status
Simulation time 481634229 ps
CPU time 3.84 seconds
Started Sep 01 02:44:35 PM UTC 24
Finished Sep 01 02:44:41 PM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44033818 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.44033
818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.767824814
Short name T840
Test name
Test status
Simulation time 206575739 ps
CPU time 3.2 seconds
Started Sep 01 02:44:36 PM UTC 24
Finished Sep 01 02:44:41 PM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767824814 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.767824814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.1737154501
Short name T843
Test name
Test status
Simulation time 438293096 ps
CPU time 4.31 seconds
Started Sep 01 02:44:36 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737154501 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.1737154501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3742456018
Short name T853
Test name
Test status
Simulation time 82578314 ps
CPU time 2.44 seconds
Started Sep 01 02:44:41 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3742456018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem
_rw_with_rand_reset.3742456018 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.182395256
Short name T847
Test name
Test status
Simulation time 39939009 ps
CPU time 1.77 seconds
Started Sep 01 02:44:40 PM UTC 24
Finished Sep 01 02:44:43 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182395256 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.182395256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.4069664448
Short name T845
Test name
Test status
Simulation time 24076883 ps
CPU time 1.28 seconds
Started Sep 01 02:44:40 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069664448 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.4069664448 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1680498474
Short name T855
Test name
Test status
Simulation time 497675947 ps
CPU time 2.69 seconds
Started Sep 01 02:44:41 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680498474 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1680498474 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3310258097
Short name T841
Test name
Test status
Simulation time 109171434 ps
CPU time 1.5 seconds
Started Sep 01 02:44:39 PM UTC 24
Finished Sep 01 02:44:41 PM UTC 24
Peak memory 224412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310258097 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3310258097 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2717141914
Short name T846
Test name
Test status
Simulation time 83760261 ps
CPU time 2.45 seconds
Started Sep 01 02:44:39 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 230024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717141914 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.271
7141914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.3592104022
Short name T854
Test name
Test status
Simulation time 340426423 ps
CPU time 3.66 seconds
Started Sep 01 02:44:40 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 225024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592104022 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3592104022 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1156874288
Short name T739
Test name
Test status
Simulation time 132018096 ps
CPU time 6.58 seconds
Started Sep 01 02:43:18 PM UTC 24
Finished Sep 01 02:43:26 PM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156874288 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1156874288 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1162609660
Short name T175
Test name
Test status
Simulation time 1317362681 ps
CPU time 30.05 seconds
Started Sep 01 02:43:17 PM UTC 24
Finished Sep 01 02:43:48 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162609660 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1162609660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1028887084
Short name T735
Test name
Test status
Simulation time 18647815 ps
CPU time 1.68 seconds
Started Sep 01 02:43:15 PM UTC 24
Finished Sep 01 02:43:18 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028887084 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1028887084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2196733417
Short name T155
Test name
Test status
Simulation time 65543291 ps
CPU time 2.12 seconds
Started Sep 01 02:43:20 PM UTC 24
Finished Sep 01 02:43:23 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2196733417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_
rw_with_rand_reset.2196733417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.4108831926
Short name T736
Test name
Test status
Simulation time 56067818 ps
CPU time 1.74 seconds
Started Sep 01 02:43:17 PM UTC 24
Finished Sep 01 02:43:20 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108831926 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.4108831926 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2739079139
Short name T158
Test name
Test status
Simulation time 18502829 ps
CPU time 1.82 seconds
Started Sep 01 02:43:11 PM UTC 24
Finished Sep 01 02:43:14 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739079139 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2739079139 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.1997580530
Short name T734
Test name
Test status
Simulation time 30801132 ps
CPU time 1.14 seconds
Started Sep 01 02:43:10 PM UTC 24
Finished Sep 01 02:43:12 PM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997580530 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1997580530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3178844559
Short name T167
Test name
Test status
Simulation time 404714708 ps
CPU time 4.36 seconds
Started Sep 01 02:43:18 PM UTC 24
Finished Sep 01 02:43:24 PM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178844559 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3178844559 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2451301292
Short name T119
Test name
Test status
Simulation time 45103996 ps
CPU time 2.1 seconds
Started Sep 01 02:43:08 PM UTC 24
Finished Sep 01 02:43:11 PM UTC 24
Peak memory 227956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451301292 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.2451301292 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2018910738
Short name T200
Test name
Test status
Simulation time 67115327 ps
CPU time 2.97 seconds
Started Sep 01 02:43:09 PM UTC 24
Finished Sep 01 02:43:13 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018910738 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2018
910738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.514041940
Short name T149
Test name
Test status
Simulation time 111024418 ps
CPU time 3.16 seconds
Started Sep 01 02:43:12 PM UTC 24
Finished Sep 01 02:43:16 PM UTC 24
Peak memory 225692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514041940 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.514041940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.3532429413
Short name T140
Test name
Test status
Simulation time 387460308 ps
CPU time 3.95 seconds
Started Sep 01 02:43:13 PM UTC 24
Finished Sep 01 02:43:18 PM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532429413 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.3532429413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4056962780
Short name T848
Test name
Test status
Simulation time 14387007 ps
CPU time 1.26 seconds
Started Sep 01 02:44:41 PM UTC 24
Finished Sep 01 02:44:43 PM UTC 24
Peak memory 224848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056962780 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4056962780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.3287124636
Short name T850
Test name
Test status
Simulation time 15880335 ps
CPU time 1.28 seconds
Started Sep 01 02:44:42 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287124636 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3287124636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3830346112
Short name T849
Test name
Test status
Simulation time 47918613 ps
CPU time 1.29 seconds
Started Sep 01 02:44:42 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830346112 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3830346112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2231572332
Short name T852
Test name
Test status
Simulation time 12002723 ps
CPU time 1.24 seconds
Started Sep 01 02:44:42 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231572332 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2231572332 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3300451515
Short name T851
Test name
Test status
Simulation time 41620831 ps
CPU time 1.18 seconds
Started Sep 01 02:44:42 PM UTC 24
Finished Sep 01 02:44:45 PM UTC 24
Peak memory 224972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300451515 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3300451515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1948461974
Short name T857
Test name
Test status
Simulation time 41704684 ps
CPU time 1.26 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948461974 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1948461974 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.120702984
Short name T856
Test name
Test status
Simulation time 34448337 ps
CPU time 1.21 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120702984 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.120702984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3560140537
Short name T858
Test name
Test status
Simulation time 13389747 ps
CPU time 1.27 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560140537 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3560140537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.73381786
Short name T859
Test name
Test status
Simulation time 34057803 ps
CPU time 1.21 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 225000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73381786 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.73381786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2999884672
Short name T860
Test name
Test status
Simulation time 14696815 ps
CPU time 1.23 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999884672 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2999884672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.2140003844
Short name T749
Test name
Test status
Simulation time 1727521658 ps
CPU time 12.18 seconds
Started Sep 01 02:43:29 PM UTC 24
Finished Sep 01 02:43:42 PM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140003844 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2140003844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.3350001007
Short name T172
Test name
Test status
Simulation time 1293533871 ps
CPU time 16.06 seconds
Started Sep 01 02:43:29 PM UTC 24
Finished Sep 01 02:43:46 PM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350001007 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3350001007 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1960611574
Short name T168
Test name
Test status
Simulation time 69603179 ps
CPU time 1.48 seconds
Started Sep 01 02:43:27 PM UTC 24
Finished Sep 01 02:43:29 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960611574 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1960611574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3677646121
Short name T744
Test name
Test status
Simulation time 212240979 ps
CPU time 2.68 seconds
Started Sep 01 02:43:30 PM UTC 24
Finished Sep 01 02:43:34 PM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3677646121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_
rw_with_rand_reset.3677646121 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.3784921036
Short name T741
Test name
Test status
Simulation time 59488555 ps
CPU time 1.48 seconds
Started Sep 01 02:43:27 PM UTC 24
Finished Sep 01 02:43:30 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784921036 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3784921036 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3477164177
Short name T183
Test name
Test status
Simulation time 20239492 ps
CPU time 1.22 seconds
Started Sep 01 02:43:26 PM UTC 24
Finished Sep 01 02:43:28 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477164177 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3477164177 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.4122733959
Short name T159
Test name
Test status
Simulation time 68333956 ps
CPU time 2.23 seconds
Started Sep 01 02:43:25 PM UTC 24
Finished Sep 01 02:43:28 PM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122733959 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.4122733959 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1245926358
Short name T740
Test name
Test status
Simulation time 11226005 ps
CPU time 1.16 seconds
Started Sep 01 02:43:24 PM UTC 24
Finished Sep 01 02:43:26 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245926358 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1245926358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.2456051885
Short name T169
Test name
Test status
Simulation time 61136021 ps
CPU time 2.61 seconds
Started Sep 01 02:43:30 PM UTC 24
Finished Sep 01 02:43:34 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456051885 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.2456051885 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.542518454
Short name T114
Test name
Test status
Simulation time 57719825 ps
CPU time 1.57 seconds
Started Sep 01 02:43:20 PM UTC 24
Finished Sep 01 02:43:23 PM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542518454 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.542518454 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.4017918169
Short name T137
Test name
Test status
Simulation time 48935751 ps
CPU time 2.44 seconds
Started Sep 01 02:43:21 PM UTC 24
Finished Sep 01 02:43:25 PM UTC 24
Peak memory 225572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017918169 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.4017
918169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1707475424
Short name T742
Test name
Test status
Simulation time 524074278 ps
CPU time 4.09 seconds
Started Sep 01 02:43:25 PM UTC 24
Finished Sep 01 02:43:30 PM UTC 24
Peak memory 225596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707475424 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1707475424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1497364929
Short name T861
Test name
Test status
Simulation time 44589213 ps
CPU time 1.22 seconds
Started Sep 01 02:44:44 PM UTC 24
Finished Sep 01 02:44:46 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497364929 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1497364929 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.143884702
Short name T862
Test name
Test status
Simulation time 30737867 ps
CPU time 1.17 seconds
Started Sep 01 02:44:45 PM UTC 24
Finished Sep 01 02:44:47 PM UTC 24
Peak memory 224844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143884702 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.143884702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1055361984
Short name T863
Test name
Test status
Simulation time 49404513 ps
CPU time 1.22 seconds
Started Sep 01 02:44:45 PM UTC 24
Finished Sep 01 02:44:47 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055361984 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1055361984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3978831323
Short name T864
Test name
Test status
Simulation time 28575463 ps
CPU time 1.21 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:48 PM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978831323 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3978831323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.2717761667
Short name T865
Test name
Test status
Simulation time 45698770 ps
CPU time 1.23 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:48 PM UTC 24
Peak memory 225268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717761667 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.2717761667 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.2180142238
Short name T866
Test name
Test status
Simulation time 40759151 ps
CPU time 1.27 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:48 PM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180142238 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2180142238 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.4208175450
Short name T867
Test name
Test status
Simulation time 48139310 ps
CPU time 1.27 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:48 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208175450 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.4208175450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1360371022
Short name T868
Test name
Test status
Simulation time 19060344 ps
CPU time 1.2 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:48 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360371022 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1360371022 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1265497847
Short name T869
Test name
Test status
Simulation time 48291550 ps
CPU time 1.29 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:49 PM UTC 24
Peak memory 224416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265497847 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1265497847 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1134290587
Short name T870
Test name
Test status
Simulation time 16783762 ps
CPU time 1.26 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:49 PM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134290587 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1134290587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1132506741
Short name T753
Test name
Test status
Simulation time 488918346 ps
CPU time 9.69 seconds
Started Sep 01 02:43:39 PM UTC 24
Finished Sep 01 02:43:50 PM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132506741 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1132506741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.2788269645
Short name T774
Test name
Test status
Simulation time 993868486 ps
CPU time 28.27 seconds
Started Sep 01 02:43:38 PM UTC 24
Finished Sep 01 02:44:07 PM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788269645 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.2788269645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2440903513
Short name T170
Test name
Test status
Simulation time 114541990 ps
CPU time 1.76 seconds
Started Sep 01 02:43:37 PM UTC 24
Finished Sep 01 02:43:39 PM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440903513 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2440903513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2728341932
Short name T750
Test name
Test status
Simulation time 312111876 ps
CPU time 2.8 seconds
Started Sep 01 02:43:40 PM UTC 24
Finished Sep 01 02:43:44 PM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2728341932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_
rw_with_rand_reset.2728341932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.4255181574
Short name T748
Test name
Test status
Simulation time 46032166 ps
CPU time 1.41 seconds
Started Sep 01 02:43:38 PM UTC 24
Finished Sep 01 02:43:40 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255181574 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4255181574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1660202575
Short name T182
Test name
Test status
Simulation time 40947310 ps
CPU time 1.22 seconds
Started Sep 01 02:43:36 PM UTC 24
Finished Sep 01 02:43:38 PM UTC 24
Peak memory 224964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660202575 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1660202575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.244543560
Short name T160
Test name
Test status
Simulation time 19370833 ps
CPU time 1.77 seconds
Started Sep 01 02:43:34 PM UTC 24
Finished Sep 01 02:43:37 PM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244543560 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.244543560 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3257279922
Short name T745
Test name
Test status
Simulation time 20977979 ps
CPU time 1.15 seconds
Started Sep 01 02:43:32 PM UTC 24
Finished Sep 01 02:43:35 PM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257279922 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3257279922 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2296823076
Short name T171
Test name
Test status
Simulation time 382160971 ps
CPU time 3.95 seconds
Started Sep 01 02:43:39 PM UTC 24
Finished Sep 01 02:43:44 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296823076 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.2296823076 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.930759309
Short name T743
Test name
Test status
Simulation time 92684422 ps
CPU time 1.61 seconds
Started Sep 01 02:43:31 PM UTC 24
Finished Sep 01 02:43:34 PM UTC 24
Peak memory 224436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930759309 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.930759309 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.162882509
Short name T746
Test name
Test status
Simulation time 59066076 ps
CPU time 2.37 seconds
Started Sep 01 02:43:32 PM UTC 24
Finished Sep 01 02:43:36 PM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162882509 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.16288
2509 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.778836087
Short name T747
Test name
Test status
Simulation time 302256860 ps
CPU time 3.94 seconds
Started Sep 01 02:43:34 PM UTC 24
Finished Sep 01 02:43:39 PM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778836087 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.778836087 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.3986814303
Short name T192
Test name
Test status
Simulation time 83905287 ps
CPU time 2.92 seconds
Started Sep 01 02:43:35 PM UTC 24
Finished Sep 01 02:43:38 PM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986814303 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.3986814303 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.455851045
Short name T871
Test name
Test status
Simulation time 39201603 ps
CPU time 1.23 seconds
Started Sep 01 02:44:46 PM UTC 24
Finished Sep 01 02:44:49 PM UTC 24
Peak memory 224612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455851045 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.455851045 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.4143567465
Short name T873
Test name
Test status
Simulation time 18733442 ps
CPU time 1.24 seconds
Started Sep 01 02:44:47 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143567465 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.4143567465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.833072496
Short name T872
Test name
Test status
Simulation time 21523681 ps
CPU time 1.17 seconds
Started Sep 01 02:44:47 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833072496 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.833072496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4109754331
Short name T874
Test name
Test status
Simulation time 43950949 ps
CPU time 1.27 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109754331 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4109754331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.372415620
Short name T875
Test name
Test status
Simulation time 31766212 ps
CPU time 1.2 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372415620 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.372415620 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.130359483
Short name T876
Test name
Test status
Simulation time 56104376 ps
CPU time 1.3 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130359483 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.130359483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3293047852
Short name T877
Test name
Test status
Simulation time 14351152 ps
CPU time 1.26 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293047852 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3293047852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3142998529
Short name T878
Test name
Test status
Simulation time 45051602 ps
CPU time 1.23 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142998529 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3142998529 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.570991329
Short name T879
Test name
Test status
Simulation time 23782670 ps
CPU time 1.22 seconds
Started Sep 01 02:44:48 PM UTC 24
Finished Sep 01 02:44:50 PM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570991329 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.570991329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2543102656
Short name T880
Test name
Test status
Simulation time 42042542 ps
CPU time 1.23 seconds
Started Sep 01 02:44:49 PM UTC 24
Finished Sep 01 02:44:51 PM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543102656 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2543102656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3103412493
Short name T754
Test name
Test status
Simulation time 74734269 ps
CPU time 2.67 seconds
Started Sep 01 02:43:47 PM UTC 24
Finished Sep 01 02:43:51 PM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3103412493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_
rw_with_rand_reset.3103412493 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1760074205
Short name T174
Test name
Test status
Simulation time 31960846 ps
CPU time 1.55 seconds
Started Sep 01 02:43:44 PM UTC 24
Finished Sep 01 02:43:47 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760074205 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1760074205 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1658396099
Short name T181
Test name
Test status
Simulation time 19482607 ps
CPU time 1.18 seconds
Started Sep 01 02:43:44 PM UTC 24
Finished Sep 01 02:43:46 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658396099 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1658396099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1839421734
Short name T752
Test name
Test status
Simulation time 49147685 ps
CPU time 2.44 seconds
Started Sep 01 02:43:45 PM UTC 24
Finished Sep 01 02:43:49 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839421734 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1839421734 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1966318250
Short name T121
Test name
Test status
Simulation time 62854437 ps
CPU time 2.93 seconds
Started Sep 01 02:43:41 PM UTC 24
Finished Sep 01 02:43:45 PM UTC 24
Peak memory 230132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966318250 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.1966
318250 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1192438948
Short name T751
Test name
Test status
Simulation time 54044334 ps
CPU time 3.04 seconds
Started Sep 01 02:43:43 PM UTC 24
Finished Sep 01 02:43:47 PM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192438948 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1192438948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.1298077207
Short name T188
Test name
Test status
Simulation time 261285723 ps
CPU time 8.08 seconds
Started Sep 01 02:43:43 PM UTC 24
Finished Sep 01 02:43:52 PM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298077207 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1298077207 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3133801622
Short name T758
Test name
Test status
Simulation time 97381733 ps
CPU time 2.77 seconds
Started Sep 01 02:43:52 PM UTC 24
Finished Sep 01 02:43:56 PM UTC 24
Peak memory 231692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3133801622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_
rw_with_rand_reset.3133801622 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3744469499
Short name T756
Test name
Test status
Simulation time 105758526 ps
CPU time 1.52 seconds
Started Sep 01 02:43:51 PM UTC 24
Finished Sep 01 02:43:53 PM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744469499 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3744469499 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.2693174023
Short name T179
Test name
Test status
Simulation time 15870139 ps
CPU time 1.21 seconds
Started Sep 01 02:43:50 PM UTC 24
Finished Sep 01 02:43:52 PM UTC 24
Peak memory 224700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693174023 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2693174023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.142411371
Short name T759
Test name
Test status
Simulation time 1885996021 ps
CPU time 4.2 seconds
Started Sep 01 02:43:51 PM UTC 24
Finished Sep 01 02:43:56 PM UTC 24
Peak memory 225448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142411371 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.142411371 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1550792952
Short name T118
Test name
Test status
Simulation time 55130909 ps
CPU time 2 seconds
Started Sep 01 02:43:48 PM UTC 24
Finished Sep 01 02:43:50 PM UTC 24
Peak memory 226428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550792952 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1550792952 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.842658547
Short name T755
Test name
Test status
Simulation time 163338584 ps
CPU time 2.99 seconds
Started Sep 01 02:43:48 PM UTC 24
Finished Sep 01 02:43:52 PM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842658547 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.84265
8547 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.625195966
Short name T757
Test name
Test status
Simulation time 1425700263 ps
CPU time 4.32 seconds
Started Sep 01 02:43:49 PM UTC 24
Finished Sep 01 02:43:54 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625195966 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.625195966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.3140136168
Short name T197
Test name
Test status
Simulation time 509891551 ps
CPU time 3.22 seconds
Started Sep 01 02:43:50 PM UTC 24
Finished Sep 01 02:43:54 PM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140136168 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.3140136168 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3785181165
Short name T765
Test name
Test status
Simulation time 39814296 ps
CPU time 3.49 seconds
Started Sep 01 02:43:56 PM UTC 24
Finished Sep 01 02:44:01 PM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3785181165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_
rw_with_rand_reset.3785181165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1758369263
Short name T761
Test name
Test status
Simulation time 30605340 ps
CPU time 1.75 seconds
Started Sep 01 02:43:55 PM UTC 24
Finished Sep 01 02:43:58 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758369263 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1758369263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.863204090
Short name T143
Test name
Test status
Simulation time 10674373 ps
CPU time 1.21 seconds
Started Sep 01 02:43:55 PM UTC 24
Finished Sep 01 02:43:57 PM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863204090 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.863204090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3287695544
Short name T763
Test name
Test status
Simulation time 105604217 ps
CPU time 2.67 seconds
Started Sep 01 02:43:55 PM UTC 24
Finished Sep 01 02:43:59 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287695544 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3287695544 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1250737131
Short name T116
Test name
Test status
Simulation time 92161354 ps
CPU time 1.69 seconds
Started Sep 01 02:43:52 PM UTC 24
Finished Sep 01 02:43:55 PM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250737131 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1250737131 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.985635382
Short name T122
Test name
Test status
Simulation time 174225436 ps
CPU time 2.48 seconds
Started Sep 01 02:43:53 PM UTC 24
Finished Sep 01 02:43:57 PM UTC 24
Peak memory 225196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985635382 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.98563
5382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2886854935
Short name T760
Test name
Test status
Simulation time 43275703 ps
CPU time 3.71 seconds
Started Sep 01 02:43:53 PM UTC 24
Finished Sep 01 02:43:58 PM UTC 24
Peak memory 225720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886854935 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2886854935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2875325038
Short name T194
Test name
Test status
Simulation time 260452769 ps
CPU time 5.76 seconds
Started Sep 01 02:43:54 PM UTC 24
Finished Sep 01 02:44:01 PM UTC 24
Peak memory 225560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875325038 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.2875325038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1641450883
Short name T772
Test name
Test status
Simulation time 339483282 ps
CPU time 4.02 seconds
Started Sep 01 02:44:02 PM UTC 24
Finished Sep 01 02:44:07 PM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1641450883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_
rw_with_rand_reset.1641450883 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2986627928
Short name T767
Test name
Test status
Simulation time 24873208 ps
CPU time 1.38 seconds
Started Sep 01 02:44:00 PM UTC 24
Finished Sep 01 02:44:02 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986627928 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2986627928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3489939786
Short name T764
Test name
Test status
Simulation time 42501308 ps
CPU time 1.22 seconds
Started Sep 01 02:43:59 PM UTC 24
Finished Sep 01 02:44:01 PM UTC 24
Peak memory 224964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489939786 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3489939786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2867070496
Short name T768
Test name
Test status
Simulation time 343380554 ps
CPU time 2.41 seconds
Started Sep 01 02:44:00 PM UTC 24
Finished Sep 01 02:44:03 PM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867070496 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.2867070496 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2343424807
Short name T762
Test name
Test status
Simulation time 31858568 ps
CPU time 1.45 seconds
Started Sep 01 02:43:56 PM UTC 24
Finished Sep 01 02:43:59 PM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343424807 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.2343424807 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.386717179
Short name T766
Test name
Test status
Simulation time 245257869 ps
CPU time 2.95 seconds
Started Sep 01 02:43:58 PM UTC 24
Finished Sep 01 02:44:01 PM UTC 24
Peak memory 225832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386717179 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.38671
7179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2061377463
Short name T769
Test name
Test status
Simulation time 869312026 ps
CPU time 5.14 seconds
Started Sep 01 02:43:59 PM UTC 24
Finished Sep 01 02:44:05 PM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061377463 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2061377463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.761316089
Short name T189
Test name
Test status
Simulation time 675494006 ps
CPU time 7.05 seconds
Started Sep 01 02:43:59 PM UTC 24
Finished Sep 01 02:44:07 PM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761316089 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.761316089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4239525649
Short name T779
Test name
Test status
Simulation time 28852336 ps
CPU time 2.39 seconds
Started Sep 01 02:44:07 PM UTC 24
Finished Sep 01 02:44:11 PM UTC 24
Peak memory 227604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4239525649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_
rw_with_rand_reset.4239525649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1434915179
Short name T775
Test name
Test status
Simulation time 22033430 ps
CPU time 1.56 seconds
Started Sep 01 02:44:05 PM UTC 24
Finished Sep 01 02:44:08 PM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434915179 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1434915179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.3625950066
Short name T771
Test name
Test status
Simulation time 16570374 ps
CPU time 1.18 seconds
Started Sep 01 02:44:04 PM UTC 24
Finished Sep 01 02:44:06 PM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625950066 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3625950066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3318524970
Short name T778
Test name
Test status
Simulation time 151064929 ps
CPU time 3.52 seconds
Started Sep 01 02:44:05 PM UTC 24
Finished Sep 01 02:44:10 PM UTC 24
Peak memory 225532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318524970 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3318524970 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.353618631
Short name T770
Test name
Test status
Simulation time 49706258 ps
CPU time 1.92 seconds
Started Sep 01 02:44:02 PM UTC 24
Finished Sep 01 02:44:05 PM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353618631 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.353618631 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1804471516
Short name T773
Test name
Test status
Simulation time 121536089 ps
CPU time 4.24 seconds
Started Sep 01 02:44:02 PM UTC 24
Finished Sep 01 02:44:07 PM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804471516 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.1804
471516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3090829124
Short name T776
Test name
Test status
Simulation time 213136256 ps
CPU time 4.86 seconds
Started Sep 01 02:44:02 PM UTC 24
Finished Sep 01 02:44:08 PM UTC 24
Peak memory 225620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090829124 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3090829124 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_app.3327996678
Short name T30
Test name
Test status
Simulation time 4431493463 ps
CPU time 303.84 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:52:21 PM UTC 24
Peak memory 317980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327996678 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3327996678 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1800054701
Short name T29
Test name
Test status
Simulation time 16161869497 ps
CPU time 352.98 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:53:10 PM UTC 24
Peak memory 471696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800054701 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1800054701 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.794181042
Short name T357
Test name
Test status
Simulation time 19851124887 ps
CPU time 1002.35 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 02:04:01 PM UTC 24
Peak memory 260312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794181042 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.794181042 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3165872828
Short name T95
Test name
Test status
Simulation time 65999248999 ps
CPU time 191.39 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:50:27 PM UTC 24
Peak memory 281140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165872828 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3165872828 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.1870045337
Short name T7
Test name
Test status
Simulation time 5126109582 ps
CPU time 8.23 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:47:22 PM UTC 24
Peak memory 230088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870045337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.1870045337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.2952996690
Short name T710
Test name
Test status
Simulation time 182114587083 ps
CPU time 4619.32 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 03:04:55 PM UTC 24
Peak memory 4335860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952996690 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.2952996690 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.1107013348
Short name T77
Test name
Test status
Simulation time 5268026329 ps
CPU time 189.6 seconds
Started Sep 01 01:47:12 PM UTC 24
Finished Sep 01 01:50:25 PM UTC 24
Peak memory 351084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107013348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1107013348 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.3918342969
Short name T39
Test name
Test status
Simulation time 9920977619 ps
CPU time 41.97 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:57 PM UTC 24
Peak memory 278340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918342969 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3918342969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.3354657274
Short name T27
Test name
Test status
Simulation time 52014226674 ps
CPU time 400.27 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 01:53:51 PM UTC 24
Peak memory 573956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354657274 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3354657274 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.4139871857
Short name T91
Test name
Test status
Simulation time 6082307371 ps
CPU time 50.58 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 01:47:58 PM UTC 24
Peak memory 235900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139871857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.4139871857 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.2556211675
Short name T65
Test name
Test status
Simulation time 1101112304 ps
CPU time 45.32 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:48:01 PM UTC 24
Peak memory 252536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2556211675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r
and_reset.2556211675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.2602681958
Short name T2
Test name
Test status
Simulation time 91196830 ps
CPU time 2.15 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:47:12 PM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602681958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.2602681958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.2026258520
Short name T1
Test name
Test status
Simulation time 204501546 ps
CPU time 2.17 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:47:12 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026258520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2026258520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.3820898792
Short name T607
Test name
Test status
Simulation time 94350976162 ps
CPU time 2881.27 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 02:35:39 PM UTC 24
Peak memory 3121448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820898792 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3820898792 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.1432408863
Short name T61
Test name
Test status
Simulation time 11353710573 ps
CPU time 35.49 seconds
Started Sep 01 01:47:06 PM UTC 24
Finished Sep 01 01:47:43 PM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432408863 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1432408863 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3307419467
Short name T44
Test name
Test status
Simulation time 1363344164 ps
CPU time 17.99 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:47:28 PM UTC 24
Peak memory 234156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307419467 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3307419467 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.201759788
Short name T231
Test name
Test status
Simulation time 87582990542 ps
CPU time 340.97 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:52:55 PM UTC 24
Peak memory 285184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201759788 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.201759788 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1795830307
Short name T202
Test name
Test status
Simulation time 5547467673 ps
CPU time 148.72 seconds
Started Sep 01 01:47:09 PM UTC 24
Finished Sep 01 01:49:41 PM UTC 24
Peak memory 362948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795830307 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1795830307 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.3619478404
Short name T109
Test name
Test status
Simulation time 18586150 ps
CPU time 0.73 seconds
Started Sep 01 01:47:20 PM UTC 24
Finished Sep 01 01:47:21 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619478404 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3619478404 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_app.4014040741
Short name T28
Test name
Test status
Simulation time 74423546755 ps
CPU time 300.5 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:52:19 PM UTC 24
Peak memory 473604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014040741 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4014040741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1376449718
Short name T13
Test name
Test status
Simulation time 3168065662 ps
CPU time 52.41 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:48:09 PM UTC 24
Peak memory 268836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376449718 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1376449718 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.771025232
Short name T58
Test name
Test status
Simulation time 11325348680 ps
CPU time 193.06 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:50:30 PM UTC 24
Peak memory 248404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771025232 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.771025232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.4101216538
Short name T48
Test name
Test status
Simulation time 35406920 ps
CPU time 1.14 seconds
Started Sep 01 01:47:15 PM UTC 24
Finished Sep 01 01:47:18 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101216538 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.4101216538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2808461572
Short name T50
Test name
Test status
Simulation time 482512579 ps
CPU time 1.14 seconds
Started Sep 01 01:47:16 PM UTC 24
Finished Sep 01 01:47:19 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808461572 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2808461572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.2233630869
Short name T5
Test name
Test status
Simulation time 4825449001 ps
CPU time 11.93 seconds
Started Sep 01 01:47:16 PM UTC 24
Finished Sep 01 01:47:30 PM UTC 24
Peak memory 232208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233630869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2233630869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.58673695
Short name T447
Test name
Test status
Simulation time 50185913969 ps
CPU time 1585.6 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 02:13:57 PM UTC 24
Peak memory 2226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58673695 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.58673695 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.3962317962
Short name T80
Test name
Test status
Simulation time 8659471778 ps
CPU time 259.78 seconds
Started Sep 01 01:47:15 PM UTC 24
Finished Sep 01 01:51:39 PM UTC 24
Peak memory 443232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962317962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3962317962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.2373880921
Short name T247
Test name
Test status
Simulation time 29128863833 ps
CPU time 443.25 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:54:43 PM UTC 24
Peak memory 615000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373880921 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2373880921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.1767528252
Short name T313
Test name
Test status
Simulation time 45010860498 ps
CPU time 724.39 seconds
Started Sep 01 01:47:17 PM UTC 24
Finished Sep 01 01:59:32 PM UTC 24
Peak memory 510836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767528252 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1767528252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.3172842432
Short name T66
Test name
Test status
Simulation time 25222892740 ps
CPU time 171.14 seconds
Started Sep 01 01:47:18 PM UTC 24
Finished Sep 01 01:50:13 PM UTC 24
Peak memory 265152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3172842432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r
and_reset.3172842432 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3932295972
Short name T17
Test name
Test status
Simulation time 323183521 ps
CPU time 2.4 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:18 PM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932295972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3932295972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.3211979999
Short name T514
Test name
Test status
Simulation time 63802908895 ps
CPU time 2170.03 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 02:23:47 PM UTC 24
Peak memory 3111356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211979999 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3211979999 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.1592616056
Short name T605
Test name
Test status
Simulation time 88206491414 ps
CPU time 2864.93 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 02:35:31 PM UTC 24
Peak memory 3047788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592616056 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1592616056 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1285897643
Short name T102
Test name
Test status
Simulation time 6446785629 ps
CPU time 26.73 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:42 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285897643 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1285897643 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.202173477
Short name T45
Test name
Test status
Simulation time 928322881 ps
CPU time 14.94 seconds
Started Sep 01 01:47:14 PM UTC 24
Finished Sep 01 01:47:30 PM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202173477 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.202173477 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.1467782991
Short name T255
Test name
Test status
Simulation time 72419357 ps
CPU time 1.34 seconds
Started Sep 01 01:55:28 PM UTC 24
Finished Sep 01 01:55:30 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467782991 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.1467782991 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_app.1108201133
Short name T259
Test name
Test status
Simulation time 1600337221 ps
CPU time 48.81 seconds
Started Sep 01 01:54:55 PM UTC 24
Finished Sep 01 01:55:45 PM UTC 24
Peak memory 250284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108201133 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1108201133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.3291471973
Short name T161
Test name
Test status
Simulation time 1729867369 ps
CPU time 154.17 seconds
Started Sep 01 01:54:44 PM UTC 24
Finished Sep 01 01:57:21 PM UTC 24
Peak memory 235992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291471973 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3291471973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.2191114851
Short name T251
Test name
Test status
Simulation time 114788326 ps
CPU time 1.55 seconds
Started Sep 01 01:55:20 PM UTC 24
Finished Sep 01 01:55:23 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191114851 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2191114851 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.3543207708
Short name T253
Test name
Test status
Simulation time 72311285 ps
CPU time 1.57 seconds
Started Sep 01 01:55:23 PM UTC 24
Finished Sep 01 01:55:26 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543207708 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3543207708 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.2027059178
Short name T250
Test name
Test status
Simulation time 2627485901 ps
CPU time 10.25 seconds
Started Sep 01 01:55:08 PM UTC 24
Finished Sep 01 01:55:20 PM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027059178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2027059178 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2011014413
Short name T340
Test name
Test status
Simulation time 5119604308 ps
CPU time 470.71 seconds
Started Sep 01 01:54:36 PM UTC 24
Finished Sep 01 02:02:33 PM UTC 24
Peak memory 529000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011014413 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2011014413 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.2231618967
Short name T283
Test name
Test status
Simulation time 5970975928 ps
CPU time 165.71 seconds
Started Sep 01 01:54:39 PM UTC 24
Finished Sep 01 01:57:27 PM UTC 24
Peak memory 363104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231618967 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2231618967 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.4163173336
Short name T258
Test name
Test status
Simulation time 7369820475 ps
CPU time 67.09 seconds
Started Sep 01 01:54:35 PM UTC 24
Finished Sep 01 01:55:43 PM UTC 24
Peak memory 234240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163173336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4163173336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.2425848024
Short name T128
Test name
Test status
Simulation time 39965007041 ps
CPU time 1163.39 seconds
Started Sep 01 01:55:27 PM UTC 24
Finished Sep 01 02:15:05 PM UTC 24
Peak memory 1088172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425848024 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.2425848024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.2296429424
Short name T264
Test name
Test status
Simulation time 20938154 ps
CPU time 1.31 seconds
Started Sep 01 01:55:55 PM UTC 24
Finished Sep 01 01:55:57 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296429424 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2296429424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_app.4094839500
Short name T265
Test name
Test status
Simulation time 1559799910 ps
CPU time 22.18 seconds
Started Sep 01 01:55:38 PM UTC 24
Finished Sep 01 01:56:02 PM UTC 24
Peak memory 235988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094839500 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.4094839500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.94761156
Short name T165
Test name
Test status
Simulation time 7435940796 ps
CPU time 362.96 seconds
Started Sep 01 01:55:34 PM UTC 24
Finished Sep 01 02:01:42 PM UTC 24
Peak memory 252524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94761156 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.94761156 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.2334978646
Short name T268
Test name
Test status
Simulation time 4645085995 ps
CPU time 45.84 seconds
Started Sep 01 01:55:46 PM UTC 24
Finished Sep 01 01:56:34 PM UTC 24
Peak memory 235984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334978646 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2334978646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2982550921
Short name T263
Test name
Test status
Simulation time 193049015 ps
CPU time 4.73 seconds
Started Sep 01 01:55:49 PM UTC 24
Finished Sep 01 01:55:54 PM UTC 24
Peak memory 231932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982550921 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2982550921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.149361435
Short name T296
Test name
Test status
Simulation time 22509202533 ps
CPU time 151.23 seconds
Started Sep 01 01:55:39 PM UTC 24
Finished Sep 01 01:58:13 PM UTC 24
Peak memory 332388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149361435 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.149361435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_error.2477213362
Short name T307
Test name
Test status
Simulation time 2099590167 ps
CPU time 202.83 seconds
Started Sep 01 01:55:40 PM UTC 24
Finished Sep 01 01:59:07 PM UTC 24
Peak memory 291300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477213362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2477213362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.2573871731
Short name T262
Test name
Test status
Simulation time 1956582861 ps
CPU time 6.15 seconds
Started Sep 01 01:55:44 PM UTC 24
Finished Sep 01 01:55:52 PM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573871731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2573871731 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.3395323844
Short name T720
Test name
Test status
Simulation time 256740186055 ps
CPU time 5763.52 seconds
Started Sep 01 01:55:31 PM UTC 24
Finished Sep 01 03:32:42 PM UTC 24
Peak memory 4674176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395323844 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3395323844 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.866801519
Short name T287
Test name
Test status
Simulation time 22031641399 ps
CPU time 127.8 seconds
Started Sep 01 01:55:34 PM UTC 24
Finished Sep 01 01:57:44 PM UTC 24
Peak memory 338512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866801519 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.866801519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.3046148384
Short name T270
Test name
Test status
Simulation time 1102651835 ps
CPU time 43.02 seconds
Started Sep 01 01:55:53 PM UTC 24
Finished Sep 01 01:56:37 PM UTC 24
Peak memory 260900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046148384 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3046148384 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.1428691253
Short name T273
Test name
Test status
Simulation time 58317079 ps
CPU time 1.29 seconds
Started Sep 01 01:56:43 PM UTC 24
Finished Sep 01 01:56:46 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428691253 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1428691253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2507762847
Short name T354
Test name
Test status
Simulation time 5292508408 ps
CPU time 447.71 seconds
Started Sep 01 01:56:10 PM UTC 24
Finished Sep 01 02:03:44 PM UTC 24
Peak memory 360980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507762847 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2507762847 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.1694910280
Short name T416
Test name
Test status
Simulation time 30756623948 ps
CPU time 891.67 seconds
Started Sep 01 01:56:07 PM UTC 24
Finished Sep 01 02:11:10 PM UTC 24
Peak memory 248424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694910280 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1694910280 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.2721029652
Short name T274
Test name
Test status
Simulation time 1516878296 ps
CPU time 9.54 seconds
Started Sep 01 01:56:36 PM UTC 24
Finished Sep 01 01:56:46 PM UTC 24
Peak memory 234012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721029652 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2721029652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.149968819
Short name T277
Test name
Test status
Simulation time 2132578693 ps
CPU time 27.82 seconds
Started Sep 01 01:56:38 PM UTC 24
Finished Sep 01 01:57:07 PM UTC 24
Peak memory 235864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149968819 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.149968819 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.225440651
Short name T325
Test name
Test status
Simulation time 37346994475 ps
CPU time 257.78 seconds
Started Sep 01 01:56:11 PM UTC 24
Finished Sep 01 02:00:33 PM UTC 24
Peak memory 389660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225440651 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.225440651 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_error.1091864682
Short name T333
Test name
Test status
Simulation time 3679210519 ps
CPU time 315.14 seconds
Started Sep 01 01:56:13 PM UTC 24
Finished Sep 01 02:01:33 PM UTC 24
Peak memory 334356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091864682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1091864682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3826988587
Short name T272
Test name
Test status
Simulation time 392233548 ps
CPU time 6.5 seconds
Started Sep 01 01:56:35 PM UTC 24
Finished Sep 01 01:56:42 PM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826988587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3826988587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2749127858
Short name T426
Test name
Test status
Simulation time 44748556543 ps
CPU time 967.44 seconds
Started Sep 01 01:55:58 PM UTC 24
Finished Sep 01 02:12:17 PM UTC 24
Peak memory 680476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749127858 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2749127858 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.570296568
Short name T353
Test name
Test status
Simulation time 32217144126 ps
CPU time 453.48 seconds
Started Sep 01 01:56:02 PM UTC 24
Finished Sep 01 02:03:41 PM UTC 24
Peak memory 578140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570296568 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.570296568 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2851184141
Short name T256
Test name
Test status
Simulation time 346572289 ps
CPU time 16.77 seconds
Started Sep 01 01:55:55 PM UTC 24
Finished Sep 01 01:56:13 PM UTC 24
Peak memory 234176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851184141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2851184141 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.2806823823
Short name T524
Test name
Test status
Simulation time 149428974652 ps
CPU time 1668.86 seconds
Started Sep 01 01:56:42 PM UTC 24
Finished Sep 01 02:24:50 PM UTC 24
Peak memory 513000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806823823 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.2806823823 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.919409513
Short name T282
Test name
Test status
Simulation time 44309859 ps
CPU time 1.23 seconds
Started Sep 01 01:57:24 PM UTC 24
Finished Sep 01 01:57:26 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919409513 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.919409513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_app.4208548632
Short name T278
Test name
Test status
Simulation time 1118738188 ps
CPU time 13.62 seconds
Started Sep 01 01:56:57 PM UTC 24
Finished Sep 01 01:57:12 PM UTC 24
Peak memory 249800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208548632 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.4208548632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.1107960949
Short name T384
Test name
Test status
Simulation time 21875098044 ps
CPU time 626.94 seconds
Started Sep 01 01:56:48 PM UTC 24
Finished Sep 01 02:07:24 PM UTC 24
Peak memory 252484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107960949 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1107960949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.245913435
Short name T280
Test name
Test status
Simulation time 29116008 ps
CPU time 1.67 seconds
Started Sep 01 01:57:18 PM UTC 24
Finished Sep 01 01:57:21 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245913435 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.245913435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1775695743
Short name T281
Test name
Test status
Simulation time 100499718 ps
CPU time 1.69 seconds
Started Sep 01 01:57:21 PM UTC 24
Finished Sep 01 01:57:24 PM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775695743 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1775695743 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.1680976077
Short name T310
Test name
Test status
Simulation time 20685635409 ps
CPU time 136.57 seconds
Started Sep 01 01:56:58 PM UTC 24
Finished Sep 01 01:59:17 PM UTC 24
Peak memory 303136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680976077 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1680976077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_error.579559619
Short name T288
Test name
Test status
Simulation time 446129749 ps
CPU time 39.06 seconds
Started Sep 01 01:57:08 PM UTC 24
Finished Sep 01 01:57:48 PM UTC 24
Peak memory 252392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579559619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.579559619 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.402119403
Short name T279
Test name
Test status
Simulation time 407124015 ps
CPU time 2.22 seconds
Started Sep 01 01:57:14 PM UTC 24
Finished Sep 01 01:57:17 PM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402119403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.402119403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.3055123162
Short name T75
Test name
Test status
Simulation time 41555200 ps
CPU time 1.52 seconds
Started Sep 01 01:57:21 PM UTC 24
Finished Sep 01 01:57:23 PM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055123162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3055123162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.2658408789
Short name T511
Test name
Test status
Simulation time 29860921095 ps
CPU time 1583.37 seconds
Started Sep 01 01:56:46 PM UTC 24
Finished Sep 01 02:23:30 PM UTC 24
Peak memory 1081892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658408789 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.2658408789 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.2388483639
Short name T326
Test name
Test status
Simulation time 16330622065 ps
CPU time 223.99 seconds
Started Sep 01 01:56:47 PM UTC 24
Finished Sep 01 02:00:35 PM UTC 24
Peak memory 313892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388483639 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2388483639 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.3194485861
Short name T290
Test name
Test status
Simulation time 2559154880 ps
CPU time 65.22 seconds
Started Sep 01 01:56:45 PM UTC 24
Finished Sep 01 01:57:52 PM UTC 24
Peak memory 236160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194485861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3194485861 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.2798408831
Short name T377
Test name
Test status
Simulation time 9683940273 ps
CPU time 540.48 seconds
Started Sep 01 01:57:24 PM UTC 24
Finished Sep 01 02:06:32 PM UTC 24
Peak memory 295536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798408831 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2798408831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.2440094239
Short name T294
Test name
Test status
Simulation time 17691997 ps
CPU time 1.25 seconds
Started Sep 01 01:57:59 PM UTC 24
Finished Sep 01 01:58:02 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440094239 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2440094239 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_app.3219023372
Short name T348
Test name
Test status
Simulation time 21027295803 ps
CPU time 326.07 seconds
Started Sep 01 01:57:34 PM UTC 24
Finished Sep 01 02:03:05 PM UTC 24
Peak memory 434788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219023372 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3219023372 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.1549662729
Short name T365
Test name
Test status
Simulation time 12575376046 ps
CPU time 442.43 seconds
Started Sep 01 01:57:29 PM UTC 24
Finished Sep 01 02:04:58 PM UTC 24
Peak memory 248552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549662729 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1549662729 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2347919493
Short name T289
Test name
Test status
Simulation time 266716238 ps
CPU time 1.79 seconds
Started Sep 01 01:57:49 PM UTC 24
Finished Sep 01 01:57:52 PM UTC 24
Peak memory 227704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347919493 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2347919493 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1801337985
Short name T291
Test name
Test status
Simulation time 33404394 ps
CPU time 1.76 seconds
Started Sep 01 01:57:53 PM UTC 24
Finished Sep 01 01:57:56 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801337985 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1801337985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3266623916
Short name T320
Test name
Test status
Simulation time 29112547034 ps
CPU time 140.34 seconds
Started Sep 01 01:57:36 PM UTC 24
Finished Sep 01 01:59:59 PM UTC 24
Peak memory 322212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266623916 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3266623916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_error.3748454272
Short name T322
Test name
Test status
Simulation time 2005961274 ps
CPU time 143.6 seconds
Started Sep 01 01:57:43 PM UTC 24
Finished Sep 01 02:00:09 PM UTC 24
Peak memory 299504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748454272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.3748454272 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.1241391512
Short name T293
Test name
Test status
Simulation time 911776686 ps
CPU time 12.45 seconds
Started Sep 01 01:57:45 PM UTC 24
Finished Sep 01 01:57:58 PM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241391512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1241391512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.990554089
Short name T297
Test name
Test status
Simulation time 913943600 ps
CPU time 19.9 seconds
Started Sep 01 01:57:53 PM UTC 24
Finished Sep 01 01:58:14 PM UTC 24
Peak memory 252404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990554089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.990554089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.4080337497
Short name T680
Test name
Test status
Simulation time 516224995762 ps
CPU time 2948.66 seconds
Started Sep 01 01:57:27 PM UTC 24
Finished Sep 01 02:47:10 PM UTC 24
Peak memory 2867944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080337497 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.4080337497 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.3633810623
Short name T305
Test name
Test status
Simulation time 1150066558 ps
CPU time 78.64 seconds
Started Sep 01 01:57:28 PM UTC 24
Finished Sep 01 01:58:49 PM UTC 24
Peak memory 258528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633810623 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.3633810623 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.1877428366
Short name T286
Test name
Test status
Simulation time 2193613559 ps
CPU time 16.04 seconds
Started Sep 01 01:57:25 PM UTC 24
Finished Sep 01 01:57:42 PM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877428366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1877428366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.1543542253
Short name T295
Test name
Test status
Simulation time 228881943 ps
CPU time 7.84 seconds
Started Sep 01 01:57:56 PM UTC 24
Finished Sep 01 01:58:05 PM UTC 24
Peak memory 246228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543542253 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.1543542253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.85458369
Short name T306
Test name
Test status
Simulation time 124718862 ps
CPU time 1.27 seconds
Started Sep 01 01:58:48 PM UTC 24
Finished Sep 01 01:58:51 PM UTC 24
Peak memory 226596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85458369 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.85458369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_app.3510116147
Short name T342
Test name
Test status
Simulation time 24976511118 ps
CPU time 256.73 seconds
Started Sep 01 01:58:16 PM UTC 24
Finished Sep 01 02:02:37 PM UTC 24
Peak memory 373328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510116147 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3510116147 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.2687731736
Short name T164
Test name
Test status
Simulation time 3899942174 ps
CPU time 166.62 seconds
Started Sep 01 01:58:14 PM UTC 24
Finished Sep 01 02:01:04 PM UTC 24
Peak memory 238180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687731736 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2687731736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1452031142
Short name T308
Test name
Test status
Simulation time 318154830 ps
CPU time 29.73 seconds
Started Sep 01 01:58:38 PM UTC 24
Finished Sep 01 01:59:09 PM UTC 24
Peak memory 250156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452031142 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1452031142 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.1112973815
Short name T311
Test name
Test status
Simulation time 1341201065 ps
CPU time 44.99 seconds
Started Sep 01 01:58:39 PM UTC 24
Finished Sep 01 01:59:26 PM UTC 24
Peak memory 234532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112973815 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1112973815 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3356854066
Short name T324
Test name
Test status
Simulation time 5861120446 ps
CPU time 114.38 seconds
Started Sep 01 01:58:24 PM UTC 24
Finished Sep 01 02:00:21 PM UTC 24
Peak memory 301636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356854066 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3356854066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_error.2743433569
Short name T350
Test name
Test status
Simulation time 13784843972 ps
CPU time 282.9 seconds
Started Sep 01 01:58:25 PM UTC 24
Finished Sep 01 02:03:13 PM UTC 24
Peak memory 328364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743433569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2743433569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.1739503520
Short name T302
Test name
Test status
Simulation time 209735757 ps
CPU time 3.83 seconds
Started Sep 01 01:58:33 PM UTC 24
Finished Sep 01 01:58:38 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739503520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1739503520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.168030473
Short name T304
Test name
Test status
Simulation time 204606504 ps
CPU time 2.2 seconds
Started Sep 01 01:58:40 PM UTC 24
Finished Sep 01 01:58:43 PM UTC 24
Peak memory 232052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168030473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.168030473 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.956132292
Short name T387
Test name
Test status
Simulation time 58903902833 ps
CPU time 577.9 seconds
Started Sep 01 01:58:02 PM UTC 24
Finished Sep 01 02:07:48 PM UTC 24
Peak memory 913960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956132292 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.956132292 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.3153902448
Short name T355
Test name
Test status
Simulation time 6717754418 ps
CPU time 340.66 seconds
Started Sep 01 01:58:06 PM UTC 24
Finished Sep 01 02:03:52 PM UTC 24
Peak memory 328280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153902448 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3153902448 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.3753564077
Short name T300
Test name
Test status
Simulation time 2503298002 ps
CPU time 31.06 seconds
Started Sep 01 01:57:59 PM UTC 24
Finished Sep 01 01:58:32 PM UTC 24
Peak memory 236144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753564077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3753564077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.3932998832
Short name T434
Test name
Test status
Simulation time 271927630516 ps
CPU time 825.85 seconds
Started Sep 01 01:58:44 PM UTC 24
Finished Sep 01 02:12:40 PM UTC 24
Peak memory 416736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932998832 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3932998832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.3861636144
Short name T318
Test name
Test status
Simulation time 45377473 ps
CPU time 1.24 seconds
Started Sep 01 01:59:46 PM UTC 24
Finished Sep 01 01:59:48 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861636144 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.3861636144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_app.1428679763
Short name T367
Test name
Test status
Simulation time 15948949713 ps
CPU time 354.09 seconds
Started Sep 01 01:59:16 PM UTC 24
Finished Sep 01 02:05:15 PM UTC 24
Peak memory 334508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428679763 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.1428679763 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.3489516446
Short name T390
Test name
Test status
Simulation time 10968689151 ps
CPU time 523.64 seconds
Started Sep 01 01:59:10 PM UTC 24
Finished Sep 01 02:08:00 PM UTC 24
Peak memory 248416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489516446 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3489516446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2625830306
Short name T316
Test name
Test status
Simulation time 931480505 ps
CPU time 10.64 seconds
Started Sep 01 01:59:32 PM UTC 24
Finished Sep 01 01:59:44 PM UTC 24
Peak memory 235824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625830306 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2625830306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.3711214971
Short name T315
Test name
Test status
Simulation time 20847477 ps
CPU time 1.45 seconds
Started Sep 01 01:59:38 PM UTC 24
Finished Sep 01 01:59:41 PM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711214971 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3711214971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.172547092
Short name T347
Test name
Test status
Simulation time 16612546743 ps
CPU time 220.53 seconds
Started Sep 01 01:59:18 PM UTC 24
Finished Sep 01 02:03:02 PM UTC 24
Peak memory 309860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172547092 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.172547092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_error.180557212
Short name T385
Test name
Test status
Simulation time 15695489114 ps
CPU time 474.81 seconds
Started Sep 01 01:59:26 PM UTC 24
Finished Sep 01 02:07:27 PM UTC 24
Peak memory 563872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180557212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.180557212 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.2119583079
Short name T314
Test name
Test status
Simulation time 860561345 ps
CPU time 6.41 seconds
Started Sep 01 01:59:30 PM UTC 24
Finished Sep 01 01:59:38 PM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119583079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2119583079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.3303844807
Short name T317
Test name
Test status
Simulation time 46631959 ps
CPU time 2.12 seconds
Started Sep 01 01:59:41 PM UTC 24
Finished Sep 01 01:59:45 PM UTC 24
Peak memory 232028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303844807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3303844807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3316951005
Short name T699
Test name
Test status
Simulation time 92743499022 ps
CPU time 3450.37 seconds
Started Sep 01 01:58:52 PM UTC 24
Finished Sep 01 02:57:00 PM UTC 24
Peak memory 3414576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316951005 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3316951005 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.2795622783
Short name T312
Test name
Test status
Simulation time 575250150 ps
CPU time 20.1 seconds
Started Sep 01 01:59:08 PM UTC 24
Finished Sep 01 01:59:29 PM UTC 24
Peak memory 240036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795622783 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2795622783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.3724253569
Short name T309
Test name
Test status
Simulation time 935759835 ps
CPU time 23.92 seconds
Started Sep 01 01:58:50 PM UTC 24
Finished Sep 01 01:59:15 PM UTC 24
Peak memory 234176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724253569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3724253569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.4228249685
Short name T530
Test name
Test status
Simulation time 35538536589 ps
CPU time 1519.85 seconds
Started Sep 01 01:59:46 PM UTC 24
Finished Sep 01 02:25:24 PM UTC 24
Peak memory 398256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228249685 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.4228249685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.881986174
Short name T330
Test name
Test status
Simulation time 31485884 ps
CPU time 1.17 seconds
Started Sep 01 02:00:44 PM UTC 24
Finished Sep 01 02:00:46 PM UTC 24
Peak memory 226660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881986174 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.881986174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_app.1860224478
Short name T334
Test name
Test status
Simulation time 6148536320 ps
CPU time 85.21 seconds
Started Sep 01 02:00:10 PM UTC 24
Finished Sep 01 02:01:38 PM UTC 24
Peak memory 281196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860224478 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1860224478 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.3974053239
Short name T361
Test name
Test status
Simulation time 3372912781 ps
CPU time 263.48 seconds
Started Sep 01 02:00:01 PM UTC 24
Finished Sep 01 02:04:32 PM UTC 24
Peak memory 240172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974053239 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3974053239 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.66480040
Short name T332
Test name
Test status
Simulation time 1128097260 ps
CPU time 45.59 seconds
Started Sep 01 02:00:33 PM UTC 24
Finished Sep 01 02:01:21 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66480040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +
UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.66480040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.298221496
Short name T327
Test name
Test status
Simulation time 59431596 ps
CPU time 1.66 seconds
Started Sep 01 02:00:36 PM UTC 24
Finished Sep 01 02:00:39 PM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298221496 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.298221496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.539872011
Short name T343
Test name
Test status
Simulation time 4170252513 ps
CPU time 136.14 seconds
Started Sep 01 02:00:20 PM UTC 24
Finished Sep 01 02:02:39 PM UTC 24
Peak memory 309868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539872011 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.539872011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_error.3819534078
Short name T405
Test name
Test status
Simulation time 5529045897 ps
CPU time 543.43 seconds
Started Sep 01 02:00:21 PM UTC 24
Finished Sep 01 02:09:32 PM UTC 24
Peak memory 391780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819534078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.3819534078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.758428120
Short name T328
Test name
Test status
Simulation time 3218001822 ps
CPU time 19.74 seconds
Started Sep 01 02:00:21 PM UTC 24
Finished Sep 01 02:00:42 PM UTC 24
Peak memory 228068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758428120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.758428120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.3679239502
Short name T329
Test name
Test status
Simulation time 86253140 ps
CPU time 2.11 seconds
Started Sep 01 02:00:40 PM UTC 24
Finished Sep 01 02:00:43 PM UTC 24
Peak memory 232056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679239502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.3679239502 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.1104045386
Short name T617
Test name
Test status
Simulation time 73067765233 ps
CPU time 2224.7 seconds
Started Sep 01 01:59:51 PM UTC 24
Finished Sep 01 02:37:23 PM UTC 24
Peak memory 1165924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104045386 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.1104045386 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.1739999820
Short name T368
Test name
Test status
Simulation time 3491289291 ps
CPU time 314.12 seconds
Started Sep 01 02:00:00 PM UTC 24
Finished Sep 01 02:05:19 PM UTC 24
Peak memory 336488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739999820 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1739999820 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.3135712640
Short name T323
Test name
Test status
Simulation time 3455744400 ps
CPU time 28.4 seconds
Started Sep 01 01:59:49 PM UTC 24
Finished Sep 01 02:00:19 PM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135712640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3135712640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.2006728781
Short name T534
Test name
Test status
Simulation time 168219469840 ps
CPU time 1508.62 seconds
Started Sep 01 02:00:43 PM UTC 24
Finished Sep 01 02:26:10 PM UTC 24
Peak memory 1203032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006728781 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2006728781 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.1875515987
Short name T338
Test name
Test status
Simulation time 31107853 ps
CPU time 1.26 seconds
Started Sep 01 02:01:52 PM UTC 24
Finished Sep 01 02:01:54 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875515987 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1875515987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_app.679565634
Short name T388
Test name
Test status
Simulation time 5261703958 ps
CPU time 402.22 seconds
Started Sep 01 02:01:05 PM UTC 24
Finished Sep 01 02:07:53 PM UTC 24
Peak memory 338472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679565634 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.679565634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.1360178297
Short name T461
Test name
Test status
Simulation time 84112673387 ps
CPU time 976.33 seconds
Started Sep 01 02:01:04 PM UTC 24
Finished Sep 01 02:17:33 PM UTC 24
Peak memory 262692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360178297 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1360178297 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.3526508403
Short name T335
Test name
Test status
Simulation time 22657748 ps
CPU time 1.58 seconds
Started Sep 01 02:01:44 PM UTC 24
Finished Sep 01 02:01:47 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526508403 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3526508403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2118360426
Short name T336
Test name
Test status
Simulation time 41982039 ps
CPU time 1.3 seconds
Started Sep 01 02:01:45 PM UTC 24
Finished Sep 01 02:01:47 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118360426 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2118360426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.2175227462
Short name T100
Test name
Test status
Simulation time 7154722093 ps
CPU time 175.62 seconds
Started Sep 01 02:01:22 PM UTC 24
Finished Sep 01 02:04:20 PM UTC 24
Peak memory 356960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175227462 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.2175227462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_error.2440483959
Short name T410
Test name
Test status
Simulation time 29632965685 ps
CPU time 492.64 seconds
Started Sep 01 02:01:35 PM UTC 24
Finished Sep 01 02:09:54 PM UTC 24
Peak memory 602732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440483959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2440483959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2935119648
Short name T337
Test name
Test status
Simulation time 1364520097 ps
CPU time 11.31 seconds
Started Sep 01 02:01:39 PM UTC 24
Finished Sep 01 02:01:51 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935119648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2935119648 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.2973841509
Short name T339
Test name
Test status
Simulation time 1155475185 ps
CPU time 9.59 seconds
Started Sep 01 02:01:47 PM UTC 24
Finished Sep 01 02:01:58 PM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973841509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2973841509 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1084706316
Short name T344
Test name
Test status
Simulation time 2921750188 ps
CPU time 108.5 seconds
Started Sep 01 02:01:04 PM UTC 24
Finished Sep 01 02:02:55 PM UTC 24
Peak memory 322048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084706316 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1084706316 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.2354813119
Short name T398
Test name
Test status
Simulation time 103724296746 ps
CPU time 471.19 seconds
Started Sep 01 02:01:04 PM UTC 24
Finished Sep 01 02:09:02 PM UTC 24
Peak memory 500268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354813119 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2354813119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.3806909055
Short name T345
Test name
Test status
Simulation time 34674503161 ps
CPU time 127.03 seconds
Started Sep 01 02:00:47 PM UTC 24
Finished Sep 01 02:02:56 PM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806909055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3806909055 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.1720847166
Short name T375
Test name
Test status
Simulation time 63962093107 ps
CPU time 271.99 seconds
Started Sep 01 02:01:48 PM UTC 24
Finished Sep 01 02:06:24 PM UTC 24
Peak memory 396220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720847166 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.1720847166 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.2679361409
Short name T351
Test name
Test status
Simulation time 21061063 ps
CPU time 1.28 seconds
Started Sep 01 02:03:11 PM UTC 24
Finished Sep 01 02:03:13 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679361409 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2679361409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_app.236625795
Short name T381
Test name
Test status
Simulation time 16074300999 ps
CPU time 256.13 seconds
Started Sep 01 02:02:38 PM UTC 24
Finished Sep 01 02:06:58 PM UTC 24
Peak memory 293476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236625795 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.236625795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.2458955999
Short name T505
Test name
Test status
Simulation time 52086313047 ps
CPU time 1202.9 seconds
Started Sep 01 02:02:36 PM UTC 24
Finished Sep 01 02:22:53 PM UTC 24
Peak memory 268964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458955999 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2458955999 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1057739181
Short name T352
Test name
Test status
Simulation time 344029296 ps
CPU time 12.28 seconds
Started Sep 01 02:03:01 PM UTC 24
Finished Sep 01 02:03:15 PM UTC 24
Peak memory 246108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057739181 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1057739181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.1478800160
Short name T349
Test name
Test status
Simulation time 97966222 ps
CPU time 1.5 seconds
Started Sep 01 02:03:02 PM UTC 24
Finished Sep 01 02:03:05 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478800160 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1478800160 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1625683426
Short name T399
Test name
Test status
Simulation time 63676020676 ps
CPU time 381.05 seconds
Started Sep 01 02:02:40 PM UTC 24
Finished Sep 01 02:09:07 PM UTC 24
Peak memory 315996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625683426 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1625683426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2858875546
Short name T417
Test name
Test status
Simulation time 62592958455 ps
CPU time 496.56 seconds
Started Sep 01 02:02:56 PM UTC 24
Finished Sep 01 02:11:19 PM UTC 24
Peak memory 541252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858875546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2858875546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.2661693796
Short name T346
Test name
Test status
Simulation time 242564684 ps
CPU time 2.71 seconds
Started Sep 01 02:02:57 PM UTC 24
Finished Sep 01 02:03:01 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661693796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2661693796 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3818063772
Short name T636
Test name
Test status
Simulation time 56955101979 ps
CPU time 2231.95 seconds
Started Sep 01 02:01:58 PM UTC 24
Finished Sep 01 02:39:36 PM UTC 24
Peak memory 2411108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818063772 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3818063772 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.1542807315
Short name T373
Test name
Test status
Simulation time 7409650532 ps
CPU time 205.49 seconds
Started Sep 01 02:02:34 PM UTC 24
Finished Sep 01 02:06:03 PM UTC 24
Peak memory 381484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542807315 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1542807315 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.2887183139
Short name T341
Test name
Test status
Simulation time 5251199010 ps
CPU time 38.03 seconds
Started Sep 01 02:01:55 PM UTC 24
Finished Sep 01 02:02:35 PM UTC 24
Peak memory 234216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887183139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2887183139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.3231552894
Short name T376
Test name
Test status
Simulation time 16628594392 ps
CPU time 202.1 seconds
Started Sep 01 02:03:06 PM UTC 24
Finished Sep 01 02:06:31 PM UTC 24
Peak memory 295924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231552894 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3231552894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.2609768938
Short name T123
Test name
Test status
Simulation time 12758647 ps
CPU time 1.14 seconds
Started Sep 01 01:47:31 PM UTC 24
Finished Sep 01 01:47:33 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609768938 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2609768938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_app.2075605724
Short name T89
Test name
Test status
Simulation time 47932071538 ps
CPU time 121.99 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:49:33 PM UTC 24
Peak memory 307808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075605724 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2075605724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.1230205954
Short name T209
Test name
Test status
Simulation time 8105124842 ps
CPU time 348.19 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:53:21 PM UTC 24
Peak memory 324112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230205954 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1230205954 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.3318387322
Short name T166
Test name
Test status
Simulation time 14727506810 ps
CPU time 850.65 seconds
Started Sep 01 01:47:23 PM UTC 24
Finished Sep 01 02:01:44 PM UTC 24
Peak memory 258656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318387322 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3318387322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2359392422
Short name T23
Test name
Test status
Simulation time 2808390520 ps
CPU time 23.51 seconds
Started Sep 01 01:47:29 PM UTC 24
Finished Sep 01 01:47:53 PM UTC 24
Peak memory 235900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359392422 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2359392422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3541432817
Short name T54
Test name
Test status
Simulation time 106101441 ps
CPU time 1.06 seconds
Started Sep 01 01:47:30 PM UTC 24
Finished Sep 01 01:47:32 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541432817 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3541432817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.839994296
Short name T186
Test name
Test status
Simulation time 26315614592 ps
CPU time 108.8 seconds
Started Sep 01 01:47:30 PM UTC 24
Finished Sep 01 01:49:21 PM UTC 24
Peak memory 236064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839994296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.839994296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.1060314703
Short name T104
Test name
Test status
Simulation time 74962723496 ps
CPU time 393.37 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:54:08 PM UTC 24
Peak memory 455188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060314703 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1060314703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.1548209339
Short name T18
Test name
Test status
Simulation time 5185300274 ps
CPU time 10.7 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:47:40 PM UTC 24
Peak memory 230056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548209339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.1548209339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.1737036554
Short name T19
Test name
Test status
Simulation time 62285049 ps
CPU time 1.62 seconds
Started Sep 01 01:47:30 PM UTC 24
Finished Sep 01 01:47:32 PM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737036554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1737036554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3168776217
Short name T701
Test name
Test status
Simulation time 397001707145 ps
CPU time 4181.22 seconds
Started Sep 01 01:47:20 PM UTC 24
Finished Sep 01 02:57:46 PM UTC 24
Peak memory 4152020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168776217 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3168776217 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.541872410
Short name T14
Test name
Test status
Simulation time 2881504472 ps
CPU time 86.68 seconds
Started Sep 01 01:47:28 PM UTC 24
Finished Sep 01 01:48:57 PM UTC 24
Peak memory 260880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541872410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.541872410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.1957230054
Short name T41
Test name
Test status
Simulation time 20225295582 ps
CPU time 105.05 seconds
Started Sep 01 01:47:31 PM UTC 24
Finished Sep 01 01:49:18 PM UTC 24
Peak memory 290636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957230054 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1957230054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.3989975050
Short name T25
Test name
Test status
Simulation time 6017506693 ps
CPU time 207.6 seconds
Started Sep 01 01:47:22 PM UTC 24
Finished Sep 01 01:50:53 PM UTC 24
Peak memory 303660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989975050 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3989975050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.2318584625
Short name T60
Test name
Test status
Simulation time 1394154657 ps
CPU time 24.37 seconds
Started Sep 01 01:47:20 PM UTC 24
Finished Sep 01 01:47:45 PM UTC 24
Peak memory 236008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318584625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2318584625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.3669392163
Short name T107
Test name
Test status
Simulation time 207442780100 ps
CPU time 1546.06 seconds
Started Sep 01 01:47:30 PM UTC 24
Finished Sep 01 02:13:34 PM UTC 24
Peak memory 797748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669392163 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3669392163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3920790685
Short name T52
Test name
Test status
Simulation time 105591416 ps
CPU time 2.42 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 01:47:27 PM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920790685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3920790685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.3563816576
Short name T51
Test name
Test status
Simulation time 171820699 ps
CPU time 2.16 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 01:47:27 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563816576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3563816576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.3100700872
Short name T638
Test name
Test status
Simulation time 96275683622 ps
CPU time 3113.27 seconds
Started Sep 01 01:47:23 PM UTC 24
Finished Sep 01 02:39:51 PM UTC 24
Peak memory 3140032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100700872 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.3100700872 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.3039950947
Short name T136
Test name
Test status
Simulation time 1992484692 ps
CPU time 39.75 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 01:48:05 PM UTC 24
Peak memory 256404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039950947 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3039950947 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.2180324719
Short name T90
Test name
Test status
Simulation time 12314321669 ps
CPU time 31.67 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 01:47:57 PM UTC 24
Peak memory 242196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180324719 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2180324719 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1306940869
Short name T438
Test name
Test status
Simulation time 270774848788 ps
CPU time 1535.34 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 02:13:17 PM UTC 24
Peak memory 1714632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306940869 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1306940869 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3466668913
Short name T207
Test name
Test status
Simulation time 14889171435 ps
CPU time 229.72 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 01:51:17 PM UTC 24
Peak memory 285200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466668913 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3466668913 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.3235446550
Short name T473
Test name
Test status
Simulation time 186664665944 ps
CPU time 1875.98 seconds
Started Sep 01 01:47:24 PM UTC 24
Finished Sep 01 02:19:01 PM UTC 24
Peak memory 1120716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235446550 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.3235446550 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.659257611
Short name T360
Test name
Test status
Simulation time 14471206 ps
CPU time 1.25 seconds
Started Sep 01 02:04:21 PM UTC 24
Finished Sep 01 02:04:23 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659257611 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.659257611 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_app.330414941
Short name T374
Test name
Test status
Simulation time 21164426146 ps
CPU time 151.17 seconds
Started Sep 01 02:03:45 PM UTC 24
Finished Sep 01 02:06:19 PM UTC 24
Peak memory 328212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330414941 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.330414941 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.4173075146
Short name T404
Test name
Test status
Simulation time 12003029152 ps
CPU time 342.7 seconds
Started Sep 01 02:03:42 PM UTC 24
Finished Sep 01 02:09:30 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173075146 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4173075146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.4224694049
Short name T396
Test name
Test status
Simulation time 9826004595 ps
CPU time 276.55 seconds
Started Sep 01 02:03:53 PM UTC 24
Finished Sep 01 02:08:34 PM UTC 24
Peak memory 318036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224694049 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4224694049 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_error.717976679
Short name T366
Test name
Test status
Simulation time 12893997153 ps
CPU time 74.07 seconds
Started Sep 01 02:03:56 PM UTC 24
Finished Sep 01 02:05:12 PM UTC 24
Peak memory 313868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717976679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.717976679 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.869351445
Short name T358
Test name
Test status
Simulation time 4972358223 ps
CPU time 10.24 seconds
Started Sep 01 02:04:01 PM UTC 24
Finished Sep 01 02:04:13 PM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869351445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.869351445 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.120447930
Short name T73
Test name
Test status
Simulation time 44912273 ps
CPU time 1.9 seconds
Started Sep 01 02:04:14 PM UTC 24
Finished Sep 01 02:04:16 PM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120447930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.120447930 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3648293248
Short name T561
Test name
Test status
Simulation time 75141418744 ps
CPU time 1539.49 seconds
Started Sep 01 02:03:14 PM UTC 24
Finished Sep 01 02:29:13 PM UTC 24
Peak memory 889452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648293248 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3648293248 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.2055696772
Short name T428
Test name
Test status
Simulation time 12725595833 ps
CPU time 544.3 seconds
Started Sep 01 02:03:16 PM UTC 24
Finished Sep 01 02:12:28 PM UTC 24
Peak memory 545380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055696772 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2055696772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.2065546540
Short name T359
Test name
Test status
Simulation time 1743850883 ps
CPU time 64.44 seconds
Started Sep 01 02:03:14 PM UTC 24
Finished Sep 01 02:04:20 PM UTC 24
Peak memory 235980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065546540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2065546540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.3687704002
Short name T498
Test name
Test status
Simulation time 27102987970 ps
CPU time 1038.07 seconds
Started Sep 01 02:04:18 PM UTC 24
Finished Sep 01 02:21:49 PM UTC 24
Peak memory 596604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687704002 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3687704002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.3239765684
Short name T371
Test name
Test status
Simulation time 13507324 ps
CPU time 1.27 seconds
Started Sep 01 02:05:30 PM UTC 24
Finished Sep 01 02:05:32 PM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239765684 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3239765684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_app.2455165697
Short name T393
Test name
Test status
Simulation time 22657142323 ps
CPU time 190.98 seconds
Started Sep 01 02:04:53 PM UTC 24
Finished Sep 01 02:08:07 PM UTC 24
Peak memory 352868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455165697 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2455165697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.1323646100
Short name T485
Test name
Test status
Simulation time 81666067713 ps
CPU time 930.79 seconds
Started Sep 01 02:04:51 PM UTC 24
Finished Sep 01 02:20:33 PM UTC 24
Peak memory 260716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323646100 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1323646100 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2961952540
Short name T429
Test name
Test status
Simulation time 35873224293 ps
CPU time 445.54 seconds
Started Sep 01 02:04:58 PM UTC 24
Finished Sep 01 02:12:30 PM UTC 24
Peak memory 522980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961952540 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2961952540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_error.2959337187
Short name T414
Test name
Test status
Simulation time 15352912863 ps
CPU time 333.66 seconds
Started Sep 01 02:04:58 PM UTC 24
Finished Sep 01 02:10:37 PM UTC 24
Peak memory 348720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959337187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2959337187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2642599985
Short name T369
Test name
Test status
Simulation time 1954022449 ps
CPU time 13.88 seconds
Started Sep 01 02:05:14 PM UTC 24
Finished Sep 01 02:05:29 PM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642599985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2642599985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.3750682383
Short name T370
Test name
Test status
Simulation time 443789344 ps
CPU time 12.58 seconds
Started Sep 01 02:05:16 PM UTC 24
Finished Sep 01 02:05:30 PM UTC 24
Peak memory 244912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750682383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3750682383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.2244013926
Short name T643
Test name
Test status
Simulation time 192191220561 ps
CPU time 2138.91 seconds
Started Sep 01 02:04:24 PM UTC 24
Finished Sep 01 02:40:27 PM UTC 24
Peak memory 2462312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244013926 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.2244013926 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.1265102365
Short name T403
Test name
Test status
Simulation time 3216594844 ps
CPU time 291.27 seconds
Started Sep 01 02:04:33 PM UTC 24
Finished Sep 01 02:09:29 PM UTC 24
Peak memory 320092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265102365 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1265102365 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.1921471734
Short name T362
Test name
Test status
Simulation time 3050848439 ps
CPU time 28.33 seconds
Started Sep 01 02:04:21 PM UTC 24
Finished Sep 01 02:04:50 PM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921471734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1921471734 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.24103204
Short name T470
Test name
Test status
Simulation time 19466859607 ps
CPU time 795.44 seconds
Started Sep 01 02:05:20 PM UTC 24
Finished Sep 01 02:18:45 PM UTC 24
Peak memory 586368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24103204 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.24103204 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.3457089979
Short name T380
Test name
Test status
Simulation time 15778477 ps
CPU time 1.3 seconds
Started Sep 01 02:06:55 PM UTC 24
Finished Sep 01 02:06:58 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457089979 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3457089979 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_app.2060793812
Short name T418
Test name
Test status
Simulation time 17229121530 ps
CPU time 307.32 seconds
Started Sep 01 02:06:21 PM UTC 24
Finished Sep 01 02:11:32 PM UTC 24
Peak memory 465456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060793812 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.2060793812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1836843377
Short name T481
Test name
Test status
Simulation time 148607238160 ps
CPU time 818.23 seconds
Started Sep 01 02:06:03 PM UTC 24
Finished Sep 01 02:19:52 PM UTC 24
Peak memory 254572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836843377 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1836843377 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.3334230217
Short name T394
Test name
Test status
Simulation time 3160740507 ps
CPU time 106.88 seconds
Started Sep 01 02:06:26 PM UTC 24
Finished Sep 01 02:08:15 PM UTC 24
Peak memory 291392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334230217 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3334230217 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2951273295
Short name T421
Test name
Test status
Simulation time 9343039157 ps
CPU time 304.02 seconds
Started Sep 01 02:06:32 PM UTC 24
Finished Sep 01 02:11:40 PM UTC 24
Peak memory 477804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951273295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2951273295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.2772717222
Short name T379
Test name
Test status
Simulation time 4503609340 ps
CPU time 20.01 seconds
Started Sep 01 02:06:33 PM UTC 24
Finished Sep 01 02:06:54 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772717222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.2772717222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.1798459675
Short name T68
Test name
Test status
Simulation time 37741790 ps
CPU time 2.29 seconds
Started Sep 01 02:06:39 PM UTC 24
Finished Sep 01 02:06:42 PM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798459675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1798459675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.4119451674
Short name T707
Test name
Test status
Simulation time 27383690987 ps
CPU time 3367.57 seconds
Started Sep 01 02:05:33 PM UTC 24
Finished Sep 01 03:02:20 PM UTC 24
Peak memory 1833520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119451674 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.4119451674 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.2399774816
Short name T441
Test name
Test status
Simulation time 10417299342 ps
CPU time 460.2 seconds
Started Sep 01 02:05:38 PM UTC 24
Finished Sep 01 02:13:25 PM UTC 24
Peak memory 371240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399774816 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2399774816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.1550382995
Short name T382
Test name
Test status
Simulation time 12271644513 ps
CPU time 95.53 seconds
Started Sep 01 02:05:30 PM UTC 24
Finished Sep 01 02:07:08 PM UTC 24
Peak memory 236028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550382995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1550382995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.2734492466
Short name T676
Test name
Test status
Simulation time 112808194992 ps
CPU time 2329.02 seconds
Started Sep 01 02:06:43 PM UTC 24
Finished Sep 01 02:46:01 PM UTC 24
Peak memory 760696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734492466 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2734492466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.2170112733
Short name T391
Test name
Test status
Simulation time 18439825 ps
CPU time 1.3 seconds
Started Sep 01 02:08:01 PM UTC 24
Finished Sep 01 02:08:04 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170112733 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2170112733 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_app.2218086868
Short name T395
Test name
Test status
Simulation time 3142376179 ps
CPU time 53.19 seconds
Started Sep 01 02:07:25 PM UTC 24
Finished Sep 01 02:08:20 PM UTC 24
Peak memory 258660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218086868 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2218086868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.3688017433
Short name T449
Test name
Test status
Simulation time 3239031505 ps
CPU time 397.16 seconds
Started Sep 01 02:07:23 PM UTC 24
Finished Sep 01 02:14:06 PM UTC 24
Peak memory 252496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688017433 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3688017433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.1545309530
Short name T397
Test name
Test status
Simulation time 6169728199 ps
CPU time 65.67 seconds
Started Sep 01 02:07:28 PM UTC 24
Finished Sep 01 02:08:35 PM UTC 24
Peak memory 246364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545309530 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1545309530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_error.1466272167
Short name T446
Test name
Test status
Simulation time 35300622012 ps
CPU time 369.97 seconds
Started Sep 01 02:07:36 PM UTC 24
Finished Sep 01 02:13:51 PM UTC 24
Peak memory 490024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466272167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1466272167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.2944172040
Short name T392
Test name
Test status
Simulation time 1451749148 ps
CPU time 15.84 seconds
Started Sep 01 02:07:49 PM UTC 24
Finished Sep 01 02:08:06 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944172040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2944172040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.1812215973
Short name T389
Test name
Test status
Simulation time 174682090 ps
CPU time 2.37 seconds
Started Sep 01 02:07:54 PM UTC 24
Finished Sep 01 02:07:57 PM UTC 24
Peak memory 231964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812215973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1812215973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.3327537938
Short name T692
Test name
Test status
Simulation time 68780717598 ps
CPU time 2616.86 seconds
Started Sep 01 02:06:59 PM UTC 24
Finished Sep 01 02:51:06 PM UTC 24
Peak memory 2773580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327537938 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.3327537938 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.4139364774
Short name T413
Test name
Test status
Simulation time 1875422627 ps
CPU time 184.87 seconds
Started Sep 01 02:07:08 PM UTC 24
Finished Sep 01 02:10:18 PM UTC 24
Peak memory 285140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139364774 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.4139364774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.1152371230
Short name T386
Test name
Test status
Simulation time 5181508732 ps
CPU time 35.62 seconds
Started Sep 01 02:06:58 PM UTC 24
Finished Sep 01 02:07:35 PM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152371230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1152371230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.2409196549
Short name T666
Test name
Test status
Simulation time 19763444090 ps
CPU time 2163.6 seconds
Started Sep 01 02:07:58 PM UTC 24
Finished Sep 01 02:44:27 PM UTC 24
Peak memory 727928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409196549 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2409196549 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2313757167
Short name T402
Test name
Test status
Simulation time 26395499 ps
CPU time 1.25 seconds
Started Sep 01 02:09:19 PM UTC 24
Finished Sep 01 02:09:22 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313757167 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2313757167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_app.774341371
Short name T425
Test name
Test status
Simulation time 30322109549 ps
CPU time 221.26 seconds
Started Sep 01 02:08:21 PM UTC 24
Finished Sep 01 02:12:06 PM UTC 24
Peak memory 373292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774341371 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.774341371 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.2735624794
Short name T501
Test name
Test status
Simulation time 13749562757 ps
CPU time 816.58 seconds
Started Sep 01 02:08:16 PM UTC 24
Finished Sep 01 02:22:03 PM UTC 24
Peak memory 246364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735624794 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2735624794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1650183817
Short name T408
Test name
Test status
Simulation time 1304666016 ps
CPU time 64.58 seconds
Started Sep 01 02:08:35 PM UTC 24
Finished Sep 01 02:09:41 PM UTC 24
Peak memory 246216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650183817 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1650183817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_error.2923252854
Short name T133
Test name
Test status
Simulation time 22536405203 ps
CPU time 436.35 seconds
Started Sep 01 02:08:36 PM UTC 24
Finished Sep 01 02:15:58 PM UTC 24
Peak memory 535144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923252854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2923252854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.118178754
Short name T400
Test name
Test status
Simulation time 1176763151 ps
CPU time 4.97 seconds
Started Sep 01 02:09:03 PM UTC 24
Finished Sep 01 02:09:09 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118178754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.118178754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.2016511081
Short name T407
Test name
Test status
Simulation time 6333840158 ps
CPU time 32.29 seconds
Started Sep 01 02:09:07 PM UTC 24
Finished Sep 01 02:09:41 PM UTC 24
Peak memory 262356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016511081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2016511081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3905232541
Short name T658
Test name
Test status
Simulation time 55955423942 ps
CPU time 2054.92 seconds
Started Sep 01 02:08:06 PM UTC 24
Finished Sep 01 02:42:46 PM UTC 24
Peak memory 1184352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905232541 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3905232541 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.203168982
Short name T439
Test name
Test status
Simulation time 4461367556 ps
CPU time 305.63 seconds
Started Sep 01 02:08:08 PM UTC 24
Finished Sep 01 02:13:19 PM UTC 24
Peak memory 336488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203168982 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.203168982 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.1390469112
Short name T401
Test name
Test status
Simulation time 2277862227 ps
CPU time 71.8 seconds
Started Sep 01 02:08:04 PM UTC 24
Finished Sep 01 02:09:18 PM UTC 24
Peak memory 234152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390469112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1390469112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3023301809
Short name T522
Test name
Test status
Simulation time 19981532135 ps
CPU time 897.46 seconds
Started Sep 01 02:09:10 PM UTC 24
Finished Sep 01 02:24:21 PM UTC 24
Peak memory 410192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023301809 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3023301809 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.2104972375
Short name T411
Test name
Test status
Simulation time 25629976 ps
CPU time 1.25 seconds
Started Sep 01 02:10:02 PM UTC 24
Finished Sep 01 02:10:05 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104972375 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2104972375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_app.940994021
Short name T409
Test name
Test status
Simulation time 294497007 ps
CPU time 11.3 seconds
Started Sep 01 02:09:41 PM UTC 24
Finished Sep 01 02:09:53 PM UTC 24
Peak memory 236056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940994021 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.940994021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2902850280
Short name T458
Test name
Test status
Simulation time 66632552621 ps
CPU time 437.59 seconds
Started Sep 01 02:09:42 PM UTC 24
Finished Sep 01 02:17:06 PM UTC 24
Peak memory 469548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902850280 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2902850280 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_error.4156699625
Short name T460
Test name
Test status
Simulation time 10710448495 ps
CPU time 450.36 seconds
Started Sep 01 02:09:42 PM UTC 24
Finished Sep 01 02:17:19 PM UTC 24
Peak memory 381556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156699625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.4156699625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.1642624699
Short name T412
Test name
Test status
Simulation time 821884475 ps
CPU time 9.76 seconds
Started Sep 01 02:09:54 PM UTC 24
Finished Sep 01 02:10:05 PM UTC 24
Peak memory 227968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642624699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1642624699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.2284331340
Short name T76
Test name
Test status
Simulation time 47814408 ps
CPU time 1.85 seconds
Started Sep 01 02:09:55 PM UTC 24
Finished Sep 01 02:09:58 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284331340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2284331340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3935228287
Short name T612
Test name
Test status
Simulation time 55886940110 ps
CPU time 1585.66 seconds
Started Sep 01 02:09:29 PM UTC 24
Finished Sep 01 02:36:14 PM UTC 24
Peak memory 1051176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935228287 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3935228287 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.2313293795
Short name T459
Test name
Test status
Simulation time 9127282113 ps
CPU time 453.84 seconds
Started Sep 01 02:09:31 PM UTC 24
Finished Sep 01 02:17:11 PM UTC 24
Peak memory 354860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313293795 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2313293795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1032214712
Short name T406
Test name
Test status
Simulation time 365031931 ps
CPU time 16.27 seconds
Started Sep 01 02:09:22 PM UTC 24
Finished Sep 01 02:09:40 PM UTC 24
Peak memory 236012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032214712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1032214712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.1496467818
Short name T422
Test name
Test status
Simulation time 21423876 ps
CPU time 1.36 seconds
Started Sep 01 02:11:41 PM UTC 24
Finished Sep 01 02:11:44 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496467818 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1496467818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_app.1124206687
Short name T131
Test name
Test status
Simulation time 7318216695 ps
CPU time 263.75 seconds
Started Sep 01 02:10:57 PM UTC 24
Finished Sep 01 02:15:25 PM UTC 24
Peak memory 389796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124206687 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1124206687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.3051158574
Short name T532
Test name
Test status
Simulation time 75849712799 ps
CPU time 884.07 seconds
Started Sep 01 02:10:38 PM UTC 24
Finished Sep 01 02:25:32 PM UTC 24
Peak memory 258596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051158574 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3051158574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.2142302219
Short name T440
Test name
Test status
Simulation time 10684009308 ps
CPU time 126.69 seconds
Started Sep 01 02:11:11 PM UTC 24
Finished Sep 01 02:13:20 PM UTC 24
Peak memory 277096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142302219 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2142302219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_error.3106177367
Short name T463
Test name
Test status
Simulation time 34679385962 ps
CPU time 398 seconds
Started Sep 01 02:11:20 PM UTC 24
Finished Sep 01 02:18:05 PM UTC 24
Peak memory 479848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106177367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3106177367 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.348657815
Short name T423
Test name
Test status
Simulation time 5513132853 ps
CPU time 15.4 seconds
Started Sep 01 02:11:33 PM UTC 24
Finished Sep 01 02:11:50 PM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348657815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.348657815 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.3014463964
Short name T420
Test name
Test status
Simulation time 38886204 ps
CPU time 1.77 seconds
Started Sep 01 02:11:36 PM UTC 24
Finished Sep 01 02:11:39 PM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014463964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3014463964 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.265185998
Short name T569
Test name
Test status
Simulation time 11466922802 ps
CPU time 1215.74 seconds
Started Sep 01 02:10:05 PM UTC 24
Finished Sep 01 02:30:35 PM UTC 24
Peak memory 907948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265185998 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.265185998 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.2163654996
Short name T502
Test name
Test status
Simulation time 83404630984 ps
CPU time 695.56 seconds
Started Sep 01 02:10:19 PM UTC 24
Finished Sep 01 02:22:03 PM UTC 24
Peak memory 684640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163654996 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2163654996 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.2300139947
Short name T419
Test name
Test status
Simulation time 3705882820 ps
CPU time 87.57 seconds
Started Sep 01 02:10:05 PM UTC 24
Finished Sep 01 02:11:35 PM UTC 24
Peak memory 236132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300139947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2300139947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2376295849
Short name T555
Test name
Test status
Simulation time 13186887655 ps
CPU time 1011.65 seconds
Started Sep 01 02:11:40 PM UTC 24
Finished Sep 01 02:28:44 PM UTC 24
Peak memory 594876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376295849 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2376295849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.261699762
Short name T435
Test name
Test status
Simulation time 43856044 ps
CPU time 1.2 seconds
Started Sep 01 02:12:39 PM UTC 24
Finished Sep 01 02:12:41 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261699762 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.261699762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_app.3330090467
Short name T444
Test name
Test status
Simulation time 1401706049 ps
CPU time 85.21 seconds
Started Sep 01 02:12:18 PM UTC 24
Finished Sep 01 02:13:45 PM UTC 24
Peak memory 256472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330090467 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3330090467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.3011890803
Short name T584
Test name
Test status
Simulation time 50319109787 ps
CPU time 1206.99 seconds
Started Sep 01 02:12:07 PM UTC 24
Finished Sep 01 02:32:28 PM UTC 24
Peak memory 266852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011890803 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3011890803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3524292186
Short name T430
Test name
Test status
Simulation time 1087026270 ps
CPU time 9.25 seconds
Started Sep 01 02:12:23 PM UTC 24
Finished Sep 01 02:12:34 PM UTC 24
Peak memory 244412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524292186 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3524292186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_error.2132577403
Short name T36
Test name
Test status
Simulation time 51323010824 ps
CPU time 458.12 seconds
Started Sep 01 02:12:29 PM UTC 24
Finished Sep 01 02:20:13 PM UTC 24
Peak memory 369260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132577403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2132577403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.112239898
Short name T431
Test name
Test status
Simulation time 579074089 ps
CPU time 4.44 seconds
Started Sep 01 02:12:30 PM UTC 24
Finished Sep 01 02:12:36 PM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112239898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.112239898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.1571466064
Short name T432
Test name
Test status
Simulation time 82819735 ps
CPU time 2.17 seconds
Started Sep 01 02:12:34 PM UTC 24
Finished Sep 01 02:12:38 PM UTC 24
Peak memory 231976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571466064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1571466064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1691769867
Short name T691
Test name
Test status
Simulation time 215326108618 ps
CPU time 2315.08 seconds
Started Sep 01 02:11:51 PM UTC 24
Finished Sep 01 02:50:53 PM UTC 24
Peak memory 2343476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691769867 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1691769867 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.3029781845
Short name T483
Test name
Test status
Simulation time 10259204400 ps
CPU time 497.98 seconds
Started Sep 01 02:11:55 PM UTC 24
Finished Sep 01 02:20:19 PM UTC 24
Peak memory 381540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029781845 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3029781845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.1248378057
Short name T433
Test name
Test status
Simulation time 5302640991 ps
CPU time 52.53 seconds
Started Sep 01 02:11:45 PM UTC 24
Finished Sep 01 02:12:39 PM UTC 24
Peak memory 236080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248378057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1248378057 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.2340975854
Short name T436
Test name
Test status
Simulation time 184341608 ps
CPU time 3.95 seconds
Started Sep 01 02:12:36 PM UTC 24
Finished Sep 01 02:12:42 PM UTC 24
Peak memory 230084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340975854 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2340975854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2734684504
Short name T443
Test name
Test status
Simulation time 80159790 ps
CPU time 1.36 seconds
Started Sep 01 02:13:35 PM UTC 24
Finished Sep 01 02:13:37 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734684504 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2734684504 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_app.2905674553
Short name T465
Test name
Test status
Simulation time 8995388459 ps
CPU time 297.26 seconds
Started Sep 01 02:13:10 PM UTC 24
Finished Sep 01 02:18:12 PM UTC 24
Peak memory 420448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905674553 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2905674553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.1616350905
Short name T585
Test name
Test status
Simulation time 44192567191 ps
CPU time 1176.73 seconds
Started Sep 01 02:12:43 PM UTC 24
Finished Sep 01 02:32:34 PM UTC 24
Peak memory 254564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616350905 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1616350905 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1585446626
Short name T452
Test name
Test status
Simulation time 15976020700 ps
CPU time 163.41 seconds
Started Sep 01 02:13:18 PM UTC 24
Finished Sep 01 02:16:04 PM UTC 24
Peak memory 316032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585446626 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1585446626 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_error.3348729230
Short name T455
Test name
Test status
Simulation time 5587812450 ps
CPU time 180.44 seconds
Started Sep 01 02:13:19 PM UTC 24
Finished Sep 01 02:16:22 PM UTC 24
Peak memory 383588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348729230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3348729230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1547214459
Short name T445
Test name
Test status
Simulation time 7788639298 ps
CPU time 25.6 seconds
Started Sep 01 02:13:21 PM UTC 24
Finished Sep 01 02:13:48 PM UTC 24
Peak memory 227924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547214459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1547214459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.3604845125
Short name T442
Test name
Test status
Simulation time 167182082 ps
CPU time 2.45 seconds
Started Sep 01 02:13:25 PM UTC 24
Finished Sep 01 02:13:30 PM UTC 24
Peak memory 234224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604845125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3604845125 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3426807985
Short name T669
Test name
Test status
Simulation time 70446495526 ps
CPU time 1897.84 seconds
Started Sep 01 02:12:41 PM UTC 24
Finished Sep 01 02:44:42 PM UTC 24
Peak memory 2005524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426807985 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3426807985 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.736198413
Short name T475
Test name
Test status
Simulation time 6800636976 ps
CPU time 379.17 seconds
Started Sep 01 02:12:42 PM UTC 24
Finished Sep 01 02:19:06 PM UTC 24
Peak memory 379548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736198413 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.736198413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.608215389
Short name T437
Test name
Test status
Simulation time 3202413444 ps
CPU time 28.59 seconds
Started Sep 01 02:12:40 PM UTC 24
Finished Sep 01 02:13:10 PM UTC 24
Peak memory 234276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608215389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.608215389 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.2212867092
Short name T496
Test name
Test status
Simulation time 38772343825 ps
CPU time 475.85 seconds
Started Sep 01 02:13:31 PM UTC 24
Finished Sep 01 02:21:33 PM UTC 24
Peak memory 363044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212867092 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2212867092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.3946056507
Short name T127
Test name
Test status
Simulation time 21487331 ps
CPU time 1.35 seconds
Started Sep 01 02:14:33 PM UTC 24
Finished Sep 01 02:14:35 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946056507 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3946056507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_app.3361573605
Short name T130
Test name
Test status
Simulation time 9124766818 ps
CPU time 77.61 seconds
Started Sep 01 02:13:58 PM UTC 24
Finished Sep 01 02:15:18 PM UTC 24
Peak memory 279140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361573605 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3361573605 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.2338605563
Short name T450
Test name
Test status
Simulation time 150688130 ps
CPU time 12.82 seconds
Started Sep 01 02:13:52 PM UTC 24
Finished Sep 01 02:14:06 PM UTC 24
Peak memory 234072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338605563 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2338605563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.980225415
Short name T129
Test name
Test status
Simulation time 3273343144 ps
CPU time 64.15 seconds
Started Sep 01 02:14:05 PM UTC 24
Finished Sep 01 02:15:11 PM UTC 24
Peak memory 252588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980225415 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.980225415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2688550398
Short name T125
Test name
Test status
Simulation time 868160767 ps
CPU time 23.19 seconds
Started Sep 01 02:14:06 PM UTC 24
Finished Sep 01 02:14:31 PM UTC 24
Peak memory 245888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688550398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2688550398 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.39038546
Short name T126
Test name
Test status
Simulation time 209354927 ps
CPU time 2.03 seconds
Started Sep 01 02:14:28 PM UTC 24
Finished Sep 01 02:14:31 PM UTC 24
Peak memory 232004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39038546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.39038546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.1577882969
Short name T671
Test name
Test status
Simulation time 16073172398 ps
CPU time 1843.32 seconds
Started Sep 01 02:13:46 PM UTC 24
Finished Sep 01 02:44:52 PM UTC 24
Peak memory 1098348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577882969 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.1577882969 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.2879198010
Short name T478
Test name
Test status
Simulation time 32559444424 ps
CPU time 327.99 seconds
Started Sep 01 02:13:49 PM UTC 24
Finished Sep 01 02:19:22 PM UTC 24
Peak memory 447016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879198010 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2879198010 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.4171450596
Short name T448
Test name
Test status
Simulation time 1569231830 ps
CPU time 25.48 seconds
Started Sep 01 02:13:38 PM UTC 24
Finished Sep 01 02:14:04 PM UTC 24
Peak memory 236012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171450596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.4171450596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.2697711821
Short name T599
Test name
Test status
Simulation time 137575709007 ps
CPU time 1202.05 seconds
Started Sep 01 02:14:32 PM UTC 24
Finished Sep 01 02:34:48 PM UTC 24
Peak memory 1049184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697711821 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2697711821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.1986591965
Short name T92
Test name
Test status
Simulation time 64023271 ps
CPU time 1.22 seconds
Started Sep 01 01:47:57 PM UTC 24
Finished Sep 01 01:47:59 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986591965 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1986591965 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3925444043
Short name T11
Test name
Test status
Simulation time 1285766295 ps
CPU time 16.84 seconds
Started Sep 01 01:47:38 PM UTC 24
Finished Sep 01 01:47:56 PM UTC 24
Peak memory 252452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925444043 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3925444043 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3344862176
Short name T372
Test name
Test status
Simulation time 248001708213 ps
CPU time 1070.24 seconds
Started Sep 01 01:47:34 PM UTC 24
Finished Sep 01 02:05:37 PM UTC 24
Peak memory 268900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344862176 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3344862176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.892364504
Short name T24
Test name
Test status
Simulation time 849190055 ps
CPU time 19.1 seconds
Started Sep 01 01:47:44 PM UTC 24
Finished Sep 01 01:48:05 PM UTC 24
Peak memory 235868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892364504 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.892364504 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3487935732
Short name T134
Test name
Test status
Simulation time 39943663 ps
CPU time 1.88 seconds
Started Sep 01 01:47:45 PM UTC 24
Finished Sep 01 01:47:47 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487935732 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3487935732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3551039256
Short name T6
Test name
Test status
Simulation time 29045939018 ps
CPU time 50.24 seconds
Started Sep 01 01:47:45 PM UTC 24
Finished Sep 01 01:48:36 PM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551039256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3551039256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.913448822
Short name T15
Test name
Test status
Simulation time 16079955716 ps
CPU time 115.73 seconds
Started Sep 01 01:47:39 PM UTC 24
Finished Sep 01 01:49:37 PM UTC 24
Peak memory 266984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913448822 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.913448822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_error.3444353484
Short name T176
Test name
Test status
Simulation time 5642577284 ps
CPU time 501.43 seconds
Started Sep 01 01:47:42 PM UTC 24
Finished Sep 01 01:56:11 PM UTC 24
Peak memory 395804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444353484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3444353484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.1915604981
Short name T55
Test name
Test status
Simulation time 11917363340 ps
CPU time 17.98 seconds
Started Sep 01 01:47:42 PM UTC 24
Finished Sep 01 01:48:01 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915604981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1915604981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.3308398099
Short name T38
Test name
Test status
Simulation time 87682314 ps
CPU time 1.92 seconds
Started Sep 01 01:47:47 PM UTC 24
Finished Sep 01 01:47:50 PM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308398099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3308398099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2833510113
Short name T499
Test name
Test status
Simulation time 119281309034 ps
CPU time 2031.83 seconds
Started Sep 01 01:47:33 PM UTC 24
Finished Sep 01 02:21:49 PM UTC 24
Peak memory 1212960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833510113 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2833510113 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.687663147
Short name T78
Test name
Test status
Simulation time 6923433826 ps
CPU time 231.25 seconds
Started Sep 01 01:47:41 PM UTC 24
Finished Sep 01 01:51:36 PM UTC 24
Peak memory 383924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687663147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.687663147 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.486095348
Short name T103
Test name
Test status
Simulation time 7829633889 ps
CPU time 115.49 seconds
Started Sep 01 01:47:55 PM UTC 24
Finished Sep 01 01:49:53 PM UTC 24
Peak memory 309100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486095348 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.486095348 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.2965730219
Short name T221
Test name
Test status
Simulation time 13865977641 ps
CPU time 193.8 seconds
Started Sep 01 01:47:33 PM UTC 24
Finished Sep 01 01:50:50 PM UTC 24
Peak memory 342564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965730219 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2965730219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.888898355
Short name T156
Test name
Test status
Simulation time 1626734128 ps
CPU time 61.21 seconds
Started Sep 01 01:47:32 PM UTC 24
Finished Sep 01 01:48:35 PM UTC 24
Peak memory 235976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888898355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.888898355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.2148707887
Short name T356
Test name
Test status
Simulation time 21713245642 ps
CPU time 955.48 seconds
Started Sep 01 01:47:49 PM UTC 24
Finished Sep 01 02:03:55 PM UTC 24
Peak memory 350800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148707887 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2148707887 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.1537831740
Short name T94
Test name
Test status
Simulation time 247323681 ps
CPU time 2.76 seconds
Started Sep 01 01:47:38 PM UTC 24
Finished Sep 01 01:47:42 PM UTC 24
Peak memory 230144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537831740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.1537831740 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3652199490
Short name T56
Test name
Test status
Simulation time 56357030 ps
CPU time 3.25 seconds
Started Sep 01 01:47:38 PM UTC 24
Finished Sep 01 01:47:42 PM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652199490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3652199490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.3678175624
Short name T88
Test name
Test status
Simulation time 5664568197 ps
CPU time 80.1 seconds
Started Sep 01 01:47:35 PM UTC 24
Finished Sep 01 01:48:58 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678175624 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3678175624 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.2459861735
Short name T204
Test name
Test status
Simulation time 1220475756 ps
CPU time 50.83 seconds
Started Sep 01 01:47:35 PM UTC 24
Finished Sep 01 01:48:28 PM UTC 24
Peak memory 234032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459861735 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.2459861735 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3513202171
Short name T153
Test name
Test status
Simulation time 7838701805 ps
CPU time 45.29 seconds
Started Sep 01 01:47:36 PM UTC 24
Finished Sep 01 01:48:23 PM UTC 24
Peak memory 242252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513202171 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3513202171 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.2829375967
Short name T150
Test name
Test status
Simulation time 4286949549 ps
CPU time 29.45 seconds
Started Sep 01 01:47:37 PM UTC 24
Finished Sep 01 01:48:07 PM UTC 24
Peak memory 234136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829375967 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2829375967 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.1139500694
Short name T687
Test name
Test status
Simulation time 144916057286 ps
CPU time 3666.7 seconds
Started Sep 01 01:47:37 PM UTC 24
Finished Sep 01 02:49:24 PM UTC 24
Peak memory 3615176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139500694 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1139500694 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.325254559
Short name T451
Test name
Test status
Simulation time 68645018266 ps
CPU time 1683.52 seconds
Started Sep 01 01:47:37 PM UTC 24
Finished Sep 01 02:15:59 PM UTC 24
Peak memory 1096128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325254559 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.325254559 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.2998864151
Short name T456
Test name
Test status
Simulation time 56818795 ps
CPU time 1.32 seconds
Started Sep 01 02:16:22 PM UTC 24
Finished Sep 01 02:16:24 PM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998864151 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2998864151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_app.487182158
Short name T482
Test name
Test status
Simulation time 32192422836 ps
CPU time 283.35 seconds
Started Sep 01 02:15:26 PM UTC 24
Finished Sep 01 02:20:14 PM UTC 24
Peak memory 328244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487182158 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.487182158 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.376529002
Short name T647
Test name
Test status
Simulation time 103121675167 ps
CPU time 1507.95 seconds
Started Sep 01 02:15:18 PM UTC 24
Finished Sep 01 02:40:45 PM UTC 24
Peak memory 256588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376529002 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.376529002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.87084414
Short name T472
Test name
Test status
Simulation time 13336576260 ps
CPU time 180.43 seconds
Started Sep 01 02:15:57 PM UTC 24
Finished Sep 01 02:19:01 PM UTC 24
Peak memory 334500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87084414 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.87084414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_error.703858317
Short name T479
Test name
Test status
Simulation time 45404872184 ps
CPU time 221.74 seconds
Started Sep 01 02:16:00 PM UTC 24
Finished Sep 01 02:19:45 PM UTC 24
Peak memory 416424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703858317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.703858317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3338954742
Short name T453
Test name
Test status
Simulation time 1762929598 ps
CPU time 5.32 seconds
Started Sep 01 02:16:00 PM UTC 24
Finished Sep 01 02:16:06 PM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338954742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3338954742 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.303220913
Short name T457
Test name
Test status
Simulation time 1786673022 ps
CPU time 32.18 seconds
Started Sep 01 02:16:06 PM UTC 24
Finished Sep 01 02:16:39 PM UTC 24
Peak memory 248316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303220913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.303220913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2808785493
Short name T686
Test name
Test status
Simulation time 237996160923 ps
CPU time 2015 seconds
Started Sep 01 02:15:06 PM UTC 24
Finished Sep 01 02:49:03 PM UTC 24
Peak memory 2493040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808785493 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2808785493 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.2564723170
Short name T467
Test name
Test status
Simulation time 8318083687 ps
CPU time 186.7 seconds
Started Sep 01 02:15:12 PM UTC 24
Finished Sep 01 02:18:22 PM UTC 24
Peak memory 344620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564723170 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2564723170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.2861025942
Short name T454
Test name
Test status
Simulation time 4142553590 ps
CPU time 103.09 seconds
Started Sep 01 02:14:36 PM UTC 24
Finished Sep 01 02:16:21 PM UTC 24
Peak memory 236204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861025942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2861025942 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.890613500
Short name T698
Test name
Test status
Simulation time 98008773523 ps
CPU time 2338.04 seconds
Started Sep 01 02:16:07 PM UTC 24
Finished Sep 01 02:55:32 PM UTC 24
Peak memory 975476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890613500 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.890613500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.3286492837
Short name T466
Test name
Test status
Simulation time 15282791 ps
CPU time 1.25 seconds
Started Sep 01 02:18:10 PM UTC 24
Finished Sep 01 02:18:13 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286492837 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3286492837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_app.2795124932
Short name T462
Test name
Test status
Simulation time 8684095397 ps
CPU time 41.54 seconds
Started Sep 01 02:17:12 PM UTC 24
Finished Sep 01 02:17:55 PM UTC 24
Peak memory 248480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795124932 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2795124932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.508178983
Short name T493
Test name
Test status
Simulation time 9063614699 ps
CPU time 255.03 seconds
Started Sep 01 02:17:06 PM UTC 24
Finished Sep 01 02:21:25 PM UTC 24
Peak memory 250448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508178983 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.508178983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2412010769
Short name T468
Test name
Test status
Simulation time 2677360395 ps
CPU time 76.29 seconds
Started Sep 01 02:17:20 PM UTC 24
Finished Sep 01 02:18:38 PM UTC 24
Peak memory 274988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412010769 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2412010769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_error.2188693711
Short name T503
Test name
Test status
Simulation time 25761684422 ps
CPU time 304.63 seconds
Started Sep 01 02:17:34 PM UTC 24
Finished Sep 01 02:22:42 PM UTC 24
Peak memory 342656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188693711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2188693711 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.3561893361
Short name T464
Test name
Test status
Simulation time 6439925849 ps
CPU time 10.48 seconds
Started Sep 01 02:17:57 PM UTC 24
Finished Sep 01 02:18:09 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561893361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3561893361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.2063033229
Short name T74
Test name
Test status
Simulation time 164626894 ps
CPU time 2.23 seconds
Started Sep 01 02:18:06 PM UTC 24
Finished Sep 01 02:18:09 PM UTC 24
Peak memory 234108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063033229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2063033229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.1290971108
Short name T704
Test name
Test status
Simulation time 21337322658 ps
CPU time 2527.88 seconds
Started Sep 01 02:16:25 PM UTC 24
Finished Sep 01 02:59:02 PM UTC 24
Peak memory 1417844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290971108 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.1290971108 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.3602132663
Short name T529
Test name
Test status
Simulation time 26581554303 ps
CPU time 514.57 seconds
Started Sep 01 02:16:40 PM UTC 24
Finished Sep 01 02:25:22 PM UTC 24
Peak memory 389668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602132663 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3602132663 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.1199888373
Short name T469
Test name
Test status
Simulation time 57220288569 ps
CPU time 134.72 seconds
Started Sep 01 02:16:23 PM UTC 24
Finished Sep 01 02:18:41 PM UTC 24
Peak memory 234244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199888373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1199888373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.359632140
Short name T702
Test name
Test status
Simulation time 68905469875 ps
CPU time 2352.04 seconds
Started Sep 01 02:18:09 PM UTC 24
Finished Sep 01 02:57:49 PM UTC 24
Peak memory 1368688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359632140 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.359632140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.3582889150
Short name T476
Test name
Test status
Simulation time 48891985 ps
CPU time 1.24 seconds
Started Sep 01 02:19:07 PM UTC 24
Finished Sep 01 02:19:09 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582889150 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.3582889150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_app.1645557426
Short name T471
Test name
Test status
Simulation time 629921579 ps
CPU time 9.25 seconds
Started Sep 01 02:18:42 PM UTC 24
Finished Sep 01 02:18:52 PM UTC 24
Peak memory 232052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645557426 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1645557426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.1562091357
Short name T539
Test name
Test status
Simulation time 4352283288 ps
CPU time 488.22 seconds
Started Sep 01 02:18:38 PM UTC 24
Finished Sep 01 02:26:53 PM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562091357 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1562091357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.2219074891
Short name T101
Test name
Test status
Simulation time 14750025829 ps
CPU time 390.66 seconds
Started Sep 01 02:18:46 PM UTC 24
Finished Sep 01 02:25:21 PM UTC 24
Peak memory 473688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219074891 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2219074891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_error.2729365222
Short name T489
Test name
Test status
Simulation time 19597948940 ps
CPU time 126.85 seconds
Started Sep 01 02:18:53 PM UTC 24
Finished Sep 01 02:21:02 PM UTC 24
Peak memory 344616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729365222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2729365222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2642970893
Short name T477
Test name
Test status
Simulation time 895863351 ps
CPU time 7.8 seconds
Started Sep 01 02:19:02 PM UTC 24
Finished Sep 01 02:19:11 PM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642970893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2642970893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.1591892023
Short name T474
Test name
Test status
Simulation time 36309263 ps
CPU time 1.94 seconds
Started Sep 01 02:19:02 PM UTC 24
Finished Sep 01 02:19:05 PM UTC 24
Peak memory 231552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591892023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.1591892023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1044439135
Short name T718
Test name
Test status
Simulation time 59862312403 ps
CPU time 4215.61 seconds
Started Sep 01 02:18:13 PM UTC 24
Finished Sep 01 03:29:20 PM UTC 24
Peak memory 2069100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044439135 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1044439135 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.2878771026
Short name T554
Test name
Test status
Simulation time 129391590066 ps
CPU time 613.16 seconds
Started Sep 01 02:18:22 PM UTC 24
Finished Sep 01 02:28:44 PM UTC 24
Peak memory 551532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878771026 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2878771026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.3588046248
Short name T480
Test name
Test status
Simulation time 15964811653 ps
CPU time 96.52 seconds
Started Sep 01 02:18:12 PM UTC 24
Finished Sep 01 02:19:51 PM UTC 24
Peak memory 236072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588046248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3588046248 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.1140826015
Short name T693
Test name
Test status
Simulation time 259480855893 ps
CPU time 2037.47 seconds
Started Sep 01 02:19:06 PM UTC 24
Finished Sep 01 02:53:27 PM UTC 24
Peak memory 1510296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140826015 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1140826015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.4140614570
Short name T486
Test name
Test status
Simulation time 16807291 ps
CPU time 1.32 seconds
Started Sep 01 02:20:34 PM UTC 24
Finished Sep 01 02:20:36 PM UTC 24
Peak memory 226720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140614570 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4140614570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_app.1925764607
Short name T510
Test name
Test status
Simulation time 15825017852 ps
CPU time 199.99 seconds
Started Sep 01 02:19:53 PM UTC 24
Finished Sep 01 02:23:16 PM UTC 24
Peak memory 295500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925764607 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1925764607 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.2306354658
Short name T596
Test name
Test status
Simulation time 28584366239 ps
CPU time 865.36 seconds
Started Sep 01 02:19:45 PM UTC 24
Finished Sep 01 02:34:22 PM UTC 24
Peak memory 248432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306354658 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2306354658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.174992588
Short name T513
Test name
Test status
Simulation time 21910674735 ps
CPU time 229.54 seconds
Started Sep 01 02:19:53 PM UTC 24
Finished Sep 01 02:23:46 PM UTC 24
Peak memory 283232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174992588 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.174992588 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_error.818523746
Short name T542
Test name
Test status
Simulation time 12623571116 ps
CPU time 403.58 seconds
Started Sep 01 02:20:15 PM UTC 24
Finished Sep 01 02:27:04 PM UTC 24
Peak memory 510572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818523746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.818523746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.2104200169
Short name T487
Test name
Test status
Simulation time 1737218351 ps
CPU time 21 seconds
Started Sep 01 02:20:15 PM UTC 24
Finished Sep 01 02:20:37 PM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104200169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2104200169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.332852946
Short name T484
Test name
Test status
Simulation time 29994595 ps
CPU time 1.96 seconds
Started Sep 01 02:20:20 PM UTC 24
Finished Sep 01 02:20:23 PM UTC 24
Peak memory 231612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332852946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.332852946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.604531418
Short name T667
Test name
Test status
Simulation time 12371757272 ps
CPU time 1500.98 seconds
Started Sep 01 02:19:11 PM UTC 24
Finished Sep 01 02:44:30 PM UTC 24
Peak memory 973480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604531418 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.604531418 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.2006126144
Short name T523
Test name
Test status
Simulation time 4691084823 ps
CPU time 296.65 seconds
Started Sep 01 02:19:22 PM UTC 24
Finished Sep 01 02:24:23 PM UTC 24
Peak memory 326180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006126144 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2006126144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.446784522
Short name T490
Test name
Test status
Simulation time 12264312946 ps
CPU time 118.63 seconds
Started Sep 01 02:19:10 PM UTC 24
Finished Sep 01 02:21:11 PM UTC 24
Peak memory 236072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446784522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.446784522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.1118519243
Short name T492
Test name
Test status
Simulation time 4040464169 ps
CPU time 50.28 seconds
Started Sep 01 02:20:24 PM UTC 24
Finished Sep 01 02:21:16 PM UTC 24
Peak memory 252584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118519243 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.1118519243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.583105536
Short name T497
Test name
Test status
Simulation time 21301815 ps
CPU time 1.31 seconds
Started Sep 01 02:21:34 PM UTC 24
Finished Sep 01 02:21:36 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583105536 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.583105536 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_app.4283425092
Short name T544
Test name
Test status
Simulation time 11610245508 ps
CPU time 350.29 seconds
Started Sep 01 02:21:13 PM UTC 24
Finished Sep 01 02:27:08 PM UTC 24
Peak memory 453160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283425092 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.4283425092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.10625472
Short name T549
Test name
Test status
Simulation time 14257523642 ps
CPU time 397.55 seconds
Started Sep 01 02:21:03 PM UTC 24
Finished Sep 01 02:27:46 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10625472 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.10625472 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_error.2758640087
Short name T494
Test name
Test status
Simulation time 628237928 ps
CPU time 7.74 seconds
Started Sep 01 02:21:17 PM UTC 24
Finished Sep 01 02:21:26 PM UTC 24
Peak memory 246184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758640087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2758640087 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.727570052
Short name T500
Test name
Test status
Simulation time 1887999625 ps
CPU time 23.03 seconds
Started Sep 01 02:21:26 PM UTC 24
Finished Sep 01 02:21:50 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727570052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.727570052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.2396566990
Short name T495
Test name
Test status
Simulation time 52247352 ps
CPU time 1.94 seconds
Started Sep 01 02:21:27 PM UTC 24
Finished Sep 01 02:21:30 PM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396566990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2396566990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.3693527036
Short name T673
Test name
Test status
Simulation time 37828584523 ps
CPU time 1460.05 seconds
Started Sep 01 02:20:38 PM UTC 24
Finished Sep 01 02:45:16 PM UTC 24
Peak memory 1722976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693527036 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.3693527036 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.162494925
Short name T509
Test name
Test status
Simulation time 7092503827 ps
CPU time 131.23 seconds
Started Sep 01 02:20:56 PM UTC 24
Finished Sep 01 02:23:10 PM UTC 24
Peak memory 305700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162494925 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.162494925 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.2598085220
Short name T491
Test name
Test status
Simulation time 1050635188 ps
CPU time 34.05 seconds
Started Sep 01 02:20:37 PM UTC 24
Finished Sep 01 02:21:13 PM UTC 24
Peak memory 236116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598085220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2598085220 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.4013650090
Short name T705
Test name
Test status
Simulation time 128779315459 ps
CPU time 2312.43 seconds
Started Sep 01 02:21:31 PM UTC 24
Finished Sep 01 03:00:31 PM UTC 24
Peak memory 1266552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013650090 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.4013650090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.3140833854
Short name T508
Test name
Test status
Simulation time 50953995 ps
CPU time 1.26 seconds
Started Sep 01 02:22:57 PM UTC 24
Finished Sep 01 02:23:00 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140833854 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3140833854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_app.3436418099
Short name T566
Test name
Test status
Simulation time 76873043226 ps
CPU time 461.03 seconds
Started Sep 01 02:22:04 PM UTC 24
Finished Sep 01 02:29:51 PM UTC 24
Peak memory 539172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436418099 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3436418099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3273046300
Short name T594
Test name
Test status
Simulation time 14361561544 ps
CPU time 709.3 seconds
Started Sep 01 02:21:51 PM UTC 24
Finished Sep 01 02:33:50 PM UTC 24
Peak memory 246348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273046300 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3273046300 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3061046435
Short name T525
Test name
Test status
Simulation time 16001684946 ps
CPU time 172.41 seconds
Started Sep 01 02:22:04 PM UTC 24
Finished Sep 01 02:24:59 PM UTC 24
Peak memory 365156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061046435 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3061046435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_error.3966846614
Short name T559
Test name
Test status
Simulation time 14684911060 ps
CPU time 377.35 seconds
Started Sep 01 02:22:44 PM UTC 24
Finished Sep 01 02:29:07 PM UTC 24
Peak memory 346668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966846614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3966846614 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.767998339
Short name T506
Test name
Test status
Simulation time 2117099742 ps
CPU time 7.85 seconds
Started Sep 01 02:22:44 PM UTC 24
Finished Sep 01 02:22:54 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767998339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.767998339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.1096803418
Short name T507
Test name
Test status
Simulation time 36023450 ps
CPU time 1.34 seconds
Started Sep 01 02:22:54 PM UTC 24
Finished Sep 01 02:22:57 PM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096803418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1096803418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2056137934
Short name T721
Test name
Test status
Simulation time 187743686062 ps
CPU time 4297.36 seconds
Started Sep 01 02:21:49 PM UTC 24
Finished Sep 01 03:34:17 PM UTC 24
Peak memory 3893956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056137934 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.2056137934 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.1410195011
Short name T515
Test name
Test status
Simulation time 10486147793 ps
CPU time 118.01 seconds
Started Sep 01 02:21:50 PM UTC 24
Finished Sep 01 02:23:51 PM UTC 24
Peak memory 299624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410195011 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1410195011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.3008110219
Short name T512
Test name
Test status
Simulation time 8913501552 ps
CPU time 120.9 seconds
Started Sep 01 02:21:37 PM UTC 24
Finished Sep 01 02:23:41 PM UTC 24
Peak memory 236120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008110219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3008110219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3099326966
Short name T668
Test name
Test status
Simulation time 51499213460 ps
CPU time 1285.07 seconds
Started Sep 01 02:22:54 PM UTC 24
Finished Sep 01 02:44:36 PM UTC 24
Peak memory 1219240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099326966 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3099326966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.1457410565
Short name T519
Test name
Test status
Simulation time 22024400 ps
CPU time 1.34 seconds
Started Sep 01 02:23:59 PM UTC 24
Finished Sep 01 02:24:02 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457410565 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1457410565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2627971996
Short name T557
Test name
Test status
Simulation time 18198659042 ps
CPU time 302.28 seconds
Started Sep 01 02:23:42 PM UTC 24
Finished Sep 01 02:28:49 PM UTC 24
Peak memory 399952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627971996 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2627971996 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.1756773255
Short name T635
Test name
Test status
Simulation time 14707610449 ps
CPU time 950.15 seconds
Started Sep 01 02:23:31 PM UTC 24
Finished Sep 01 02:39:33 PM UTC 24
Peak memory 260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756773255 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1756773255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2962564572
Short name T578
Test name
Test status
Simulation time 20679058098 ps
CPU time 471.09 seconds
Started Sep 01 02:23:47 PM UTC 24
Finished Sep 01 02:31:44 PM UTC 24
Peak memory 526868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962564572 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2962564572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_error.1127415658
Short name T517
Test name
Test status
Simulation time 55840480 ps
CPU time 6.24 seconds
Started Sep 01 02:23:48 PM UTC 24
Finished Sep 01 02:23:55 PM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127415658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1127415658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.2560510525
Short name T521
Test name
Test status
Simulation time 9051995843 ps
CPU time 21.71 seconds
Started Sep 01 02:23:51 PM UTC 24
Finished Sep 01 02:24:14 PM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560510525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2560510525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2053587089
Short name T518
Test name
Test status
Simulation time 141193814 ps
CPU time 2.05 seconds
Started Sep 01 02:23:55 PM UTC 24
Finished Sep 01 02:23:58 PM UTC 24
Peak memory 232004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053587089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2053587089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.2726043687
Short name T708
Test name
Test status
Simulation time 267557407030 ps
CPU time 2363.96 seconds
Started Sep 01 02:23:11 PM UTC 24
Finished Sep 01 03:03:04 PM UTC 24
Peak memory 2472628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726043687 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.2726043687 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.3529286290
Short name T576
Test name
Test status
Simulation time 16838934746 ps
CPU time 481.36 seconds
Started Sep 01 02:23:17 PM UTC 24
Finished Sep 01 02:31:24 PM UTC 24
Peak memory 395820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529286290 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.3529286290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.3986613412
Short name T516
Test name
Test status
Simulation time 5904719101 ps
CPU time 51.74 seconds
Started Sep 01 02:23:00 PM UTC 24
Finished Sep 01 02:23:54 PM UTC 24
Peak memory 234276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986613412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.3986613412 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.279266602
Short name T587
Test name
Test status
Simulation time 96916918607 ps
CPU time 528.31 seconds
Started Sep 01 02:23:56 PM UTC 24
Finished Sep 01 02:32:52 PM UTC 24
Peak memory 332856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279266602 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.279266602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.1348648222
Short name T531
Test name
Test status
Simulation time 22206096 ps
CPU time 1.21 seconds
Started Sep 01 02:25:22 PM UTC 24
Finished Sep 01 02:25:25 PM UTC 24
Peak memory 226720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348648222 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1348648222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_app.2074946874
Short name T550
Test name
Test status
Simulation time 22674825949 ps
CPU time 199.28 seconds
Started Sep 01 02:24:25 PM UTC 24
Finished Sep 01 02:27:47 PM UTC 24
Peak memory 287336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074946874 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2074946874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.1863614483
Short name T683
Test name
Test status
Simulation time 64502611540 ps
CPU time 1379.16 seconds
Started Sep 01 02:24:22 PM UTC 24
Finished Sep 01 02:47:37 PM UTC 24
Peak memory 271012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863614483 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1863614483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1624224855
Short name T543
Test name
Test status
Simulation time 5583045509 ps
CPU time 132.77 seconds
Started Sep 01 02:24:51 PM UTC 24
Finished Sep 01 02:27:06 PM UTC 24
Peak memory 322152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624224855 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1624224855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_error.1250982732
Short name T37
Test name
Test status
Simulation time 18280695447 ps
CPU time 429.69 seconds
Started Sep 01 02:25:00 PM UTC 24
Finished Sep 01 02:32:16 PM UTC 24
Peak memory 354864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250982732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1250982732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.4266013113
Short name T527
Test name
Test status
Simulation time 58520030 ps
CPU time 1.64 seconds
Started Sep 01 02:25:00 PM UTC 24
Finished Sep 01 02:25:03 PM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266013113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.4266013113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.1996356957
Short name T528
Test name
Test status
Simulation time 169439318 ps
CPU time 2.06 seconds
Started Sep 01 02:25:04 PM UTC 24
Finished Sep 01 02:25:07 PM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996356957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1996356957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.2337352463
Short name T712
Test name
Test status
Simulation time 86887599093 ps
CPU time 2768.02 seconds
Started Sep 01 02:24:10 PM UTC 24
Finished Sep 01 03:10:51 PM UTC 24
Peak memory 1462908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337352463 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.2337352463 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.1063644712
Short name T526
Test name
Test status
Simulation time 1882064623 ps
CPU time 43.46 seconds
Started Sep 01 02:24:15 PM UTC 24
Finished Sep 01 02:24:59 PM UTC 24
Peak memory 242156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063644712 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1063644712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.1885860670
Short name T520
Test name
Test status
Simulation time 211003934 ps
CPU time 6.26 seconds
Started Sep 01 02:24:02 PM UTC 24
Finished Sep 01 02:24:10 PM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885860670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1885860670 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.3964570541
Short name T538
Test name
Test status
Simulation time 6531947449 ps
CPU time 99.8 seconds
Started Sep 01 02:25:08 PM UTC 24
Finished Sep 01 02:26:50 PM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964570541 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3964570541 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.3985090194
Short name T540
Test name
Test status
Simulation time 73488211 ps
CPU time 1.23 seconds
Started Sep 01 02:26:51 PM UTC 24
Finished Sep 01 02:26:54 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985090194 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3985090194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_app.3186477658
Short name T574
Test name
Test status
Simulation time 20092112661 ps
CPU time 327.92 seconds
Started Sep 01 02:25:43 PM UTC 24
Finished Sep 01 02:31:15 PM UTC 24
Peak memory 451112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186477658 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.3186477658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.3748085904
Short name T545
Test name
Test status
Simulation time 1826385362 ps
CPU time 102.43 seconds
Started Sep 01 02:25:34 PM UTC 24
Finished Sep 01 02:27:19 PM UTC 24
Peak memory 248520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748085904 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3748085904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1274106883
Short name T567
Test name
Test status
Simulation time 15139489480 ps
CPU time 270.13 seconds
Started Sep 01 02:25:44 PM UTC 24
Finished Sep 01 02:30:18 PM UTC 24
Peak memory 377456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274106883 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1274106883 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_error.686857987
Short name T536
Test name
Test status
Simulation time 250774960 ps
CPU time 6.42 seconds
Started Sep 01 02:26:11 PM UTC 24
Finished Sep 01 02:26:19 PM UTC 24
Peak memory 234744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686857987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.686857987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.3194299963
Short name T537
Test name
Test status
Simulation time 907600660 ps
CPU time 11.7 seconds
Started Sep 01 02:26:16 PM UTC 24
Finished Sep 01 02:26:29 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194299963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3194299963 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.2582521843
Short name T541
Test name
Test status
Simulation time 3692722735 ps
CPU time 39.01 seconds
Started Sep 01 02:26:19 PM UTC 24
Finished Sep 01 02:27:00 PM UTC 24
Peak memory 262832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582521843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2582521843 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.2779765933
Short name T535
Test name
Test status
Simulation time 416228600 ps
CPU time 48.79 seconds
Started Sep 01 02:25:25 PM UTC 24
Finished Sep 01 02:26:15 PM UTC 24
Peak memory 252328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779765933 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.2779765933 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2483729297
Short name T572
Test name
Test status
Simulation time 8993110664 ps
CPU time 309.87 seconds
Started Sep 01 02:25:26 PM UTC 24
Finished Sep 01 02:30:40 PM UTC 24
Peak memory 436816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483729297 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2483729297 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.3387474520
Short name T533
Test name
Test status
Simulation time 4334134494 ps
CPU time 19.79 seconds
Started Sep 01 02:25:22 PM UTC 24
Finished Sep 01 02:25:43 PM UTC 24
Peak memory 236080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387474520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3387474520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.3240901145
Short name T700
Test name
Test status
Simulation time 95369987732 ps
CPU time 1816.55 seconds
Started Sep 01 02:26:29 PM UTC 24
Finished Sep 01 02:57:09 PM UTC 24
Peak memory 738252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240901145 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3240901145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.1600264526
Short name T551
Test name
Test status
Simulation time 27683187 ps
CPU time 1.25 seconds
Started Sep 01 02:27:46 PM UTC 24
Finished Sep 01 02:27:49 PM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600264526 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1600264526 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_app.609436714
Short name T553
Test name
Test status
Simulation time 2584890507 ps
CPU time 74.05 seconds
Started Sep 01 02:27:07 PM UTC 24
Finished Sep 01 02:28:23 PM UTC 24
Peak memory 270948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609436714 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.609436714 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.3554828939
Short name T583
Test name
Test status
Simulation time 27850359407 ps
CPU time 308.99 seconds
Started Sep 01 02:27:05 PM UTC 24
Finished Sep 01 02:32:18 PM UTC 24
Peak memory 240132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554828939 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3554828939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1774644751
Short name T556
Test name
Test status
Simulation time 30648277488 ps
CPU time 97 seconds
Started Sep 01 02:27:09 PM UTC 24
Finished Sep 01 02:28:48 PM UTC 24
Peak memory 277072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774644751 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1774644751 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_error.4035291409
Short name T627
Test name
Test status
Simulation time 66198816821 ps
CPU time 662.07 seconds
Started Sep 01 02:27:19 PM UTC 24
Finished Sep 01 02:38:30 PM UTC 24
Peak memory 641660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035291409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.4035291409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.521261746
Short name T547
Test name
Test status
Simulation time 1079923908 ps
CPU time 4.62 seconds
Started Sep 01 02:27:35 PM UTC 24
Finished Sep 01 02:27:41 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521261746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.521261746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.3053366645
Short name T548
Test name
Test status
Simulation time 48279471 ps
CPU time 2.33 seconds
Started Sep 01 02:27:41 PM UTC 24
Finished Sep 01 02:27:45 PM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053366645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3053366645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2293619370
Short name T723
Test name
Test status
Simulation time 213228323624 ps
CPU time 5308.83 seconds
Started Sep 01 02:26:55 PM UTC 24
Finished Sep 01 03:56:30 PM UTC 24
Peak memory 3934924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293619370 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2293619370 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1316322346
Short name T546
Test name
Test status
Simulation time 309188597 ps
CPU time 31.91 seconds
Started Sep 01 02:27:01 PM UTC 24
Finished Sep 01 02:27:34 PM UTC 24
Peak memory 246244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316322346 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1316322346 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.225525316
Short name T552
Test name
Test status
Simulation time 7494325854 ps
CPU time 73.27 seconds
Started Sep 01 02:26:54 PM UTC 24
Finished Sep 01 02:28:09 PM UTC 24
Peak memory 236152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225525316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.225525316 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.1217608993
Short name T564
Test name
Test status
Simulation time 5651347553 ps
CPU time 114.34 seconds
Started Sep 01 02:27:45 PM UTC 24
Finished Sep 01 02:29:42 PM UTC 24
Peak memory 279076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217608993 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1217608993 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.969691524
Short name T83
Test name
Test status
Simulation time 46787158 ps
CPU time 1.25 seconds
Started Sep 01 01:48:37 PM UTC 24
Finished Sep 01 01:48:39 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969691524 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.969691524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_app.521737626
Short name T240
Test name
Test status
Simulation time 19743359636 ps
CPU time 365.96 seconds
Started Sep 01 01:48:06 PM UTC 24
Finished Sep 01 01:54:17 PM UTC 24
Peak memory 336424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521737626 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.521737626 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.134623317
Short name T223
Test name
Test status
Simulation time 13194461934 ps
CPU time 187.45 seconds
Started Sep 01 01:48:08 PM UTC 24
Finished Sep 01 01:51:19 PM UTC 24
Peak memory 328264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134623317 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.134623317 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.3862287849
Short name T132
Test name
Test status
Simulation time 14497959440 ps
CPU time 1656.79 seconds
Started Sep 01 01:47:59 PM UTC 24
Finished Sep 01 02:15:56 PM UTC 24
Peak memory 258660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862287849 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3862287849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.1710962689
Short name T98
Test name
Test status
Simulation time 111972246 ps
CPU time 1.77 seconds
Started Sep 01 01:48:28 PM UTC 24
Finished Sep 01 01:48:30 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710962689 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1710962689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.1317176621
Short name T212
Test name
Test status
Simulation time 66236663 ps
CPU time 1.22 seconds
Started Sep 01 01:48:30 PM UTC 24
Finished Sep 01 01:48:32 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317176621 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1317176621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1929704346
Short name T185
Test name
Test status
Simulation time 60641226891 ps
CPU time 109.49 seconds
Started Sep 01 01:48:32 PM UTC 24
Finished Sep 01 01:50:24 PM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929704346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1929704346 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.1379474318
Short name T97
Test name
Test status
Simulation time 13505106997 ps
CPU time 425.79 seconds
Started Sep 01 01:48:10 PM UTC 24
Finished Sep 01 01:55:23 PM UTC 24
Peak memory 465496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379474318 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1379474318 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_error.2396099712
Short name T285
Test name
Test status
Simulation time 95347804123 ps
CPU time 555.55 seconds
Started Sep 01 01:48:11 PM UTC 24
Finished Sep 01 01:57:35 PM UTC 24
Peak memory 576012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396099712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2396099712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.793485774
Short name T85
Test name
Test status
Simulation time 7399814951 ps
CPU time 14.06 seconds
Started Sep 01 01:48:26 PM UTC 24
Finished Sep 01 01:48:41 PM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793485774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.793485774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.3492045162
Short name T69
Test name
Test status
Simulation time 90106256 ps
CPU time 1.94 seconds
Started Sep 01 01:48:34 PM UTC 24
Finished Sep 01 01:48:37 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492045162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3492045162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1843444266
Short name T203
Test name
Test status
Simulation time 78397469401 ps
CPU time 566.41 seconds
Started Sep 01 01:47:59 PM UTC 24
Finished Sep 01 01:57:33 PM UTC 24
Peak memory 903704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843444266 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1843444266 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.4142595704
Short name T32
Test name
Test status
Simulation time 621358684 ps
CPU time 22.77 seconds
Started Sep 01 01:48:11 PM UTC 24
Finished Sep 01 01:48:36 PM UTC 24
Peak memory 252844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142595704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.4142595704 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.2702145697
Short name T135
Test name
Test status
Simulation time 7023670216 ps
CPU time 131.19 seconds
Started Sep 01 01:48:36 PM UTC 24
Finished Sep 01 01:50:50 PM UTC 24
Peak memory 313120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702145697 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2702145697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.2783967778
Short name T254
Test name
Test status
Simulation time 8737534654 ps
CPU time 443.5 seconds
Started Sep 01 01:47:59 PM UTC 24
Finished Sep 01 01:55:29 PM UTC 24
Peak memory 353000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783967778 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2783967778 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.3282247715
Short name T206
Test name
Test status
Simulation time 6219111269 ps
CPU time 62.15 seconds
Started Sep 01 01:47:57 PM UTC 24
Finished Sep 01 01:49:01 PM UTC 24
Peak memory 234232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282247715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.3282247715 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.4133322299
Short name T427
Test name
Test status
Simulation time 55517688772 ps
CPU time 1410.12 seconds
Started Sep 01 01:48:35 PM UTC 24
Finished Sep 01 02:12:22 PM UTC 24
Peak memory 780844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133322299 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.4133322299 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.598079957
Short name T152
Test name
Test status
Simulation time 264553565 ps
CPU time 5.84 seconds
Started Sep 01 01:48:04 PM UTC 24
Finished Sep 01 01:48:11 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598079957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.598079957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1549090232
Short name T151
Test name
Test status
Simulation time 31747281 ps
CPU time 3.2 seconds
Started Sep 01 01:48:06 PM UTC 24
Finished Sep 01 01:48:10 PM UTC 24
Peak memory 228048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549090232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.1549090232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2121270984
Short name T86
Test name
Test status
Simulation time 5755774055 ps
CPU time 43.8 seconds
Started Sep 01 01:47:59 PM UTC 24
Finished Sep 01 01:48:45 PM UTC 24
Peak memory 236032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121270984 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2121270984 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.3863358596
Short name T84
Test name
Test status
Simulation time 4556567049 ps
CPU time 37.37 seconds
Started Sep 01 01:48:02 PM UTC 24
Finished Sep 01 01:48:40 PM UTC 24
Peak memory 234504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863358596 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3863358596 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.2056771801
Short name T87
Test name
Test status
Simulation time 6597366494 ps
CPU time 42.76 seconds
Started Sep 01 01:48:02 PM UTC 24
Finished Sep 01 01:48:46 PM UTC 24
Peak memory 242332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056771801 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2056771801 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.4200001959
Short name T154
Test name
Test status
Simulation time 2693212500 ps
CPU time 22.35 seconds
Started Sep 01 01:48:02 PM UTC 24
Finished Sep 01 01:48:25 PM UTC 24
Peak memory 230192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200001959 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4200001959 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.3805526224
Short name T205
Test name
Test status
Simulation time 10092994116 ps
CPU time 182.7 seconds
Started Sep 01 01:48:02 PM UTC 24
Finished Sep 01 01:51:07 PM UTC 24
Peak memory 291212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805526224 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3805526224 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.937213839
Short name T579
Test name
Test status
Simulation time 60401898854 ps
CPU time 2601.39 seconds
Started Sep 01 01:48:02 PM UTC 24
Finished Sep 01 02:31:54 PM UTC 24
Peak memory 3000764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937213839 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.937213839 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.3623875636
Short name T560
Test name
Test status
Simulation time 23164714 ps
CPU time 1.22 seconds
Started Sep 01 02:29:08 PM UTC 24
Finished Sep 01 02:29:11 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623875636 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3623875636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_app.662110369
Short name T562
Test name
Test status
Simulation time 1866512211 ps
CPU time 33.86 seconds
Started Sep 01 02:28:45 PM UTC 24
Finished Sep 01 02:29:20 PM UTC 24
Peak memory 237988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662110369 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.662110369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1761114424
Short name T614
Test name
Test status
Simulation time 8478249905 ps
CPU time 516.26 seconds
Started Sep 01 02:28:24 PM UTC 24
Finished Sep 01 02:37:07 PM UTC 24
Peak memory 248352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761114424 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1761114424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3936871731
Short name T610
Test name
Test status
Simulation time 18798497448 ps
CPU time 438.85 seconds
Started Sep 01 02:28:45 PM UTC 24
Finished Sep 01 02:36:09 PM UTC 24
Peak memory 537256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936871731 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3936871731 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_error.2392601270
Short name T589
Test name
Test status
Simulation time 11463887300 ps
CPU time 248.28 seconds
Started Sep 01 02:28:49 PM UTC 24
Finished Sep 01 02:33:01 PM UTC 24
Peak memory 317636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392601270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2392601270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.92808872
Short name T558
Test name
Test status
Simulation time 482943513 ps
CPU time 6.92 seconds
Started Sep 01 02:28:49 PM UTC 24
Finished Sep 01 02:28:57 PM UTC 24
Peak memory 227532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92808872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.92808872 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.1043919943
Short name T108
Test name
Test status
Simulation time 86557864 ps
CPU time 2.22 seconds
Started Sep 01 02:28:58 PM UTC 24
Finished Sep 01 02:29:01 PM UTC 24
Peak memory 234104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043919943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1043919943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.1028639280
Short name T722
Test name
Test status
Simulation time 803496833993 ps
CPU time 4392.37 seconds
Started Sep 01 02:27:50 PM UTC 24
Finished Sep 01 03:41:57 PM UTC 24
Peak memory 3633780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028639280 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.1028639280 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.3484279457
Short name T595
Test name
Test status
Simulation time 12176549285 ps
CPU time 358.64 seconds
Started Sep 01 02:28:10 PM UTC 24
Finished Sep 01 02:34:13 PM UTC 24
Peak memory 485992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484279457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3484279457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.115129111
Short name T563
Test name
Test status
Simulation time 3761966620 ps
CPU time 99.94 seconds
Started Sep 01 02:27:48 PM UTC 24
Finished Sep 01 02:29:31 PM UTC 24
Peak memory 236060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115129111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.115129111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.2937215408
Short name T608
Test name
Test status
Simulation time 16626429097 ps
CPU time 393 seconds
Started Sep 01 02:29:02 PM UTC 24
Finished Sep 01 02:35:41 PM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937215408 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2937215408 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.1615093402
Short name T571
Test name
Test status
Simulation time 19010650 ps
CPU time 1.32 seconds
Started Sep 01 02:30:37 PM UTC 24
Finished Sep 01 02:30:40 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615093402 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1615093402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_app.2783343602
Short name T601
Test name
Test status
Simulation time 11299068525 ps
CPU time 314.77 seconds
Started Sep 01 02:29:43 PM UTC 24
Finished Sep 01 02:35:02 PM UTC 24
Peak memory 442956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783343602 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2783343602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.60005883
Short name T697
Test name
Test status
Simulation time 130385443257 ps
CPU time 1514.33 seconds
Started Sep 01 02:29:32 PM UTC 24
Finished Sep 01 02:55:05 PM UTC 24
Peak memory 268832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60005883 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.60005883 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.427614394
Short name T618
Test name
Test status
Simulation time 6880988557 ps
CPU time 451.7 seconds
Started Sep 01 02:29:48 PM UTC 24
Finished Sep 01 02:37:26 PM UTC 24
Peak memory 338468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427614394 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.427614394 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1793728978
Short name T616
Test name
Test status
Simulation time 23184677048 ps
CPU time 444.59 seconds
Started Sep 01 02:29:52 PM UTC 24
Finished Sep 01 02:37:23 PM UTC 24
Peak memory 555620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793728978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1793728978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.4199810500
Short name T568
Test name
Test status
Simulation time 220178285 ps
CPU time 3.18 seconds
Started Sep 01 02:30:19 PM UTC 24
Finished Sep 01 02:30:23 PM UTC 24
Peak memory 227924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199810500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.4199810500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.1626917321
Short name T570
Test name
Test status
Simulation time 3643302231 ps
CPU time 11.72 seconds
Started Sep 01 02:30:24 PM UTC 24
Finished Sep 01 02:30:37 PM UTC 24
Peak memory 252320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626917321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1626917321 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.3515732593
Short name T588
Test name
Test status
Simulation time 19405410151 ps
CPU time 221.14 seconds
Started Sep 01 02:29:14 PM UTC 24
Finished Sep 01 02:32:58 PM UTC 24
Peak memory 451244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515732593 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.3515732593 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.3455650914
Short name T621
Test name
Test status
Simulation time 50352200297 ps
CPU time 492.29 seconds
Started Sep 01 02:29:21 PM UTC 24
Finished Sep 01 02:37:39 PM UTC 24
Peak memory 559692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455650914 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.3455650914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.607063580
Short name T565
Test name
Test status
Simulation time 1017373526 ps
CPU time 34.35 seconds
Started Sep 01 02:29:11 PM UTC 24
Finished Sep 01 02:29:47 PM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607063580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.607063580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.1672428819
Short name T713
Test name
Test status
Simulation time 49646433270 ps
CPU time 2558.82 seconds
Started Sep 01 02:30:36 PM UTC 24
Finished Sep 01 03:13:46 PM UTC 24
Peak memory 856624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672428819 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1672428819 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.154347771
Short name T581
Test name
Test status
Simulation time 24770972 ps
CPU time 1.27 seconds
Started Sep 01 02:32:03 PM UTC 24
Finished Sep 01 02:32:06 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154347771 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.154347771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_app.2258602487
Short name T613
Test name
Test status
Simulation time 5275948182 ps
CPU time 335.04 seconds
Started Sep 01 02:31:24 PM UTC 24
Finished Sep 01 02:37:04 PM UTC 24
Peak memory 328232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258602487 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2258602487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.2652618772
Short name T577
Test name
Test status
Simulation time 205290644 ps
CPU time 11.88 seconds
Started Sep 01 02:31:16 PM UTC 24
Finished Sep 01 02:31:29 PM UTC 24
Peak memory 234160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652618772 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2652618772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1453782192
Short name T586
Test name
Test status
Simulation time 9480385918 ps
CPU time 78.31 seconds
Started Sep 01 02:31:25 PM UTC 24
Finished Sep 01 02:32:45 PM UTC 24
Peak memory 264804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453782192 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1453782192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_error.3016146524
Short name T619
Test name
Test status
Simulation time 19532070813 ps
CPU time 359.81 seconds
Started Sep 01 02:31:30 PM UTC 24
Finished Sep 01 02:37:35 PM UTC 24
Peak memory 350800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016146524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3016146524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.3078983009
Short name T580
Test name
Test status
Simulation time 3614439455 ps
CPU time 11.7 seconds
Started Sep 01 02:31:45 PM UTC 24
Finished Sep 01 02:31:58 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078983009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3078983009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.155141184
Short name T64
Test name
Test status
Simulation time 657729841 ps
CPU time 7.18 seconds
Started Sep 01 02:31:54 PM UTC 24
Finished Sep 01 02:32:03 PM UTC 24
Peak memory 246300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155141184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.155141184 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1865338935
Short name T716
Test name
Test status
Simulation time 133723991522 ps
CPU time 3299.93 seconds
Started Sep 01 02:30:40 PM UTC 24
Finished Sep 01 03:26:21 PM UTC 24
Peak memory 3099244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865338935 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1865338935 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.2983955245
Short name T575
Test name
Test status
Simulation time 3894883559 ps
CPU time 10.11 seconds
Started Sep 01 02:31:12 PM UTC 24
Finished Sep 01 02:31:23 PM UTC 24
Peak memory 236168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983955245 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.2983955245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.3290955893
Short name T573
Test name
Test status
Simulation time 3692283997 ps
CPU time 28.83 seconds
Started Sep 01 02:30:40 PM UTC 24
Finished Sep 01 02:31:11 PM UTC 24
Peak memory 236176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290955893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3290955893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.782759821
Short name T684
Test name
Test status
Simulation time 100225615407 ps
CPU time 998.51 seconds
Started Sep 01 02:31:58 PM UTC 24
Finished Sep 01 02:48:49 PM UTC 24
Peak memory 545720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782759821 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.782759821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.716766544
Short name T592
Test name
Test status
Simulation time 27416113 ps
CPU time 1.28 seconds
Started Sep 01 02:33:02 PM UTC 24
Finished Sep 01 02:33:05 PM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716766544 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.716766544 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_app.2160521017
Short name T602
Test name
Test status
Simulation time 4015975650 ps
CPU time 151.69 seconds
Started Sep 01 02:32:29 PM UTC 24
Finished Sep 01 02:35:04 PM UTC 24
Peak memory 270872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160521017 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2160521017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1321106219
Short name T709
Test name
Test status
Simulation time 96870121938 ps
CPU time 1830.48 seconds
Started Sep 01 02:32:19 PM UTC 24
Finished Sep 01 03:03:11 PM UTC 24
Peak memory 277084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321106219 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1321106219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2298120486
Short name T598
Test name
Test status
Simulation time 4667437417 ps
CPU time 129.48 seconds
Started Sep 01 02:32:35 PM UTC 24
Finished Sep 01 02:34:47 PM UTC 24
Peak memory 301612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298120486 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2298120486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_error.2185388260
Short name T593
Test name
Test status
Simulation time 13932626032 ps
CPU time 53.3 seconds
Started Sep 01 02:32:46 PM UTC 24
Finished Sep 01 02:33:41 PM UTC 24
Peak memory 268972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185388260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2185388260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.1705098845
Short name T590
Test name
Test status
Simulation time 2463106917 ps
CPU time 8.54 seconds
Started Sep 01 02:32:52 PM UTC 24
Finished Sep 01 02:33:02 PM UTC 24
Peak memory 228012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705098845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.1705098845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.3845348084
Short name T591
Test name
Test status
Simulation time 37676271 ps
CPU time 2.12 seconds
Started Sep 01 02:32:59 PM UTC 24
Finished Sep 01 02:33:02 PM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845348084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3845348084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.3353243275
Short name T724
Test name
Test status
Simulation time 494492351754 ps
CPU time 6109.55 seconds
Started Sep 01 02:32:12 PM UTC 24
Finished Sep 01 04:15:14 PM UTC 24
Peak memory 4807380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353243275 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.3353243275 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.467369543
Short name T646
Test name
Test status
Simulation time 31459799225 ps
CPU time 490.99 seconds
Started Sep 01 02:32:18 PM UTC 24
Finished Sep 01 02:40:35 PM UTC 24
Peak memory 391844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467369543 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.467369543 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.1550089294
Short name T582
Test name
Test status
Simulation time 259260251 ps
CPU time 3.13 seconds
Started Sep 01 02:32:06 PM UTC 24
Finished Sep 01 02:32:11 PM UTC 24
Peak memory 234108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550089294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1550089294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.2119626211
Short name T650
Test name
Test status
Simulation time 31784144663 ps
CPU time 532.68 seconds
Started Sep 01 02:33:02 PM UTC 24
Finished Sep 01 02:42:02 PM UTC 24
Peak memory 494492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119626211 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2119626211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.91275352
Short name T603
Test name
Test status
Simulation time 15854964 ps
CPU time 1.37 seconds
Started Sep 01 02:35:03 PM UTC 24
Finished Sep 01 02:35:06 PM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91275352 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.91275352 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_app.1386331811
Short name T630
Test name
Test status
Simulation time 8251644278 ps
CPU time 268.81 seconds
Started Sep 01 02:34:14 PM UTC 24
Finished Sep 01 02:38:47 PM UTC 24
Peak memory 377364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386331811 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1386331811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.1041409001
Short name T695
Test name
Test status
Simulation time 20453604694 ps
CPU time 1231.29 seconds
Started Sep 01 02:33:50 PM UTC 24
Finished Sep 01 02:54:37 PM UTC 24
Peak memory 264840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041409001 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1041409001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.839718054
Short name T648
Test name
Test status
Simulation time 33686906872 ps
CPU time 388.4 seconds
Started Sep 01 02:34:22 PM UTC 24
Finished Sep 01 02:40:57 PM UTC 24
Peak memory 340588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839718054 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.839718054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_error.3087753865
Short name T634
Test name
Test status
Simulation time 45318500487 ps
CPU time 282.29 seconds
Started Sep 01 02:34:36 PM UTC 24
Finished Sep 01 02:39:23 PM UTC 24
Peak memory 399980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087753865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.3087753865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.3482052400
Short name T604
Test name
Test status
Simulation time 12883014823 ps
CPU time 20.68 seconds
Started Sep 01 02:34:47 PM UTC 24
Finished Sep 01 02:35:09 PM UTC 24
Peak memory 228012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482052400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3482052400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.1174250832
Short name T600
Test name
Test status
Simulation time 119770587 ps
CPU time 2.42 seconds
Started Sep 01 02:34:50 PM UTC 24
Finished Sep 01 02:34:53 PM UTC 24
Peak memory 234128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174250832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1174250832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1976420859
Short name T625
Test name
Test status
Simulation time 3836316152 ps
CPU time 310.15 seconds
Started Sep 01 02:33:05 PM UTC 24
Finished Sep 01 02:38:20 PM UTC 24
Peak memory 383664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976420859 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1976420859 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.2449544930
Short name T626
Test name
Test status
Simulation time 7288772948 ps
CPU time 275.74 seconds
Started Sep 01 02:33:43 PM UTC 24
Finished Sep 01 02:38:23 PM UTC 24
Peak memory 416292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449544930 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2449544930 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.1480484211
Short name T597
Test name
Test status
Simulation time 2821062663 ps
CPU time 90.35 seconds
Started Sep 01 02:33:03 PM UTC 24
Finished Sep 01 02:34:36 PM UTC 24
Peak memory 236112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480484211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.1480484211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.3857278216
Short name T694
Test name
Test status
Simulation time 28486893841 ps
CPU time 1147.62 seconds
Started Sep 01 02:34:54 PM UTC 24
Finished Sep 01 02:54:16 PM UTC 24
Peak memory 1233824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857278216 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3857278216 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.667051481
Short name T611
Test name
Test status
Simulation time 165625094 ps
CPU time 1.4 seconds
Started Sep 01 02:36:11 PM UTC 24
Finished Sep 01 02:36:13 PM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667051481 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.667051481 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_app.4034833558
Short name T651
Test name
Test status
Simulation time 5343243212 ps
CPU time 401.62 seconds
Started Sep 01 02:35:31 PM UTC 24
Finished Sep 01 02:42:19 PM UTC 24
Peak memory 344672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034833558 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.4034833558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.1472174722
Short name T682
Test name
Test status
Simulation time 18249849886 ps
CPU time 732.07 seconds
Started Sep 01 02:35:13 PM UTC 24
Finished Sep 01 02:47:34 PM UTC 24
Peak memory 258592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472174722 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1472174722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.471877873
Short name T615
Test name
Test status
Simulation time 4020570341 ps
CPU time 103.26 seconds
Started Sep 01 02:35:32 PM UTC 24
Finished Sep 01 02:37:18 PM UTC 24
Peak memory 258724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471877873 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.471877873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_error.3628302776
Short name T649
Test name
Test status
Simulation time 9917153476 ps
CPU time 327.01 seconds
Started Sep 01 02:35:39 PM UTC 24
Finished Sep 01 02:41:11 PM UTC 24
Peak memory 490088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628302776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3628302776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.1147411396
Short name T609
Test name
Test status
Simulation time 348269322 ps
CPU time 7.22 seconds
Started Sep 01 02:35:42 PM UTC 24
Finished Sep 01 02:35:50 PM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147411396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1147411396 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.4215727825
Short name T670
Test name
Test status
Simulation time 5764881837 ps
CPU time 568.73 seconds
Started Sep 01 02:35:07 PM UTC 24
Finished Sep 01 02:44:44 PM UTC 24
Peak memory 514588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215727825 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.4215727825 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.60098834
Short name T664
Test name
Test status
Simulation time 73411944014 ps
CPU time 533.73 seconds
Started Sep 01 02:35:10 PM UTC 24
Finished Sep 01 02:44:11 PM UTC 24
Peak memory 662184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60098834 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.60098834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.1309632053
Short name T606
Test name
Test status
Simulation time 1042400191 ps
CPU time 25.7 seconds
Started Sep 01 02:35:05 PM UTC 24
Finished Sep 01 02:35:32 PM UTC 24
Peak memory 235356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309632053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1309632053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.2604517021
Short name T714
Test name
Test status
Simulation time 102263664400 ps
CPU time 2400.03 seconds
Started Sep 01 02:35:55 PM UTC 24
Finished Sep 01 03:16:25 PM UTC 24
Peak memory 787196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604517021 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2604517021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.663598574
Short name T622
Test name
Test status
Simulation time 18052208 ps
CPU time 1.26 seconds
Started Sep 01 02:37:40 PM UTC 24
Finished Sep 01 02:37:42 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663598574 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.663598574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_app.905462900
Short name T639
Test name
Test status
Simulation time 77669091598 ps
CPU time 154.23 seconds
Started Sep 01 02:37:20 PM UTC 24
Finished Sep 01 02:39:56 PM UTC 24
Peak memory 340588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905462900 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.905462900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.1503601447
Short name T660
Test name
Test status
Simulation time 13267315937 ps
CPU time 348.46 seconds
Started Sep 01 02:37:07 PM UTC 24
Finished Sep 01 02:43:01 PM UTC 24
Peak memory 240144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503601447 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1503601447 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2005774865
Short name T640
Test name
Test status
Simulation time 6642142277 ps
CPU time 157.4 seconds
Started Sep 01 02:37:24 PM UTC 24
Finished Sep 01 02:40:04 PM UTC 24
Peak memory 311856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005774865 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2005774865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_error.700118328
Short name T665
Test name
Test status
Simulation time 16537444371 ps
CPU time 408.84 seconds
Started Sep 01 02:37:25 PM UTC 24
Finished Sep 01 02:44:19 PM UTC 24
Peak memory 553508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700118328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.700118328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.1745133638
Short name T624
Test name
Test status
Simulation time 2748432986 ps
CPU time 17.32 seconds
Started Sep 01 02:37:27 PM UTC 24
Finished Sep 01 02:37:46 PM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745133638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1745133638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.1042371385
Short name T620
Test name
Test status
Simulation time 51639023 ps
CPU time 2.05 seconds
Started Sep 01 02:37:36 PM UTC 24
Finished Sep 01 02:37:39 PM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042371385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1042371385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.2061707406
Short name T715
Test name
Test status
Simulation time 115758678348 ps
CPU time 2763.54 seconds
Started Sep 01 02:36:15 PM UTC 24
Finished Sep 01 03:22:50 PM UTC 24
Peak memory 2828856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061707406 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.2061707406 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.2136505544
Short name T662
Test name
Test status
Simulation time 16390628200 ps
CPU time 379.98 seconds
Started Sep 01 02:37:05 PM UTC 24
Finished Sep 01 02:43:31 PM UTC 24
Peak memory 344620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136505544 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2136505544 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2466466522
Short name T623
Test name
Test status
Simulation time 3823489440 ps
CPU time 89.34 seconds
Started Sep 01 02:36:14 PM UTC 24
Finished Sep 01 02:37:45 PM UTC 24
Peak memory 236056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466466522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2466466522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.168373933
Short name T703
Test name
Test status
Simulation time 120575698236 ps
CPU time 1234.48 seconds
Started Sep 01 02:37:40 PM UTC 24
Finished Sep 01 02:58:30 PM UTC 24
Peak memory 449136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168373933 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.168373933 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.3356993043
Short name T633
Test name
Test status
Simulation time 15058667 ps
CPU time 1.24 seconds
Started Sep 01 02:38:57 PM UTC 24
Finished Sep 01 02:38:59 PM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356993043 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3356993043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_app.4033259122
Short name T657
Test name
Test status
Simulation time 10305754374 ps
CPU time 255.78 seconds
Started Sep 01 02:38:24 PM UTC 24
Finished Sep 01 02:42:43 PM UTC 24
Peak memory 399908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033259122 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4033259122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.4180136400
Short name T711
Test name
Test status
Simulation time 61311376587 ps
CPU time 1760.16 seconds
Started Sep 01 02:38:21 PM UTC 24
Finished Sep 01 03:08:03 PM UTC 24
Peak memory 256520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180136400 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.4180136400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1876057126
Short name T681
Test name
Test status
Simulation time 90485757632 ps
CPU time 534.13 seconds
Started Sep 01 02:38:31 PM UTC 24
Finished Sep 01 02:47:32 PM UTC 24
Peak memory 494188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876057126 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1876057126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_error.3036124054
Short name T674
Test name
Test status
Simulation time 13322327020 ps
CPU time 404.98 seconds
Started Sep 01 02:38:34 PM UTC 24
Finished Sep 01 02:45:25 PM UTC 24
Peak memory 506472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036124054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3036124054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.538520512
Short name T632
Test name
Test status
Simulation time 1685226988 ps
CPU time 20.19 seconds
Started Sep 01 02:38:35 PM UTC 24
Finished Sep 01 02:38:57 PM UTC 24
Peak memory 229988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538520512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.538520512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.2872231357
Short name T631
Test name
Test status
Simulation time 40442314 ps
CPU time 2 seconds
Started Sep 01 02:38:48 PM UTC 24
Finished Sep 01 02:38:51 PM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872231357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2872231357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.3675602272
Short name T717
Test name
Test status
Simulation time 60491542405 ps
CPU time 2965.04 seconds
Started Sep 01 02:37:46 PM UTC 24
Finished Sep 01 03:27:47 PM UTC 24
Peak memory 2894444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675602272 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.3675602272 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.3858164810
Short name T628
Test name
Test status
Simulation time 8235493086 ps
CPU time 45.4 seconds
Started Sep 01 02:37:46 PM UTC 24
Finished Sep 01 02:38:33 PM UTC 24
Peak memory 256552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858164810 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3858164810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.2508960984
Short name T629
Test name
Test status
Simulation time 3808636435 ps
CPU time 49.32 seconds
Started Sep 01 02:37:43 PM UTC 24
Finished Sep 01 02:38:34 PM UTC 24
Peak memory 236072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508960984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.2508960984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3296161538
Short name T690
Test name
Test status
Simulation time 140359777090 ps
CPU time 686.25 seconds
Started Sep 01 02:38:52 PM UTC 24
Finished Sep 01 02:50:28 PM UTC 24
Peak memory 377844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296161538 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3296161538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.565820013
Short name T644
Test name
Test status
Simulation time 25595593 ps
CPU time 1.38 seconds
Started Sep 01 02:40:27 PM UTC 24
Finished Sep 01 02:40:30 PM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565820013 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.565820013 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_app.981532299
Short name T656
Test name
Test status
Simulation time 4487451571 ps
CPU time 166.97 seconds
Started Sep 01 02:39:50 PM UTC 24
Finished Sep 01 02:42:40 PM UTC 24
Peak memory 318004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981532299 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.981532299 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.3792412132
Short name T677
Test name
Test status
Simulation time 31419268045 ps
CPU time 387.65 seconds
Started Sep 01 02:39:38 PM UTC 24
Finished Sep 01 02:46:11 PM UTC 24
Peak memory 244444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792412132 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3792412132 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3784570856
Short name T659
Test name
Test status
Simulation time 13597691278 ps
CPU time 171.16 seconds
Started Sep 01 02:39:52 PM UTC 24
Finished Sep 01 02:42:46 PM UTC 24
Peak memory 315948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784570856 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3784570856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1414416561
Short name T645
Test name
Test status
Simulation time 1061551073 ps
CPU time 34.26 seconds
Started Sep 01 02:39:57 PM UTC 24
Finished Sep 01 02:40:33 PM UTC 24
Peak memory 262576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414416561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1414416561 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.1575125911
Short name T641
Test name
Test status
Simulation time 707317636 ps
CPU time 9.73 seconds
Started Sep 01 02:40:05 PM UTC 24
Finished Sep 01 02:40:16 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575125911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1575125911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.2328651619
Short name T642
Test name
Test status
Simulation time 291402576 ps
CPU time 5.66 seconds
Started Sep 01 02:40:17 PM UTC 24
Finished Sep 01 02:40:24 PM UTC 24
Peak memory 236032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328651619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2328651619 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1860407798
Short name T706
Test name
Test status
Simulation time 11783098699 ps
CPU time 1283.62 seconds
Started Sep 01 02:39:24 PM UTC 24
Finished Sep 01 03:01:04 PM UTC 24
Peak memory 840240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860407798 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1860407798 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.286767276
Short name T661
Test name
Test status
Simulation time 6911188852 ps
CPU time 227.28 seconds
Started Sep 01 02:39:34 PM UTC 24
Finished Sep 01 02:43:25 PM UTC 24
Peak memory 412196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286767276 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.286767276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.1115049305
Short name T637
Test name
Test status
Simulation time 25996808337 ps
CPU time 47.15 seconds
Started Sep 01 02:39:00 PM UTC 24
Finished Sep 01 02:39:49 PM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115049305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1115049305 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.297913019
Short name T685
Test name
Test status
Simulation time 26085153235 ps
CPU time 499.14 seconds
Started Sep 01 02:40:25 PM UTC 24
Finished Sep 01 02:48:51 PM UTC 24
Peak memory 328272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297913019 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.297913019 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.657421132
Short name T655
Test name
Test status
Simulation time 15525636 ps
CPU time 1.3 seconds
Started Sep 01 02:42:34 PM UTC 24
Finished Sep 01 02:42:36 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657421132 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.657421132 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_app.2968795172
Short name T679
Test name
Test status
Simulation time 8078004569 ps
CPU time 331.25 seconds
Started Sep 01 02:40:58 PM UTC 24
Finished Sep 01 02:46:34 PM UTC 24
Peak memory 330348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968795172 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2968795172 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.189842215
Short name T678
Test name
Test status
Simulation time 13616902545 ps
CPU time 339.71 seconds
Started Sep 01 02:40:46 PM UTC 24
Finished Sep 01 02:46:30 PM UTC 24
Peak memory 244332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189842215 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.189842215 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1315131356
Short name T663
Test name
Test status
Simulation time 13850404969 ps
CPU time 142.74 seconds
Started Sep 01 02:41:12 PM UTC 24
Finished Sep 01 02:43:37 PM UTC 24
Peak memory 266836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315131356 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1315131356 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_error.1345842418
Short name T672
Test name
Test status
Simulation time 2397227645 ps
CPU time 188.64 seconds
Started Sep 01 02:42:03 PM UTC 24
Finished Sep 01 02:45:15 PM UTC 24
Peak memory 309856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345842418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1345842418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.3400180479
Short name T654
Test name
Test status
Simulation time 3689207505 ps
CPU time 11.84 seconds
Started Sep 01 02:42:20 PM UTC 24
Finished Sep 01 02:42:32 PM UTC 24
Peak memory 228028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400180479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3400180479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.1397598271
Short name T653
Test name
Test status
Simulation time 131848516 ps
CPU time 1.9 seconds
Started Sep 01 02:42:21 PM UTC 24
Finished Sep 01 02:42:23 PM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397598271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1397598271 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1746572101
Short name T719
Test name
Test status
Simulation time 326404698915 ps
CPU time 2926.01 seconds
Started Sep 01 02:40:33 PM UTC 24
Finished Sep 01 03:29:57 PM UTC 24
Peak memory 2779748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746572101 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1746572101 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.2774835712
Short name T689
Test name
Test status
Simulation time 87883752344 ps
CPU time 550.06 seconds
Started Sep 01 02:40:36 PM UTC 24
Finished Sep 01 02:49:54 PM UTC 24
Peak memory 635484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774835712 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.2774835712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.808394656
Short name T652
Test name
Test status
Simulation time 43964751122 ps
CPU time 107.5 seconds
Started Sep 01 02:40:30 PM UTC 24
Finished Sep 01 02:42:20 PM UTC 24
Peak memory 236128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808394656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.808394656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.3876474990
Short name T675
Test name
Test status
Simulation time 6667058640 ps
CPU time 186.12 seconds
Started Sep 01 02:42:25 PM UTC 24
Finished Sep 01 02:45:34 PM UTC 24
Peak memory 435056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876474990 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3876474990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3252013624
Short name T215
Test name
Test status
Simulation time 232084474 ps
CPU time 1.38 seconds
Started Sep 01 01:49:38 PM UTC 24
Finished Sep 01 01:49:40 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252013624 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3252013624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_app.3424409205
Short name T257
Test name
Test status
Simulation time 22946565126 ps
CPU time 406.7 seconds
Started Sep 01 01:48:46 PM UTC 24
Finished Sep 01 01:55:38 PM UTC 24
Peak memory 494120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424409205 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.3424409205 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1129782531
Short name T260
Test name
Test status
Simulation time 37959819094 ps
CPU time 415.97 seconds
Started Sep 01 01:48:47 PM UTC 24
Finished Sep 01 01:55:48 PM UTC 24
Peak memory 524896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129782531 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1129782531 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.1980143885
Short name T163
Test name
Test status
Simulation time 54190438753 ps
CPU time 690.92 seconds
Started Sep 01 01:48:41 PM UTC 24
Finished Sep 01 02:00:21 PM UTC 24
Peak memory 254500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980143885 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1980143885 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.3787819490
Short name T216
Test name
Test status
Simulation time 789215860 ps
CPU time 32.12 seconds
Started Sep 01 01:49:21 PM UTC 24
Finished Sep 01 01:49:55 PM UTC 24
Peak memory 236020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787819490 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.3787819490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.714541009
Short name T214
Test name
Test status
Simulation time 30119282 ps
CPU time 1.55 seconds
Started Sep 01 01:49:24 PM UTC 24
Finished Sep 01 01:49:27 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714541009 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.714541009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.1741236517
Short name T184
Test name
Test status
Simulation time 2404839576 ps
CPU time 45.25 seconds
Started Sep 01 01:49:28 PM UTC 24
Finished Sep 01 01:50:15 PM UTC 24
Peak memory 232220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741236517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1741236517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.517417468
Short name T26
Test name
Test status
Simulation time 6573411432 ps
CPU time 179.68 seconds
Started Sep 01 01:48:58 PM UTC 24
Finished Sep 01 01:52:00 PM UTC 24
Peak memory 359008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517417468 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.517417468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_error.1046471911
Short name T59
Test name
Test status
Simulation time 15171972489 ps
CPU time 348.6 seconds
Started Sep 01 01:49:02 PM UTC 24
Finished Sep 01 01:54:56 PM UTC 24
Peak memory 438888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046471911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1046471911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.205664806
Short name T213
Test name
Test status
Simulation time 591796587 ps
CPU time 3.46 seconds
Started Sep 01 01:49:19 PM UTC 24
Finished Sep 01 01:49:24 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205664806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.205664806 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.12900980
Short name T42
Test name
Test status
Simulation time 54411853 ps
CPU time 2.11 seconds
Started Sep 01 01:49:31 PM UTC 24
Finished Sep 01 01:49:35 PM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12900980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.12900980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.1445753631
Short name T688
Test name
Test status
Simulation time 377379803733 ps
CPU time 3611.76 seconds
Started Sep 01 01:48:40 PM UTC 24
Finished Sep 01 02:49:32 PM UTC 24
Peak memory 3494488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445753631 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1445753631 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.1233437827
Short name T81
Test name
Test status
Simulation time 14772063773 ps
CPU time 194.19 seconds
Started Sep 01 01:48:59 PM UTC 24
Finished Sep 01 01:52:16 PM UTC 24
Peak memory 299952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233437827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.1233437827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.3346784740
Short name T249
Test name
Test status
Simulation time 229147377061 ps
CPU time 377.07 seconds
Started Sep 01 01:48:41 PM UTC 24
Finished Sep 01 01:55:04 PM UTC 24
Peak memory 541296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346784740 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3346784740 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.252192827
Short name T208
Test name
Test status
Simulation time 3758278550 ps
CPU time 50.62 seconds
Started Sep 01 01:48:38 PM UTC 24
Finished Sep 01 01:49:31 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252192827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.252192827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.1912484849
Short name T504
Test name
Test status
Simulation time 197985102204 ps
CPU time 1965.87 seconds
Started Sep 01 01:49:33 PM UTC 24
Finished Sep 01 02:22:43 PM UTC 24
Peak memory 1188792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912484849 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1912484849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1592320356
Short name T220
Test name
Test status
Simulation time 21948250 ps
CPU time 1.22 seconds
Started Sep 01 01:50:45 PM UTC 24
Finished Sep 01 01:50:47 PM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592320356 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1592320356 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_app.2424802869
Short name T187
Test name
Test status
Simulation time 20341050458 ps
CPU time 275.99 seconds
Started Sep 01 01:49:54 PM UTC 24
Finished Sep 01 01:54:34 PM UTC 24
Peak memory 391792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424802869 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2424802869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1727260840
Short name T33
Test name
Test status
Simulation time 1820620126 ps
CPU time 59.49 seconds
Started Sep 01 01:49:55 PM UTC 24
Finished Sep 01 01:50:57 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727260840 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1727260840 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.626700204
Short name T162
Test name
Test status
Simulation time 9871558616 ps
CPU time 528.44 seconds
Started Sep 01 01:49:52 PM UTC 24
Finished Sep 01 01:58:48 PM UTC 24
Peak memory 251704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626700204 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.626700204 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3135224612
Short name T217
Test name
Test status
Simulation time 79478860 ps
CPU time 1.73 seconds
Started Sep 01 01:50:28 PM UTC 24
Finished Sep 01 01:50:30 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135224612 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3135224612 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.511576855
Short name T218
Test name
Test status
Simulation time 20972903 ps
CPU time 1.38 seconds
Started Sep 01 01:50:31 PM UTC 24
Finished Sep 01 01:50:33 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511576855 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.511576855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3690823061
Short name T34
Test name
Test status
Simulation time 5121654202 ps
CPU time 88.82 seconds
Started Sep 01 01:50:32 PM UTC 24
Finished Sep 01 01:52:03 PM UTC 24
Peak memory 234364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690823061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3690823061 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_error.3867233194
Short name T21
Test name
Test status
Simulation time 24526434316 ps
CPU time 226.35 seconds
Started Sep 01 01:50:24 PM UTC 24
Finished Sep 01 01:54:14 PM UTC 24
Peak memory 397932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867233194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3867233194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.1189055928
Short name T219
Test name
Test status
Simulation time 4102982758 ps
CPU time 17.57 seconds
Started Sep 01 01:50:26 PM UTC 24
Finished Sep 01 01:50:44 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189055928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1189055928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.1769925021
Short name T696
Test name
Test status
Simulation time 162418465113 ps
CPU time 3854.21 seconds
Started Sep 01 01:49:42 PM UTC 24
Finished Sep 01 02:54:39 PM UTC 24
Peak memory 3770892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769925021 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.1769925021 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.246785585
Short name T321
Test name
Test status
Simulation time 77052473748 ps
CPU time 576.28 seconds
Started Sep 01 01:50:16 PM UTC 24
Finished Sep 01 02:00:01 PM UTC 24
Peak memory 369556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246785585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.246785585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.2671603719
Short name T31
Test name
Test status
Simulation time 7305425315 ps
CPU time 234.1 seconds
Started Sep 01 01:49:52 PM UTC 24
Finished Sep 01 01:53:49 PM UTC 24
Peak memory 419900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671603719 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2671603719 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.1900505039
Short name T222
Test name
Test status
Simulation time 2674606500 ps
CPU time 82.78 seconds
Started Sep 01 01:49:41 PM UTC 24
Finished Sep 01 01:51:05 PM UTC 24
Peak memory 235064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900505039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1900505039 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.1484296206
Short name T292
Test name
Test status
Simulation time 139345488402 ps
CPU time 434.15 seconds
Started Sep 01 01:50:38 PM UTC 24
Finished Sep 01 01:57:58 PM UTC 24
Peak memory 352868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484296206 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1484296206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.3309464776
Short name T144
Test name
Test status
Simulation time 45813803143 ps
CPU time 365.71 seconds
Started Sep 01 01:50:45 PM UTC 24
Finished Sep 01 01:56:56 PM UTC 24
Peak memory 302072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3309464776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_r
and_reset.3309464776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.1412596069
Short name T227
Test name
Test status
Simulation time 17811530 ps
CPU time 1.28 seconds
Started Sep 01 01:51:46 PM UTC 24
Finished Sep 01 01:51:48 PM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412596069 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1412596069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_app.1522930320
Short name T236
Test name
Test status
Simulation time 16173340999 ps
CPU time 124.67 seconds
Started Sep 01 01:50:58 PM UTC 24
Finished Sep 01 01:53:05 PM UTC 24
Peak memory 305672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522930320 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1522930320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2598021747
Short name T239
Test name
Test status
Simulation time 12726206669 ps
CPU time 186.26 seconds
Started Sep 01 01:51:07 PM UTC 24
Finished Sep 01 01:54:16 PM UTC 24
Peak memory 281128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598021747 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2598021747 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.2662925711
Short name T415
Test name
Test status
Simulation time 88585581725 ps
CPU time 1188.28 seconds
Started Sep 01 01:50:54 PM UTC 24
Finished Sep 01 02:10:56 PM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662925711 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2662925711 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2550200122
Short name T225
Test name
Test status
Simulation time 700207305 ps
CPU time 1.74 seconds
Started Sep 01 01:51:37 PM UTC 24
Finished Sep 01 01:51:40 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550200122 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2550200122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.410749616
Short name T224
Test name
Test status
Simulation time 195109766 ps
CPU time 1.53 seconds
Started Sep 01 01:51:38 PM UTC 24
Finished Sep 01 01:51:40 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410749616 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.410749616 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1586628508
Short name T228
Test name
Test status
Simulation time 5691251168 ps
CPU time 31.68 seconds
Started Sep 01 01:51:40 PM UTC 24
Finished Sep 01 01:52:13 PM UTC 24
Peak memory 236112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586628508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1586628508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.2139186608
Short name T267
Test name
Test status
Simulation time 6537706712 ps
CPU time 297.09 seconds
Started Sep 01 01:51:08 PM UTC 24
Finished Sep 01 01:56:09 PM UTC 24
Peak memory 305756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139186608 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2139186608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_error.2967743654
Short name T303
Test name
Test status
Simulation time 70524365287 ps
CPU time 433.47 seconds
Started Sep 01 01:51:19 PM UTC 24
Finished Sep 01 01:58:39 PM UTC 24
Peak memory 531056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967743654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.2967743654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.1282004762
Short name T226
Test name
Test status
Simulation time 1198806992 ps
CPU time 12 seconds
Started Sep 01 01:51:31 PM UTC 24
Finished Sep 01 01:51:45 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282004762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1282004762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.4082353653
Short name T70
Test name
Test status
Simulation time 118636336 ps
CPU time 1.88 seconds
Started Sep 01 01:51:41 PM UTC 24
Finished Sep 01 01:51:44 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082353653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.4082353653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.1158040469
Short name T301
Test name
Test status
Simulation time 50417489607 ps
CPU time 460.48 seconds
Started Sep 01 01:50:51 PM UTC 24
Finished Sep 01 01:58:38 PM UTC 24
Peak memory 815628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158040469 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.1158040469 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.2523314532
Short name T79
Test name
Test status
Simulation time 2078301127 ps
CPU time 17.51 seconds
Started Sep 01 01:51:18 PM UTC 24
Finished Sep 01 01:51:37 PM UTC 24
Peak memory 248556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523314532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2523314532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.3710969454
Short name T331
Test name
Test status
Simulation time 82939204253 ps
CPU time 603.45 seconds
Started Sep 01 01:50:51 PM UTC 24
Finished Sep 01 02:01:03 PM UTC 24
Peak memory 619024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710969454 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3710969454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.4072951606
Short name T229
Test name
Test status
Simulation time 3076972455 ps
CPU time 99.02 seconds
Started Sep 01 01:50:48 PM UTC 24
Finished Sep 01 01:52:29 PM UTC 24
Peak memory 235928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072951606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.4072951606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.1628911103
Short name T424
Test name
Test status
Simulation time 101014222327 ps
CPU time 1196.4 seconds
Started Sep 01 01:51:42 PM UTC 24
Finished Sep 01 02:11:54 PM UTC 24
Peak memory 383924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628911103 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1628911103 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.649066113
Short name T237
Test name
Test status
Simulation time 20062705 ps
CPU time 1.34 seconds
Started Sep 01 01:53:06 PM UTC 24
Finished Sep 01 01:53:08 PM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649066113 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.649066113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_app.1928407877
Short name T276
Test name
Test status
Simulation time 21114919615 ps
CPU time 278.54 seconds
Started Sep 01 01:52:13 PM UTC 24
Finished Sep 01 01:56:56 PM UTC 24
Peak memory 320008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928407877 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1928407877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.251580794
Short name T299
Test name
Test status
Simulation time 12224733911 ps
CPU time 362.74 seconds
Started Sep 01 01:52:16 PM UTC 24
Finished Sep 01 01:58:24 PM UTC 24
Peak memory 330276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251580794 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.251580794 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.18705873
Short name T363
Test name
Test status
Simulation time 45336581499 ps
CPU time 759.47 seconds
Started Sep 01 01:52:03 PM UTC 24
Finished Sep 01 02:04:53 PM UTC 24
Peak memory 252520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18705873 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.18705873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.313915118
Short name T232
Test name
Test status
Simulation time 3061468351 ps
CPU time 12.73 seconds
Started Sep 01 01:52:43 PM UTC 24
Finished Sep 01 01:52:57 PM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313915118 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.313915118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.238648722
Short name T233
Test name
Test status
Simulation time 67313806 ps
CPU time 1.37 seconds
Started Sep 01 01:52:56 PM UTC 24
Finished Sep 01 01:52:59 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238648722 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.238648722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.1489167501
Short name T238
Test name
Test status
Simulation time 5281241037 ps
CPU time 25.23 seconds
Started Sep 01 01:52:57 PM UTC 24
Finished Sep 01 01:53:24 PM UTC 24
Peak memory 236044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489167501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1489167501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1858251706
Short name T105
Test name
Test status
Simulation time 12411317140 ps
CPU time 117.59 seconds
Started Sep 01 01:52:19 PM UTC 24
Finished Sep 01 01:54:19 PM UTC 24
Peak memory 260676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858251706 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1858251706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_error.23153329
Short name T22
Test name
Test status
Simulation time 2274488387 ps
CPU time 194.95 seconds
Started Sep 01 01:52:22 PM UTC 24
Finished Sep 01 01:55:40 PM UTC 24
Peak memory 301608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23153329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.23153329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.1323445109
Short name T230
Test name
Test status
Simulation time 4149545075 ps
CPU time 11.28 seconds
Started Sep 01 01:52:30 PM UTC 24
Finished Sep 01 01:52:42 PM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323445109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1323445109 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.2745135369
Short name T234
Test name
Test status
Simulation time 110699436 ps
CPU time 1.97 seconds
Started Sep 01 01:52:59 PM UTC 24
Finished Sep 01 01:53:02 PM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745135369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2745135369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.2638307344
Short name T364
Test name
Test status
Simulation time 25486715135 ps
CPU time 766.26 seconds
Started Sep 01 01:52:01 PM UTC 24
Finished Sep 01 02:04:57 PM UTC 24
Peak memory 602708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638307344 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.2638307344 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2986069337
Short name T269
Test name
Test status
Simulation time 14138269890 ps
CPU time 268.02 seconds
Started Sep 01 01:52:02 PM UTC 24
Finished Sep 01 01:56:34 PM UTC 24
Peak memory 414352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986069337 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2986069337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.3316711882
Short name T235
Test name
Test status
Simulation time 3853446044 ps
CPU time 73.91 seconds
Started Sep 01 01:51:49 PM UTC 24
Finished Sep 01 01:53:05 PM UTC 24
Peak memory 236132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316711882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3316711882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.958513572
Short name T252
Test name
Test status
Simulation time 7866630476 ps
CPU time 139.71 seconds
Started Sep 01 01:53:04 PM UTC 24
Finished Sep 01 01:55:26 PM UTC 24
Peak memory 267200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958513572 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.958513572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.3648972135
Short name T245
Test name
Test status
Simulation time 57909617 ps
CPU time 1.35 seconds
Started Sep 01 01:54:32 PM UTC 24
Finished Sep 01 01:54:34 PM UTC 24
Peak memory 225100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648972135 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3648972135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_app.2291912595
Short name T246
Test name
Test status
Simulation time 1095498068 ps
CPU time 46.19 seconds
Started Sep 01 01:53:50 PM UTC 24
Finished Sep 01 01:54:38 PM UTC 24
Peak memory 252364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291912595 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2291912595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.27811777
Short name T248
Test name
Test status
Simulation time 21408611797 ps
CPU time 60.16 seconds
Started Sep 01 01:53:52 PM UTC 24
Finished Sep 01 01:54:54 PM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27811777 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.27811777 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.4077766465
Short name T378
Test name
Test status
Simulation time 13658024280 ps
CPU time 781.86 seconds
Started Sep 01 01:53:25 PM UTC 24
Finished Sep 01 02:06:38 PM UTC 24
Peak memory 256552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077766465 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.4077766465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3008240831
Short name T241
Test name
Test status
Simulation time 18496299 ps
CPU time 1.37 seconds
Started Sep 01 01:54:20 PM UTC 24
Finished Sep 01 01:54:22 PM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008240831 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3008240831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.2221891754
Short name T242
Test name
Test status
Simulation time 16367931 ps
CPU time 1.37 seconds
Started Sep 01 01:54:23 PM UTC 24
Finished Sep 01 01:54:25 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221891754 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2221891754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2356855383
Short name T266
Test name
Test status
Simulation time 29537820481 ps
CPU time 98.57 seconds
Started Sep 01 01:54:26 PM UTC 24
Finished Sep 01 01:56:07 PM UTC 24
Peak memory 234284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356855383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2356855383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.2136558911
Short name T319
Test name
Test status
Simulation time 39001119707 ps
CPU time 336.67 seconds
Started Sep 01 01:54:09 PM UTC 24
Finished Sep 01 01:59:50 PM UTC 24
Peak memory 356964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136558911 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2136558911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_error.3241592209
Short name T298
Test name
Test status
Simulation time 12097382353 ps
CPU time 241.85 seconds
Started Sep 01 01:54:17 PM UTC 24
Finished Sep 01 01:58:22 PM UTC 24
Peak memory 397924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241592209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3241592209 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.515871285
Short name T243
Test name
Test status
Simulation time 1072998641 ps
CPU time 9.62 seconds
Started Sep 01 01:54:18 PM UTC 24
Finished Sep 01 01:54:28 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515871285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.515871285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.1417752033
Short name T244
Test name
Test status
Simulation time 62322079 ps
CPU time 1.99 seconds
Started Sep 01 01:54:27 PM UTC 24
Finished Sep 01 01:54:30 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417752033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1417752033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3421687103
Short name T488
Test name
Test status
Simulation time 181310300311 ps
CPU time 1645.31 seconds
Started Sep 01 01:53:11 PM UTC 24
Finished Sep 01 02:20:55 PM UTC 24
Peak memory 1851988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421687103 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3421687103 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.3654268569
Short name T271
Test name
Test status
Simulation time 8196552349 ps
CPU time 139.04 seconds
Started Sep 01 01:54:16 PM UTC 24
Finished Sep 01 01:56:37 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654268569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3654268569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.1798777766
Short name T284
Test name
Test status
Simulation time 8336490797 ps
CPU time 241.43 seconds
Started Sep 01 01:53:23 PM UTC 24
Finished Sep 01 01:57:29 PM UTC 24
Peak memory 393836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798777766 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1798777766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.3745491043
Short name T211
Test name
Test status
Simulation time 26460182644 ps
CPU time 79.39 seconds
Started Sep 01 01:53:09 PM UTC 24
Finished Sep 01 01:54:30 PM UTC 24
Peak memory 234296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745491043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3745491043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.1272259777
Short name T383
Test name
Test status
Simulation time 29953357517 ps
CPU time 762.59 seconds
Started Sep 01 01:54:29 PM UTC 24
Finished Sep 01 02:07:21 PM UTC 24
Peak memory 334704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272259777 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1272259777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/9.kmac_stress_all/latest
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