Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15568539	1			T11	118		T12	148		T13	1041
all_values[1]	15568539	1			T11	118		T12	148		T13	1041
all_values[2]	15568539	1			T11	118		T12	148		T13	1041

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

516038

1

T11

125

T12

82

T13

10

auto[1]

46189579

1

T11

229

T12

362

T13

3113

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46494804

1

T11

336

T12

432

T13

2760

auto[1]

210813

1

T11

18

T12

12

T13

363

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	188840	1			T11	112		T13	3		T46	6
all_values[0]	auto[0]	auto[1]	1325	1			T11	6		T13	4		T46	2
all_values[0]	auto[1]	auto[0]	15309428	1			T12	144		T13	917		T30	85
all_values[0]	auto[1]	auto[1]	68946	1			T12	4		T13	117		T30	3
all_values[1]	auto[0]	auto[0]	136913	1			T11	5		T12	6		T13	1
all_values[1]	auto[0]	auto[1]	940	1			T11	2		T12	1		T13	2
all_values[1]	auto[1]	auto[0]	15361355	1			T11	107		T12	138		T13	919
all_values[1]	auto[1]	auto[1]	69331	1			T11	4		T12	3		T13	119
all_values[2]	auto[0]	auto[0]	186958	1			T12	72		T30	85		T46	6
all_values[2]	auto[0]	auto[1]	1062	1			T12	3		T30	3		T46	2
all_values[2]	auto[1]	auto[0]	15311310	1			T11	112		T12	72		T13	920
all_values[2]	auto[1]	auto[1]	69209	1			T11	6		T12	1		T13	121