Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	219	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	2658	1			T52	5		T145	5		T146	5
len_5001_7500	6482	1			T51	2		T52	8		T145	32
len_2501_5000	1485	1			T52	4		T145	5		T146	2
len_1025_2500	910	1			T145	2		T146	1		T147	4
len_769_1024	5084	1			T10	3		T23	2		T15	9
len_513_768	5478	1			T9	3		T10	5		T14	2
len_257_512	5864	1			T9	1		T10	2		T14	5
len_0_256	18660	1			T11	3		T12	3		T13	73
len_keccak_block_sizes[72]	46	1			T13	1		T45	1		T47	1
len_keccak_block_sizes[104]	35	1			T10	1		T47	1		T53	1
len_keccak_block_sizes[136]	32	1			T47	1		T53	1		T54	1
len_keccak_block_sizes[144]	35	1			T47	1		T54	1		T186	1
len_keccak_block_sizes[168]	22	1			T186	1		T137	1		T187	1
len_1	75	1			T13	1		T45	1		T47	1
len_0	516	1			T13	1		T45	1		T29	2