Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15568539	1			T11	118		T12	148		T13	1041
all_pins[1]	15568539	1			T11	118		T12	148		T13	1041
all_pins[2]	15568539	1			T11	118		T12	148		T13	1041

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46286862	1			T11	354		T12	440		T13	3006
values[0x1]	418755	1			T12	4		T13	117		T30	3
transitions[0x0=>0x1]	416374	1			T12	4		T13	117		T30	3
transitions[0x1=>0x0]	416396	1			T12	4		T13	117		T30	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15499593	1			T11	118		T12	144		T13	924
all_pins[0]	values[0x1]	68946	1			T12	4		T13	117		T30	3
all_pins[0]	transitions[0x0=>0x1]	68937	1			T12	4		T13	117		T30	3
all_pins[0]	transitions[0x1=>0x0]	4766	1			T23	7		T51	2		T49	13
all_pins[1]	values[0x0]	15563764	1			T11	118		T12	148		T13	1041
all_pins[1]	values[0x1]	4775	1			T23	7		T51	2		T49	13
all_pins[1]	transitions[0x0=>0x1]	4474	1			T23	7		T51	2		T49	13
all_pins[1]	transitions[0x1=>0x0]	344733	1			T23	4		T31	8855		T20	1103
all_pins[2]	values[0x0]	15223505	1			T11	118		T12	148		T13	1041
all_pins[2]	values[0x1]	345034	1			T23	4		T31	8881		T20	1103
all_pins[2]	transitions[0x0=>0x1]	342963	1			T23	4		T31	8823		T20	1102
all_pins[2]	transitions[0x1=>0x0]	66897	1			T12	4		T13	117		T30	3