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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.40 97.89 92.58 99.89 78.17 95.53 98.89 97.88


Total test records in report: 882
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T760 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.1041816189 Sep 04 06:11:27 AM UTC 24 Sep 04 06:11:41 AM UTC 24 504887404 ps
T761 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.2534346604 Sep 04 06:11:28 AM UTC 24 Sep 04 06:11:42 AM UTC 24 434703010 ps
T762 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3860867859 Sep 04 06:11:30 AM UTC 24 Sep 04 06:11:41 AM UTC 24 152635088 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3881986924 Sep 04 06:11:34 AM UTC 24 Sep 04 06:11:41 AM UTC 24 461009452 ps
T764 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1659504861 Sep 04 06:11:30 AM UTC 24 Sep 04 06:11:42 AM UTC 24 71124616 ps
T765 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4224031177 Sep 04 06:11:38 AM UTC 24 Sep 04 06:11:42 AM UTC 24 40058022 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.60090150 Sep 04 06:11:27 AM UTC 24 Sep 04 06:11:42 AM UTC 24 448060283 ps
T766 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3894362634 Sep 04 06:11:28 AM UTC 24 Sep 04 06:11:42 AM UTC 24 512535388 ps
T767 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1923620243 Sep 04 06:11:32 AM UTC 24 Sep 04 06:11:42 AM UTC 24 103933402 ps
T768 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2987390656 Sep 04 06:11:39 AM UTC 24 Sep 04 06:11:42 AM UTC 24 481169380 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.2025030263 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:43 AM UTC 24 48900312 ps
T769 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1449325748 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:43 AM UTC 24 28812748 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3996887736 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:43 AM UTC 24 85661797 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1741155279 Sep 04 06:11:32 AM UTC 24 Sep 04 06:11:43 AM UTC 24 198943622 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4016935978 Sep 04 06:11:39 AM UTC 24 Sep 04 06:11:43 AM UTC 24 334583451 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3070921250 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:44 AM UTC 24 247049440 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2561471158 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:44 AM UTC 24 38620370 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3169587628 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:44 AM UTC 24 176710259 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3005939764 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:44 AM UTC 24 141280965 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2570783241 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:45 AM UTC 24 193082430 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.4150744928 Sep 04 06:11:41 AM UTC 24 Sep 04 06:11:45 AM UTC 24 438661529 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1439457732 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:45 AM UTC 24 42335108 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.4251728270 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:45 AM UTC 24 15842286 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.976010337 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:56 AM UTC 24 27025667 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.820486652 Sep 04 06:11:24 AM UTC 24 Sep 04 06:11:45 AM UTC 24 1521534618 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2800110540 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:45 AM UTC 24 49656577 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.4166093654 Sep 04 06:11:24 AM UTC 24 Sep 04 06:11:45 AM UTC 24 726849324 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3464444535 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:45 AM UTC 24 19313207 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.817654206 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:46 AM UTC 24 32324578 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1205358601 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:46 AM UTC 24 41385490 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3913508879 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:46 AM UTC 24 39356319 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1729807314 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:46 AM UTC 24 35296435 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2173361913 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:46 AM UTC 24 132710054 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3076437399 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:46 AM UTC 24 63018864 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1994669047 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:46 AM UTC 24 187409431 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.485054410 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:46 AM UTC 24 55938440 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1315410255 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:47 AM UTC 24 75186242 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3048652270 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:47 AM UTC 24 105814520 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.469106949 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:47 AM UTC 24 99026482 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4209737797 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:47 AM UTC 24 91394753 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.445961134 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:47 AM UTC 24 90646999 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.90804543 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:47 AM UTC 24 99189339 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.932269652 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:47 AM UTC 24 223895479 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2918222333 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:48 AM UTC 24 71388160 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3874030145 Sep 04 06:11:43 AM UTC 24 Sep 04 06:11:48 AM UTC 24 1559183272 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2260384525 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:48 AM UTC 24 28891705 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.156560685 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:48 AM UTC 24 28738922 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2140343420 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:49 AM UTC 24 34065406 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3682500203 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:49 AM UTC 24 133983387 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3152843438 Sep 04 06:11:27 AM UTC 24 Sep 04 06:11:49 AM UTC 24 5164386536 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1504943672 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:49 AM UTC 24 125098347 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3187457070 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:50 AM UTC 24 220596496 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2745707116 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:52 AM UTC 24 137183444 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3667177998 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:53 AM UTC 24 47487508 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3308028510 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:53 AM UTC 24 208249909 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1318570068 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:56 AM UTC 24 523749618 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1746794561 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:54 AM UTC 24 112849858 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4234867082 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:54 AM UTC 24 23978621 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1688786978 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:54 AM UTC 24 43311886 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.75660967 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 15607555 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2849406553 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 13896340 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3391801270 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 13898367 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3035795356 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:54 AM UTC 24 353806463 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3353060402 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:54 AM UTC 24 62449138 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2330580947 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 46974345 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3477049592 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 36238703 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3022010398 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 93975319 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2327037724 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 92859024 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.4154727250 Sep 04 06:11:44 AM UTC 24 Sep 04 06:11:54 AM UTC 24 298638069 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2085437956 Sep 04 06:11:51 AM UTC 24 Sep 04 06:11:54 AM UTC 24 167569358 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1843077397 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:54 AM UTC 24 131899619 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4095080812 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 37768746 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2241203368 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 102412155 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1021063782 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 40712951 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1378466135 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 82296994 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3503672194 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 293516039 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1173718770 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:55 AM UTC 24 43276401 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.341812206 Sep 04 06:11:53 AM UTC 24 Sep 04 06:11:55 AM UTC 24 28135223 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.869509923 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:55 AM UTC 24 187099034 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4280806709 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:56 AM UTC 24 28423286 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2100562170 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:56 AM UTC 24 125361477 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3858771703 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:56 AM UTC 24 127377585 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1886726692 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:56 AM UTC 24 82933268 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3393164608 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:57 AM UTC 24 43519115 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3049609328 Sep 04 06:11:49 AM UTC 24 Sep 04 06:11:57 AM UTC 24 1896280163 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3469512495 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:57 AM UTC 24 22011160 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2381610712 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 20778639 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3626403066 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 16937185 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.220036989 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 41551094 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2948529307 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 36772401 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.340595163 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 51565188 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3712829316 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 136125674 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3231978992 Sep 04 06:11:53 AM UTC 24 Sep 04 06:11:58 AM UTC 24 98425384 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.541142426 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:58 AM UTC 24 428164486 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.322335848 Sep 04 06:11:55 AM UTC 24 Sep 04 06:11:58 AM UTC 24 54056704 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3561773816 Sep 04 06:11:27 AM UTC 24 Sep 04 06:11:58 AM UTC 24 2888507532 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.74043081 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:59 AM UTC 24 14869477 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1231436777 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:59 AM UTC 24 17371140 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3330614602 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:59 AM UTC 24 105260459 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3871879015 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:59 AM UTC 24 21309208 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1569056140 Sep 04 06:11:55 AM UTC 24 Sep 04 06:11:59 AM UTC 24 95220159 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.860027625 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:59 AM UTC 24 42219537 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3652888405 Sep 04 06:11:46 AM UTC 24 Sep 04 06:11:59 AM UTC 24 888769872 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.189594786 Sep 04 06:11:56 AM UTC 24 Sep 04 06:11:59 AM UTC 24 153107613 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3211166082 Sep 04 06:11:46 AM UTC 24 Sep 04 06:12:00 AM UTC 24 142657266 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2336961446 Sep 04 06:11:55 AM UTC 24 Sep 04 06:12:00 AM UTC 24 37844703 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1776346358 Sep 04 06:11:55 AM UTC 24 Sep 04 06:12:00 AM UTC 24 37428923 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2298807074 Sep 04 06:11:56 AM UTC 24 Sep 04 06:12:00 AM UTC 24 53825320 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.944264538 Sep 04 06:11:56 AM UTC 24 Sep 04 06:12:00 AM UTC 24 466312379 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.777060415 Sep 04 06:11:56 AM UTC 24 Sep 04 06:12:00 AM UTC 24 109745832 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3667967230 Sep 04 06:11:46 AM UTC 24 Sep 04 06:12:02 AM UTC 24 219622725 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3024551154 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:08 AM UTC 24 54368369 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.212038093 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:09 AM UTC 24 20888661 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2490891382 Sep 04 06:12:01 AM UTC 24 Sep 04 06:12:10 AM UTC 24 19837565 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3927631519 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 23437491 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2945259151 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 10287001 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2039062237 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 19607792 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2343328751 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 17192651 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.417469238 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 16797622 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3889999974 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 14826877 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.4236103068 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 43928483 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1912889543 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:10 AM UTC 24 11321311 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.4215137355 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 15423607 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2360233943 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:10 AM UTC 24 19971608 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2642328361 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:10 AM UTC 24 33971189 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1844569959 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:11 AM UTC 24 33268515 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.998363051 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:11 AM UTC 24 13874383 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2008237483 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:11 AM UTC 24 35227536 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.60095468 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:11 AM UTC 24 15744587 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1490769323 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:11 AM UTC 24 29671364 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1410877726 Sep 04 06:11:58 AM UTC 24 Sep 04 06:12:11 AM UTC 24 39817548 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2826652686 Sep 04 06:11:59 AM UTC 24 Sep 04 06:12:11 AM UTC 24 54698322 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.1769607306
Short name T9
Test name
Test status
Simulation time 1249570074 ps
CPU time 15.93 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:59 AM UTC 24
Peak memory 250452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769607306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1769607306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.51675639
Short name T15
Test name
Test status
Simulation time 58912079711 ps
CPU time 115.02 seconds
Started Sep 04 06:22:55 AM UTC 24
Finished Sep 04 06:24:52 AM UTC 24
Peak memory 329724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51675639 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.51675639 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.3732184946
Short name T51
Test name
Test status
Simulation time 5126713277 ps
CPU time 122.99 seconds
Started Sep 04 06:23:19 AM UTC 24
Finished Sep 04 06:25:25 AM UTC 24
Peak memory 285340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3732184946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_r
and_reset.3732184946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.942497662
Short name T125
Test name
Test status
Simulation time 157763997 ps
CPU time 2.54 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:13 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942497662 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.942497662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.3524217978
Short name T19
Test name
Test status
Simulation time 3471705087 ps
CPU time 42.2 seconds
Started Sep 04 06:22:33 AM UTC 24
Finished Sep 04 06:23:20 AM UTC 24
Peak memory 286512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524217978 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3524217978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1523636105
Short name T5
Test name
Test status
Simulation time 3672242200 ps
CPU time 25.12 seconds
Started Sep 04 06:23:11 AM UTC 24
Finished Sep 04 06:23:37 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523636105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1523636105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.2727208776
Short name T7
Test name
Test status
Simulation time 1442756769 ps
CPU time 4.8 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:47 AM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727208776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2727208776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_error.602216245
Short name T20
Test name
Test status
Simulation time 19974574428 ps
CPU time 366.54 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:28:53 AM UTC 24
Peak memory 373372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602216245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.602216245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2602263207
Short name T106
Test name
Test status
Simulation time 41287541 ps
CPU time 1.09 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602263207 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.2602263207 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.1889626388
Short name T67
Test name
Test status
Simulation time 76598477503 ps
CPU time 1107.1 seconds
Started Sep 04 06:23:16 AM UTC 24
Finished Sep 04 06:41:56 AM UTC 24
Peak memory 547728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889626388 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.1889626388 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.542275779
Short name T59
Test name
Test status
Simulation time 52283819 ps
CPU time 2.34 seconds
Started Sep 04 06:47:12 AM UTC 24
Finished Sep 04 06:47:16 AM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542275779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.542275779 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.2200063012
Short name T62
Test name
Test status
Simulation time 588781929 ps
CPU time 2.04 seconds
Started Sep 04 06:48:41 AM UTC 24
Finished Sep 04 06:48:44 AM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200063012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2200063012 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.2025030263
Short name T167
Test name
Test status
Simulation time 48900312 ps
CPU time 0.94 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:43 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025030263 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2025030263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3493293024
Short name T2
Test name
Test status
Simulation time 26943621 ps
CPU time 1.01 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:43 AM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493293024 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3493293024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.1109078248
Short name T88
Test name
Test status
Simulation time 2875675207 ps
CPU time 17.73 seconds
Started Sep 04 07:14:53 AM UTC 24
Finished Sep 04 07:15:12 AM UTC 24
Peak memory 248492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109078248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1109078248 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.236106005
Short name T3
Test name
Test status
Simulation time 23158488 ps
CPU time 1.09 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:44 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236106005 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.236106005 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.1496050390
Short name T29
Test name
Test status
Simulation time 1357885614 ps
CPU time 31.99 seconds
Started Sep 04 06:22:35 AM UTC 24
Finished Sep 04 06:23:11 AM UTC 24
Peak memory 235948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496050390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1496050390 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.2406371644
Short name T39
Test name
Test status
Simulation time 52156363 ps
CPU time 2.17 seconds
Started Sep 04 06:33:40 AM UTC 24
Finished Sep 04 06:33:44 AM UTC 24
Peak memory 232060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406371644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2406371644 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.2589526639
Short name T140
Test name
Test status
Simulation time 23107529 ps
CPU time 1.32 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589526639 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.2589526639 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.469106949
Short name T110
Test name
Test status
Simulation time 99026482 ps
CPU time 2.37 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469106949 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.4691
06949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.3410134423
Short name T137
Test name
Test status
Simulation time 12843140399 ps
CPU time 159.24 seconds
Started Sep 04 06:22:45 AM UTC 24
Finished Sep 04 06:25:27 AM UTC 24
Peak memory 291344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410134423 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3410134423 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.3222562503
Short name T80
Test name
Test status
Simulation time 45459272 ps
CPU time 2.13 seconds
Started Sep 04 06:54:34 AM UTC 24
Finished Sep 04 06:54:38 AM UTC 24
Peak memory 232040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222562503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3222562503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.1447822476
Short name T58
Test name
Test status
Simulation time 60423508 ps
CPU time 2.49 seconds
Started Sep 04 06:59:37 AM UTC 24
Finished Sep 04 06:59:40 AM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447822476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1447822476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.610503732
Short name T55
Test name
Test status
Simulation time 108351265 ps
CPU time 1.89 seconds
Started Sep 04 07:24:41 AM UTC 24
Finished Sep 04 07:24:45 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610503732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.610503732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.1887374401
Short name T89
Test name
Test status
Simulation time 34831220 ps
CPU time 2.2 seconds
Started Sep 04 08:03:07 AM UTC 24
Finished Sep 04 08:03:11 AM UTC 24
Peak memory 234048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887374401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1887374401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.1702129719
Short name T1
Test name
Test status
Simulation time 32073496 ps
CPU time 0.71 seconds
Started Sep 04 06:22:33 AM UTC 24
Finished Sep 04 06:22:38 AM UTC 24
Peak memory 227212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702129719 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1702129719 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.609061954
Short name T171
Test name
Test status
Simulation time 209881957 ps
CPU time 4.21 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:30 AM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609061954 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.609061954 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2981225935
Short name T191
Test name
Test status
Simulation time 44014962524 ps
CPU time 412.95 seconds
Started Sep 04 06:30:34 AM UTC 24
Finished Sep 04 06:37:33 AM UTC 24
Peak memory 270788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981225935 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2981225935 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2726867844
Short name T115
Test name
Test status
Simulation time 1325413360 ps
CPU time 2.72 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726867844 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2726
867844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.404743938
Short name T66
Test name
Test status
Simulation time 13818794780 ps
CPU time 385.43 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:29:12 AM UTC 24
Peak memory 485964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404743938 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.404743938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.2577792721
Short name T154
Test name
Test status
Simulation time 43837494 ps
CPU time 0.91 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577792721 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2577792721 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_error.335598716
Short name T84
Test name
Test status
Simulation time 5573643921 ps
CPU time 377.18 seconds
Started Sep 04 06:25:25 AM UTC 24
Finished Sep 04 06:31:47 AM UTC 24
Peak memory 387600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335598716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.335598716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3187457070
Short name T176
Test name
Test status
Simulation time 220596496 ps
CPU time 2.73 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:50 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187457070 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3187457070 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.29149901
Short name T127
Test name
Test status
Simulation time 151151218 ps
CPU time 2.75 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 225464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29149901 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.29149901 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.4194114388
Short name T172
Test name
Test status
Simulation time 216998961 ps
CPU time 2.51 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:34 AM UTC 24
Peak memory 225584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194114388 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.4194114388 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2482374658
Short name T73
Test name
Test status
Simulation time 21659825208 ps
CPU time 280.04 seconds
Started Sep 04 07:05:32 AM UTC 24
Finished Sep 04 07:10:16 AM UTC 24
Peak memory 401964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482374658 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2482374658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.1993073200
Short name T25
Test name
Test status
Simulation time 24554830253 ps
CPU time 319.37 seconds
Started Sep 04 06:22:35 AM UTC 24
Finished Sep 04 06:28:05 AM UTC 24
Peak memory 473700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993073200 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1993073200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_error.433685173
Short name T35
Test name
Test status
Simulation time 9234215901 ps
CPU time 306.64 seconds
Started Sep 04 06:59:07 AM UTC 24
Finished Sep 04 07:04:18 AM UTC 24
Peak memory 432740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433685173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.433685173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.4145700285
Short name T729
Test name
Test status
Simulation time 541778013 ps
CPU time 6.83 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:17 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145700285 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4145700285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.3258792709
Short name T730
Test name
Test status
Simulation time 589720638 ps
CPU time 13.19 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:24 AM UTC 24
Peak memory 225592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258792709 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3258792709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.3162568868
Short name T129
Test name
Test status
Simulation time 112681172 ps
CPU time 1.02 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162568868 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3162568868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2088049017
Short name T132
Test name
Test status
Simulation time 177651610 ps
CPU time 1.65 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 228592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2088049017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_
rw_with_rand_reset.2088049017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.1902086000
Short name T181
Test name
Test status
Simulation time 22016791 ps
CPU time 0.87 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902086000 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.1902086000 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.584058441
Short name T128
Test name
Test status
Simulation time 34534978 ps
CPU time 0.74 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584058441 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.584058441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2535392638
Short name T726
Test name
Test status
Simulation time 33157348 ps
CPU time 0.68 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 225008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535392638 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2535392638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.941969351
Short name T728
Test name
Test status
Simulation time 697506912 ps
CPU time 2.23 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:13 AM UTC 24
Peak memory 225480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941969351 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.941969351 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2035866688
Short name T105
Test name
Test status
Simulation time 32717801 ps
CPU time 1.13 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035866688 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2035866688 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.4089814131
Short name T107
Test name
Test status
Simulation time 115733261 ps
CPU time 1.55 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089814131 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.4089
814131 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3233876434
Short name T133
Test name
Test status
Simulation time 727995692 ps
CPU time 4.06 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:14 AM UTC 24
Peak memory 225744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233876434 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3233876434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.985938018
Short name T157
Test name
Test status
Simulation time 1984918003 ps
CPU time 8.47 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:34 AM UTC 24
Peak memory 225584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985938018 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.985938018 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2273552438
Short name T747
Test name
Test status
Simulation time 758948685 ps
CPU time 9.74 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:35 AM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273552438 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2273552438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2537270758
Short name T731
Test name
Test status
Simulation time 17591349 ps
CPU time 0.94 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537270758 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2537270758 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1173259842
Short name T136
Test name
Test status
Simulation time 28080558 ps
CPU time 1.52 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1173259842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_
rw_with_rand_reset.1173259842 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1140898091
Short name T732
Test name
Test status
Simulation time 27559668 ps
CPU time 1 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140898091 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1140898091 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2216093349
Short name T130
Test name
Test status
Simulation time 47568365 ps
CPU time 0.71 seconds
Started Sep 04 06:11:22 AM UTC 24
Finished Sep 04 06:11:24 AM UTC 24
Peak memory 225000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216093349 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2216093349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.976969219
Short name T141
Test name
Test status
Simulation time 32421209 ps
CPU time 1.4 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976969219 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.976969219 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.612809347
Short name T727
Test name
Test status
Simulation time 33201432 ps
CPU time 0.73 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:11 AM UTC 24
Peak memory 223332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612809347 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.612809347 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2451848702
Short name T152
Test name
Test status
Simulation time 183648979 ps
CPU time 1.4 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451848702 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.2451848702 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3889014795
Short name T117
Test name
Test status
Simulation time 79829205 ps
CPU time 1.59 seconds
Started Sep 04 06:11:02 AM UTC 24
Finished Sep 04 06:11:12 AM UTC 24
Peak memory 224336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889014795 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3889
014795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.2957856591
Short name T135
Test name
Test status
Simulation time 128762523 ps
CPU time 3.03 seconds
Started Sep 04 06:11:22 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957856591 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.2957856591 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.117146501
Short name T126
Test name
Test status
Simulation time 209213677 ps
CPU time 2.39 seconds
Started Sep 04 06:11:22 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117146501 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.117146501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1315410255
Short name T792
Test name
Test status
Simulation time 75186242 ps
CPU time 2.2 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1315410255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem
_rw_with_rand_reset.1315410255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.817654206
Short name T784
Test name
Test status
Simulation time 32324578 ps
CPU time 1.19 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817654206 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.817654206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.1439457732
Short name T777
Test name
Test status
Simulation time 42335108 ps
CPU time 0.76 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439457732 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.1439457732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3076437399
Short name T789
Test name
Test status
Simulation time 63018864 ps
CPU time 1.61 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076437399 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3076437399 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3996887736
Short name T770
Test name
Test status
Simulation time 85661797 ps
CPU time 1.03 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:43 AM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996887736 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.3996887736 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2570783241
Short name T775
Test name
Test status
Simulation time 193082430 ps
CPU time 2.57 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570783241 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.257
0783241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.2561471158
Short name T773
Test name
Test status
Simulation time 38620370 ps
CPU time 1.63 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:44 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561471158 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2561471158 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3048652270
Short name T793
Test name
Test status
Simulation time 105814520 ps
CPU time 2.58 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 225652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048652270 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3048652270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4209737797
Short name T794
Test name
Test status
Simulation time 91394753 ps
CPU time 2.24 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 227600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4209737797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem
_rw_with_rand_reset.4209737797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3464444535
Short name T783
Test name
Test status
Simulation time 19313207 ps
CPU time 0.94 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464444535 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3464444535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.4251728270
Short name T778
Test name
Test status
Simulation time 15842286 ps
CPU time 0.79 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251728270 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.4251728270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1729807314
Short name T787
Test name
Test status
Simulation time 35296435 ps
CPU time 1.41 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729807314 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.1729807314 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2800110540
Short name T781
Test name
Test status
Simulation time 49656577 ps
CPU time 1.15 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 224272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800110540 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.2800110540 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.3874030145
Short name T798
Test name
Test status
Simulation time 1559183272 ps
CPU time 3.42 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:48 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874030145 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3874030145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.932269652
Short name T796
Test name
Test status
Simulation time 223895479 ps
CPU time 2.81 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 225572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932269652 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.932269652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.4154727250
Short name T820
Test name
Test status
Simulation time 298638069 ps
CPU time 2.29 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 231464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4154727250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem
_rw_with_rand_reset.4154727250 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.3913508879
Short name T786
Test name
Test status
Simulation time 39356319 ps
CPU time 1.1 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913508879 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3913508879 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1205358601
Short name T785
Test name
Test status
Simulation time 41385490 ps
CPU time 0.81 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205358601 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1205358601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.90804543
Short name T795
Test name
Test status
Simulation time 99189339 ps
CPU time 2.34 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90804543 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.90804543 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2173361913
Short name T788
Test name
Test status
Simulation time 132710054 ps
CPU time 1.33 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173361913 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.2173361913 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.485054410
Short name T791
Test name
Test status
Simulation time 55938440 ps
CPU time 1.49 seconds
Started Sep 04 06:11:43 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 228472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485054410 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.4850
54410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1994669047
Short name T790
Test name
Test status
Simulation time 187409431 ps
CPU time 1.47 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:46 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994669047 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1994669047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.445961134
Short name T179
Test name
Test status
Simulation time 90646999 ps
CPU time 2.2 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:47 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445961134 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.445961134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3682500203
Short name T802
Test name
Test status
Simulation time 133983387 ps
CPU time 1.67 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:49 AM UTC 24
Peak memory 226544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3682500203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem
_rw_with_rand_reset.3682500203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.156560685
Short name T800
Test name
Test status
Simulation time 28738922 ps
CPU time 1.28 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:48 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156560685 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.156560685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2918222333
Short name T797
Test name
Test status
Simulation time 71388160 ps
CPU time 0.83 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:48 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918222333 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2918222333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1504943672
Short name T804
Test name
Test status
Simulation time 125098347 ps
CPU time 2.44 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:49 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504943672 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1504943672 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3667177998
Short name T806
Test name
Test status
Simulation time 47487508 ps
CPU time 1.04 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:53 AM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667177998 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3667177998 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1688786978
Short name T810
Test name
Test status
Simulation time 43311886 ps
CPU time 1.51 seconds
Started Sep 04 06:11:44 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 228536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688786978 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.168
8786978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2140343420
Short name T801
Test name
Test status
Simulation time 34065406 ps
CPU time 1.77 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:49 AM UTC 24
Peak memory 224560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140343420 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2140343420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.976010337
Short name T779
Test name
Test status
Simulation time 27025667 ps
CPU time 1.34 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 228528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=976010337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_
rw_with_rand_reset.976010337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.4280806709
Short name T831
Test name
Test status
Simulation time 28423286 ps
CPU time 1.07 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 224308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280806709 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.4280806709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1173718770
Short name T828
Test name
Test status
Simulation time 43276401 ps
CPU time 0.86 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173718770 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1173718770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3652888405
Short name T854
Test name
Test status
Simulation time 888769872 ps
CPU time 1.67 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652888405 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3652888405 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2260384525
Short name T799
Test name
Test status
Simulation time 28891705 ps
CPU time 1.08 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:48 AM UTC 24
Peak memory 224432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260384525 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2260384525 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2100562170
Short name T832
Test name
Test status
Simulation time 125361477 ps
CPU time 1.46 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100562170 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.210
0562170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.3858771703
Short name T833
Test name
Test status
Simulation time 127377585 ps
CPU time 1.85 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858771703 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3858771703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1886726692
Short name T834
Test name
Test status
Simulation time 82933268 ps
CPU time 2.19 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886726692 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1886726692 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2745707116
Short name T805
Test name
Test status
Simulation time 137183444 ps
CPU time 2.13 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:52 AM UTC 24
Peak memory 231700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2745707116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem
_rw_with_rand_reset.2745707116 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.75660967
Short name T811
Test name
Test status
Simulation time 15607555 ps
CPU time 0.84 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75660967 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.75660967 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.3391801270
Short name T813
Test name
Test status
Simulation time 13898367 ps
CPU time 1.05 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391801270 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3391801270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1378466135
Short name T826
Test name
Test status
Simulation time 82296994 ps
CPU time 2.28 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378466135 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1378466135 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3330614602
Short name T850
Test name
Test status
Simulation time 105260459 ps
CPU time 1.21 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330614602 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3330614602 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.3393164608
Short name T835
Test name
Test status
Simulation time 43519115 ps
CPU time 2.13 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:11:57 AM UTC 24
Peak memory 225488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393164608 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.339
3164608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3211166082
Short name T856
Test name
Test status
Simulation time 142657266 ps
CPU time 1.99 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211166082 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3211166082 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.3667967230
Short name T861
Test name
Test status
Simulation time 219622725 ps
CPU time 4.01 seconds
Started Sep 04 06:11:46 AM UTC 24
Finished Sep 04 06:12:02 AM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667967230 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3667967230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3503672194
Short name T827
Test name
Test status
Simulation time 293516039 ps
CPU time 2.18 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 231676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3503672194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem
_rw_with_rand_reset.3503672194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3477049592
Short name T817
Test name
Test status
Simulation time 36238703 ps
CPU time 1.09 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477049592 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3477049592 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.2849406553
Short name T812
Test name
Test status
Simulation time 13896340 ps
CPU time 0.9 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849406553 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2849406553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.4095080812
Short name T823
Test name
Test status
Simulation time 37768746 ps
CPU time 1.94 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095080812 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.4095080812 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3022010398
Short name T818
Test name
Test status
Simulation time 93975319 ps
CPU time 1.2 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 226420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022010398 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.3022010398 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1843077397
Short name T822
Test name
Test status
Simulation time 131899619 ps
CPU time 1.64 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843077397 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.184
3077397 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1021063782
Short name T825
Test name
Test status
Simulation time 40712951 ps
CPU time 2.21 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 225556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021063782 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1021063782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2241203368
Short name T824
Test name
Test status
Simulation time 102412155 ps
CPU time 2.07 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241203368 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2241203368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.4234867082
Short name T809
Test name
Test status
Simulation time 23978621 ps
CPU time 1.42 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 230424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4234867082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem
_rw_with_rand_reset.4234867082 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3308028510
Short name T807
Test name
Test status
Simulation time 208249909 ps
CPU time 1.01 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:53 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308028510 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3308028510 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2330580947
Short name T816
Test name
Test status
Simulation time 46974345 ps
CPU time 0.76 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330580947 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2330580947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3353060402
Short name T815
Test name
Test status
Simulation time 62449138 ps
CPU time 1.7 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353060402 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.3353060402 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2327037724
Short name T819
Test name
Test status
Simulation time 92859024 ps
CPU time 1.11 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327037724 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2327037724 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.869509923
Short name T830
Test name
Test status
Simulation time 187099034 ps
CPU time 2.4 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869509923 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.8695
09923 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.3049609328
Short name T836
Test name
Test status
Simulation time 1896280163 ps
CPU time 3.8 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:57 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049609328 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3049609328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1318570068
Short name T177
Test name
Test status
Simulation time 523749618 ps
CPU time 2.94 seconds
Started Sep 04 06:11:49 AM UTC 24
Finished Sep 04 06:11:56 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318570068 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1318570068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2336961446
Short name T857
Test name
Test status
Simulation time 37844703 ps
CPU time 2.12 seconds
Started Sep 04 06:11:55 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 231696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2336961446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem
_rw_with_rand_reset.2336961446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.322335848
Short name T846
Test name
Test status
Simulation time 54056704 ps
CPU time 1.02 seconds
Started Sep 04 06:11:55 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322335848 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.322335848 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.341812206
Short name T829
Test name
Test status
Simulation time 28135223 ps
CPU time 1.09 seconds
Started Sep 04 06:11:53 AM UTC 24
Finished Sep 04 06:11:55 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341812206 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.341812206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1776346358
Short name T858
Test name
Test status
Simulation time 37428923 ps
CPU time 2.33 seconds
Started Sep 04 06:11:55 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776346358 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.1776346358 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1746794561
Short name T808
Test name
Test status
Simulation time 112849858 ps
CPU time 1.33 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746794561 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.1746794561 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2085437956
Short name T821
Test name
Test status
Simulation time 167569358 ps
CPU time 2.06 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 225940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085437956 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.208
5437956 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3035795356
Short name T814
Test name
Test status
Simulation time 353806463 ps
CPU time 1.58 seconds
Started Sep 04 06:11:51 AM UTC 24
Finished Sep 04 06:11:54 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035795356 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3035795356 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.3231978992
Short name T844
Test name
Test status
Simulation time 98425384 ps
CPU time 3.73 seconds
Started Sep 04 06:11:53 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231978992 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3231978992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.189594786
Short name T855
Test name
Test status
Simulation time 153107613 ps
CPU time 2.46 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=189594786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_
rw_with_rand_reset.189594786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.860027625
Short name T853
Test name
Test status
Simulation time 42219537 ps
CPU time 1.2 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860027625 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.860027625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1231436777
Short name T849
Test name
Test status
Simulation time 17371140 ps
CPU time 0.93 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231436777 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1231436777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.541142426
Short name T845
Test name
Test status
Simulation time 428164486 ps
CPU time 1.73 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541142426 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.541142426 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1569056140
Short name T852
Test name
Test status
Simulation time 95220159 ps
CPU time 1.16 seconds
Started Sep 04 06:11:55 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569056140 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.1569056140 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.944264538
Short name T859
Test name
Test status
Simulation time 466312379 ps
CPU time 2.73 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944264538 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.9442
64538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.777060415
Short name T860
Test name
Test status
Simulation time 109745832 ps
CPU time 2.73 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777060415 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.777060415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.2298807074
Short name T178
Test name
Test status
Simulation time 53825320 ps
CPU time 2.52 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:12:00 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298807074 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2298807074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.1290570916
Short name T155
Test name
Test status
Simulation time 892088487 ps
CPU time 4.48 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:30 AM UTC 24
Peak memory 225456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290570916 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.1290570916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.820486652
Short name T780
Test name
Test status
Simulation time 1521534618 ps
CPU time 19.48 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820486652 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.820486652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3682109471
Short name T734
Test name
Test status
Simulation time 15325362 ps
CPU time 0.9 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682109471 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3682109471 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2621823839
Short name T153
Test name
Test status
Simulation time 476011219 ps
CPU time 1.71 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 226604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2621823839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_
rw_with_rand_reset.2621823839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3593423722
Short name T735
Test name
Test status
Simulation time 46138156 ps
CPU time 1.13 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593423722 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3593423722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2938585833
Short name T142
Test name
Test status
Simulation time 29656376 ps
CPU time 1.19 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938585833 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2938585833 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2247735612
Short name T733
Test name
Test status
Simulation time 68763579 ps
CPU time 0.87 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247735612 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2247735612 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.1077866574
Short name T741
Test name
Test status
Simulation time 174590869 ps
CPU time 2.16 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 225660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077866574 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.1077866574 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1495324891
Short name T111
Test name
Test status
Simulation time 86350754 ps
CPU time 0.98 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:26 AM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495324891 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1495324891 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1946590007
Short name T740
Test name
Test status
Simulation time 100284286 ps
CPU time 2.29 seconds
Started Sep 04 06:11:23 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946590007 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1946590007 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3871879015
Short name T851
Test name
Test status
Simulation time 21309208 ps
CPU time 0.87 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871879015 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3871879015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.74043081
Short name T848
Test name
Test status
Simulation time 14869477 ps
CPU time 0.75 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:59 AM UTC 24
Peak memory 224248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74043081 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.74043081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.3469512495
Short name T837
Test name
Test status
Simulation time 22011160 ps
CPU time 0.76 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:57 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469512495 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3469512495 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2381610712
Short name T838
Test name
Test status
Simulation time 20778639 ps
CPU time 0.69 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381610712 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2381610712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3626403066
Short name T839
Test name
Test status
Simulation time 16937185 ps
CPU time 0.71 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626403066 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3626403066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.220036989
Short name T840
Test name
Test status
Simulation time 41551094 ps
CPU time 0.7 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220036989 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.220036989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.340595163
Short name T842
Test name
Test status
Simulation time 51565188 ps
CPU time 0.8 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340595163 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.340595163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.3712829316
Short name T843
Test name
Test status
Simulation time 136125674 ps
CPU time 0.76 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712829316 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3712829316 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2948529307
Short name T841
Test name
Test status
Simulation time 36772401 ps
CPU time 0.75 seconds
Started Sep 04 06:11:56 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 224600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948529307 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2948529307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.4236103068
Short name T871
Test name
Test status
Simulation time 43928483 ps
CPU time 0.96 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236103068 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4236103068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.4166093654
Short name T782
Test name
Test status
Simulation time 726849324 ps
CPU time 8.29 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166093654 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.4166093654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.3302533695
Short name T744
Test name
Test status
Simulation time 1315542740 ps
CPU time 6.81 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:33 AM UTC 24
Peak memory 225464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302533695 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3302533695 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2255177446
Short name T738
Test name
Test status
Simulation time 101838721 ps
CPU time 1.1 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255177446 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2255177446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2016531351
Short name T739
Test name
Test status
Simulation time 23108274 ps
CPU time 1.51 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2016531351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_
rw_with_rand_reset.2016531351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.2758180151
Short name T737
Test name
Test status
Simulation time 33345976 ps
CPU time 1.05 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758180151 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2758180151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2300445757
Short name T164
Test name
Test status
Simulation time 23024987 ps
CPU time 0.88 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 225024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300445757 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2300445757 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1873674984
Short name T143
Test name
Test status
Simulation time 18486916 ps
CPU time 1.49 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873674984 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.1873674984 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.1592896998
Short name T736
Test name
Test status
Simulation time 15819009 ps
CPU time 0.87 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592896998 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1592896998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3014292429
Short name T743
Test name
Test status
Simulation time 297218979 ps
CPU time 1.85 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:29 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014292429 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.3014292429 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3143499083
Short name T118
Test name
Test status
Simulation time 148805571 ps
CPU time 1.05 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:27 AM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143499083 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3143499083 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1533684735
Short name T108
Test name
Test status
Simulation time 75320164 ps
CPU time 1.89 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 228472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533684735 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.1533
684735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.3635006608
Short name T742
Test name
Test status
Simulation time 141832089 ps
CPU time 2.34 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:28 AM UTC 24
Peak memory 225552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635006608 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3635006608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.2360233943
Short name T874
Test name
Test status
Simulation time 19971608 ps
CPU time 1.05 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360233943 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2360233943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3927631519
Short name T865
Test name
Test status
Simulation time 23437491 ps
CPU time 0.75 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927631519 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3927631519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.417469238
Short name T869
Test name
Test status
Simulation time 16797622 ps
CPU time 0.88 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417469238 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.417469238 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.2343328751
Short name T868
Test name
Test status
Simulation time 17192651 ps
CPU time 0.85 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343328751 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2343328751 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1844569959
Short name T876
Test name
Test status
Simulation time 33268515 ps
CPU time 1.04 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844569959 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1844569959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.998363051
Short name T877
Test name
Test status
Simulation time 13874383 ps
CPU time 1.08 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998363051 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.998363051 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1490769323
Short name T880
Test name
Test status
Simulation time 29671364 ps
CPU time 1.13 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490769323 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1490769323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2039062237
Short name T867
Test name
Test status
Simulation time 19607792 ps
CPU time 0.96 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039062237 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2039062237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.1410877726
Short name T881
Test name
Test status
Simulation time 39817548 ps
CPU time 1.01 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410877726 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.1410877726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2945259151
Short name T866
Test name
Test status
Simulation time 10287001 ps
CPU time 0.87 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945259151 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2945259151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3152843438
Short name T803
Test name
Test status
Simulation time 5164386536 ps
CPU time 9.99 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:49 AM UTC 24
Peak memory 225544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152843438 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3152843438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3561773816
Short name T847
Test name
Test status
Simulation time 2888507532 ps
CPU time 19.08 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:58 AM UTC 24
Peak memory 225452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561773816 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3561773816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.179564755
Short name T753
Test name
Test status
Simulation time 42093337 ps
CPU time 1 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179564755 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.179564755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3843847519
Short name T749
Test name
Test status
Simulation time 92927356 ps
CPU time 1.69 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 230528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3843847519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_
rw_with_rand_reset.3843847519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.3108792506
Short name T752
Test name
Test status
Simulation time 77088642 ps
CPU time 1.02 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108792506 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3108792506 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.303854135
Short name T163
Test name
Test status
Simulation time 44485084 ps
CPU time 0.97 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 224848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303854135 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.303854135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.3483845470
Short name T144
Test name
Test status
Simulation time 20640860 ps
CPU time 1.23 seconds
Started Sep 04 06:11:25 AM UTC 24
Finished Sep 04 06:11:37 AM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483845470 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.3483845470 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.2076392946
Short name T748
Test name
Test status
Simulation time 27079123 ps
CPU time 0.64 seconds
Started Sep 04 06:11:25 AM UTC 24
Finished Sep 04 06:11:38 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076392946 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2076392946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3445585048
Short name T759
Test name
Test status
Simulation time 75837455 ps
CPU time 1.92 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 224580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445585048 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3445585048 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1624058244
Short name T114
Test name
Test status
Simulation time 74281141 ps
CPU time 0.97 seconds
Started Sep 04 06:11:24 AM UTC 24
Finished Sep 04 06:11:38 AM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624058244 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1624058244 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.1041816189
Short name T760
Test name
Test status
Simulation time 504887404 ps
CPU time 2.46 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 225528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041816189 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1041816189 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.60090150
Short name T180
Test name
Test status
Simulation time 448060283 ps
CPU time 2.72 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60090150 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.60090150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.4215137355
Short name T873
Test name
Test status
Simulation time 15423607 ps
CPU time 0.92 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215137355 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.4215137355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3889999974
Short name T870
Test name
Test status
Simulation time 14826877 ps
CPU time 0.89 seconds
Started Sep 04 06:11:58 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889999974 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3889999974 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2642328361
Short name T875
Test name
Test status
Simulation time 33971189 ps
CPU time 0.93 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642328361 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2642328361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.1912889543
Short name T872
Test name
Test status
Simulation time 11321311 ps
CPU time 0.77 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912889543 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1912889543 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3024551154
Short name T862
Test name
Test status
Simulation time 54368369 ps
CPU time 0.89 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:08 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024551154 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3024551154 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.2008237483
Short name T878
Test name
Test status
Simulation time 35227536 ps
CPU time 0.8 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008237483 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2008237483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2826652686
Short name T882
Test name
Test status
Simulation time 54698322 ps
CPU time 0.91 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826652686 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2826652686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.60095468
Short name T879
Test name
Test status
Simulation time 15744587 ps
CPU time 0.77 seconds
Started Sep 04 06:11:59 AM UTC 24
Finished Sep 04 06:12:11 AM UTC 24
Peak memory 224644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60095468 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.60095468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.212038093
Short name T863
Test name
Test status
Simulation time 20888661 ps
CPU time 0.74 seconds
Started Sep 04 06:12:01 AM UTC 24
Finished Sep 04 06:12:09 AM UTC 24
Peak memory 224492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212038093 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.212038093 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2490891382
Short name T864
Test name
Test status
Simulation time 19837565 ps
CPU time 0.79 seconds
Started Sep 04 06:12:01 AM UTC 24
Finished Sep 04 06:12:10 AM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490891382 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2490891382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1285899443
Short name T745
Test name
Test status
Simulation time 401243203 ps
CPU time 2.01 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:34 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1285899443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_
rw_with_rand_reset.1285899443 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.1938672295
Short name T756
Test name
Test status
Simulation time 28488120 ps
CPU time 1.3 seconds
Started Sep 04 06:11:28 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 224552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938672295 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1938672295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.830890869
Short name T166
Test name
Test status
Simulation time 50733869 ps
CPU time 1.08 seconds
Started Sep 04 06:11:28 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 224908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830890869 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.830890869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3355864817
Short name T156
Test name
Test status
Simulation time 185629582 ps
CPU time 1.4 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:33 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355864817 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.3355864817 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1736032924
Short name T182
Test name
Test status
Simulation time 52626555 ps
CPU time 1.33 seconds
Started Sep 04 06:11:27 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736032924 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1736032924 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.4034317360
Short name T183
Test name
Test status
Simulation time 112692099 ps
CPU time 1.71 seconds
Started Sep 04 06:11:28 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034317360 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.4034
317360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.2534346604
Short name T761
Test name
Test status
Simulation time 434703010 ps
CPU time 2.44 seconds
Started Sep 04 06:11:28 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 225608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534346604 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.2534346604 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3894362634
Short name T766
Test name
Test status
Simulation time 512535388 ps
CPU time 2.66 seconds
Started Sep 04 06:11:28 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 225476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894362634 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3894362634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3860867859
Short name T762
Test name
Test status
Simulation time 152635088 ps
CPU time 1.97 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 231540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3860867859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_
rw_with_rand_reset.3860867859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.1487120507
Short name T755
Test name
Test status
Simulation time 34617694 ps
CPU time 1.21 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 224344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487120507 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.1487120507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3905365050
Short name T165
Test name
Test status
Simulation time 13440023 ps
CPU time 0.73 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:33 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905365050 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3905365050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1659504861
Short name T764
Test name
Test status
Simulation time 71124616 ps
CPU time 2.09 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 225600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659504861 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.1659504861 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.914288988
Short name T116
Test name
Test status
Simulation time 90108980 ps
CPU time 0.94 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:33 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914288988 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.914288988 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3384243934
Short name T113
Test name
Test status
Simulation time 136508426 ps
CPU time 2.45 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:34 AM UTC 24
Peak memory 230060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384243934 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.3384
243934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1698545654
Short name T746
Test name
Test status
Simulation time 131186621 ps
CPU time 2.88 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:35 AM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698545654 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1698545654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1049950891
Short name T754
Test name
Test status
Simulation time 47097405 ps
CPU time 1.42 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 228592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1049950891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_
rw_with_rand_reset.1049950891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.1380047511
Short name T751
Test name
Test status
Simulation time 26832682 ps
CPU time 0.88 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:40 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380047511 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1380047511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1291894167
Short name T162
Test name
Test status
Simulation time 20119833 ps
CPU time 0.66 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:39 AM UTC 24
Peak memory 224584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291894167 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1291894167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3881986924
Short name T763
Test name
Test status
Simulation time 461009452 ps
CPU time 2.68 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 225472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881986924 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3881986924 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2354507624
Short name T109
Test name
Test status
Simulation time 20421185 ps
CPU time 1.09 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354507624 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2354507624 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1993946355
Short name T758
Test name
Test status
Simulation time 127341980 ps
CPU time 1.6 seconds
Started Sep 04 06:11:30 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993946355 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.1993
946355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1923620243
Short name T767
Test name
Test status
Simulation time 103933402 ps
CPU time 1.64 seconds
Started Sep 04 06:11:32 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923620243 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1923620243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.1741155279
Short name T174
Test name
Test status
Simulation time 198943622 ps
CPU time 2.63 seconds
Started Sep 04 06:11:32 AM UTC 24
Finished Sep 04 06:11:43 AM UTC 24
Peak memory 225548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741155279 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.1741155279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2987390656
Short name T768
Test name
Test status
Simulation time 481169380 ps
CPU time 2.13 seconds
Started Sep 04 06:11:39 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2987390656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_
rw_with_rand_reset.2987390656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.1861848361
Short name T750
Test name
Test status
Simulation time 24235031 ps
CPU time 0.9 seconds
Started Sep 04 06:11:36 AM UTC 24
Finished Sep 04 06:11:39 AM UTC 24
Peak memory 224556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861848361 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1861848361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.3646132735
Short name T161
Test name
Test status
Simulation time 42635875 ps
CPU time 0.68 seconds
Started Sep 04 06:11:36 AM UTC 24
Finished Sep 04 06:11:39 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646132735 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3646132735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.4224031177
Short name T765
Test name
Test status
Simulation time 40058022 ps
CPU time 1.96 seconds
Started Sep 04 06:11:38 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224031177 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.4224031177 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1141785755
Short name T119
Test name
Test status
Simulation time 63468991 ps
CPU time 0.77 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:37 AM UTC 24
Peak memory 224432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141785755 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.1141785755 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3344658641
Short name T757
Test name
Test status
Simulation time 31192905 ps
CPU time 1.66 seconds
Started Sep 04 06:11:34 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344658641 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.3344
658641 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.479435220
Short name T134
Test name
Test status
Simulation time 187516773 ps
CPU time 2.51 seconds
Started Sep 04 06:11:36 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479435220 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.479435220 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.698438191
Short name T175
Test name
Test status
Simulation time 105817604 ps
CPU time 3.07 seconds
Started Sep 04 06:11:36 AM UTC 24
Finished Sep 04 06:11:41 AM UTC 24
Peak memory 225664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698438191 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.698438191 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3005939764
Short name T774
Test name
Test status
Simulation time 141280965 ps
CPU time 2.2 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:44 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3005939764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_
rw_with_rand_reset.3005939764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1449325748
Short name T769
Test name
Test status
Simulation time 28812748 ps
CPU time 0.99 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:43 AM UTC 24
Peak memory 224496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449325748 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1449325748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3070921250
Short name T772
Test name
Test status
Simulation time 247049440 ps
CPU time 1.66 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:44 AM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070921250 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3070921250 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.999321535
Short name T112
Test name
Test status
Simulation time 30506442 ps
CPU time 1.5 seconds
Started Sep 04 06:11:39 AM UTC 24
Finished Sep 04 06:11:42 AM UTC 24
Peak memory 226328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999321535 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.999321535 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.4016935978
Short name T771
Test name
Test status
Simulation time 334583451 ps
CPU time 3.19 seconds
Started Sep 04 06:11:39 AM UTC 24
Finished Sep 04 06:11:43 AM UTC 24
Peak memory 230000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016935978 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.4016
935978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.4150744928
Short name T776
Test name
Test status
Simulation time 438661529 ps
CPU time 3.05 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:45 AM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150744928 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.4150744928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3169587628
Short name T173
Test name
Test status
Simulation time 176710259 ps
CPU time 2.32 seconds
Started Sep 04 06:11:41 AM UTC 24
Finished Sep 04 06:11:44 AM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169587628 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3169587628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_app.2321974681
Short name T10
Test name
Test status
Simulation time 1816509333 ps
CPU time 36.03 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:23:19 AM UTC 24
Peak memory 258444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321974681 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2321974681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.742019773
Short name T16
Test name
Test status
Simulation time 148019467371 ps
CPU time 266.57 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:27:12 AM UTC 24
Peak memory 461420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742019773 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.742019773 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.3519977347
Short name T145
Test name
Test status
Simulation time 19138294649 ps
CPU time 361.02 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 06:28:42 AM UTC 24
Peak memory 252132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519977347 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3519977347 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3325836812
Short name T4
Test name
Test status
Simulation time 7892255362 ps
CPU time 23.03 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:23:06 AM UTC 24
Peak memory 236204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325836812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3325836812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1367704929
Short name T216
Test name
Test status
Simulation time 60301690188 ps
CPU time 695.88 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 06:34:21 AM UTC 24
Peak memory 571992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367704929 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1367704929 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.193577836
Short name T32
Test name
Test status
Simulation time 15680703209 ps
CPU time 407.7 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:29:34 AM UTC 24
Peak memory 541552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193577836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.193577836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.973757948
Short name T24
Test name
Test status
Simulation time 18384154310 ps
CPU time 252.01 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 06:26:52 AM UTC 24
Peak memory 311444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973757948 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.973757948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.2158452660
Short name T87
Test name
Test status
Simulation time 4850747502 ps
CPU time 95.76 seconds
Started Sep 04 06:22:28 AM UTC 24
Finished Sep 04 06:24:06 AM UTC 24
Peak memory 236072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158452660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2158452660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.4105539739
Short name T434
Test name
Test status
Simulation time 499490125669 ps
CPU time 3052.88 seconds
Started Sep 04 06:22:33 AM UTC 24
Finished Sep 04 07:14:03 AM UTC 24
Peak memory 1323556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105539739 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.4105539739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.2307916229
Short name T52
Test name
Test status
Simulation time 10738620655 ps
CPU time 250.46 seconds
Started Sep 04 06:22:33 AM UTC 24
Finished Sep 04 06:26:50 AM UTC 24
Peak memory 266860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2307916229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r
and_reset.2307916229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.548297426
Short name T12
Test name
Test status
Simulation time 85598806 ps
CPU time 4.32 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:47 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548297426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.548297426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.2218331498
Short name T11
Test name
Test status
Simulation time 892977664 ps
CPU time 4.28 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:46 AM UTC 24
Peak memory 230020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218331498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2218331498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.715832893
Short name T432
Test name
Test status
Simulation time 326916607456 ps
CPU time 3035.06 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 07:13:45 AM UTC 24
Peak memory 3121596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715832893 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.715832893 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2911251620
Short name T305
Test name
Test status
Simulation time 36300678124 ps
CPU time 1878.89 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 06:54:17 AM UTC 24
Peak memory 1147332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911251620 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2911251620 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.704314521
Short name T281
Test name
Test status
Simulation time 26205044005 ps
CPU time 1662.98 seconds
Started Sep 04 06:22:29 AM UTC 24
Finished Sep 04 06:50:39 AM UTC 24
Peak memory 909768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704314521 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.704314521 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2554692639
Short name T13
Test name
Test status
Simulation time 1075286191 ps
CPU time 20.15 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:22:52 AM UTC 24
Peak memory 234036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554692639 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2554692639 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3184208809
Short name T99
Test name
Test status
Simulation time 16053954575 ps
CPU time 286.07 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 06:27:31 AM UTC 24
Peak memory 283168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184208809 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3184208809 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.901108131
Short name T385
Test name
Test status
Simulation time 60880354510 ps
CPU time 2529.51 seconds
Started Sep 04 06:22:31 AM UTC 24
Finished Sep 04 07:05:20 AM UTC 24
Peak memory 2953680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901108131 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.901108131 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.642884146
Short name T48
Test name
Test status
Simulation time 17029268 ps
CPU time 1.28 seconds
Started Sep 04 06:23:23 AM UTC 24
Finished Sep 04 06:23:26 AM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642884146 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.642884146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_app.135421324
Short name T120
Test name
Test status
Simulation time 83590523579 ps
CPU time 361.87 seconds
Started Sep 04 06:22:49 AM UTC 24
Finished Sep 04 06:28:56 AM UTC 24
Peak memory 543312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135421324 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.135421324 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.2163207676
Short name T148
Test name
Test status
Simulation time 20359387613 ps
CPU time 884.9 seconds
Started Sep 04 06:22:35 AM UTC 24
Finished Sep 04 06:37:37 AM UTC 24
Peak memory 248360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163207676 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2163207676 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.408829980
Short name T26
Test name
Test status
Simulation time 6051439895 ps
CPU time 49.67 seconds
Started Sep 04 06:23:10 AM UTC 24
Finished Sep 04 06:24:01 AM UTC 24
Peak memory 246204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408829980 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.408829980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.4141170
Short name T50
Test name
Test status
Simulation time 346304923 ps
CPU time 24.74 seconds
Started Sep 04 06:23:10 AM UTC 24
Finished Sep 04 06:23:36 AM UTC 24
Peak memory 235880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +U
VM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.4141170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.3162615485
Short name T14
Test name
Test status
Simulation time 3960678828 ps
CPU time 32.37 seconds
Started Sep 04 06:22:55 AM UTC 24
Finished Sep 04 06:23:28 AM UTC 24
Peak memory 236156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162615485 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3162615485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_error.3825235702
Short name T23
Test name
Test status
Simulation time 775757559 ps
CPU time 37.05 seconds
Started Sep 04 06:23:01 AM UTC 24
Finished Sep 04 06:23:39 AM UTC 24
Peak memory 251912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825235702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3825235702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.220871151
Short name T8
Test name
Test status
Simulation time 411758653 ps
CPU time 2.73 seconds
Started Sep 04 06:23:07 AM UTC 24
Finished Sep 04 06:23:11 AM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220871151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.220871151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.1073914055
Short name T18
Test name
Test status
Simulation time 34331232 ps
CPU time 2.2 seconds
Started Sep 04 06:23:12 AM UTC 24
Finished Sep 04 06:23:15 AM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073914055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1073914055 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2037386907
Short name T270
Test name
Test status
Simulation time 14350647626 ps
CPU time 1525.72 seconds
Started Sep 04 06:22:35 AM UTC 24
Finished Sep 04 06:48:24 AM UTC 24
Peak memory 1030696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037386907 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2037386907 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.2329691049
Short name T33
Test name
Test status
Simulation time 12359869695 ps
CPU time 401.74 seconds
Started Sep 04 06:22:55 AM UTC 24
Finished Sep 04 06:29:42 AM UTC 24
Peak memory 373620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329691049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2329691049 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.1406960171
Short name T41
Test name
Test status
Simulation time 35180550987 ps
CPU time 120.89 seconds
Started Sep 04 06:23:20 AM UTC 24
Finished Sep 04 06:25:23 AM UTC 24
Peak memory 311088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406960171 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1406960171 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.791128920
Short name T46
Test name
Test status
Simulation time 89074996 ps
CPU time 4.4 seconds
Started Sep 04 06:22:47 AM UTC 24
Finished Sep 04 06:22:53 AM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791128920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.791128920 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3927786840
Short name T30
Test name
Test status
Simulation time 301813675 ps
CPU time 4.17 seconds
Started Sep 04 06:22:47 AM UTC 24
Finished Sep 04 06:22:52 AM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927786840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3927786840 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1770436435
Short name T47
Test name
Test status
Simulation time 49712547549 ps
CPU time 45.73 seconds
Started Sep 04 06:22:35 AM UTC 24
Finished Sep 04 06:23:23 AM UTC 24
Peak memory 260648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770436435 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1770436435 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2292058118
Short name T53
Test name
Test status
Simulation time 7869873875 ps
CPU time 60.05 seconds
Started Sep 04 06:22:39 AM UTC 24
Finished Sep 04 06:23:44 AM UTC 24
Peak memory 256452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292058118 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2292058118 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.3429084652
Short name T291
Test name
Test status
Simulation time 53460337166 ps
CPU time 1754.33 seconds
Started Sep 04 06:22:42 AM UTC 24
Finished Sep 04 06:52:18 AM UTC 24
Peak memory 922060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429084652 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3429084652 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2236062991
Short name T45
Test name
Test status
Simulation time 2724151774 ps
CPU time 25.81 seconds
Started Sep 04 06:22:42 AM UTC 24
Finished Sep 04 06:23:09 AM UTC 24
Peak memory 234164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236062991 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2236062991 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.3054555419
Short name T186
Test name
Test status
Simulation time 6691964586 ps
CPU time 125.13 seconds
Started Sep 04 06:22:45 AM UTC 24
Finished Sep 04 06:24:53 AM UTC 24
Peak memory 362968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054555419 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3054555419 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.57538473
Short name T265
Test name
Test status
Simulation time 136763972 ps
CPU time 1.27 seconds
Started Sep 04 06:47:20 AM UTC 24
Finished Sep 04 06:47:23 AM UTC 24
Peak memory 226596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57538473 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.57538473 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_app.2322416009
Short name T264
Test name
Test status
Simulation time 2346208561 ps
CPU time 41.02 seconds
Started Sep 04 06:46:39 AM UTC 24
Finished Sep 04 06:47:21 AM UTC 24
Peak memory 240164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322416009 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2322416009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.331643631
Short name T290
Test name
Test status
Simulation time 6925669089 ps
CPU time 321.84 seconds
Started Sep 04 06:46:34 AM UTC 24
Finished Sep 04 06:52:01 AM UTC 24
Peak memory 244396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331643631 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.331643631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.4145407774
Short name T71
Test name
Test status
Simulation time 114402117 ps
CPU time 1.7 seconds
Started Sep 04 06:47:06 AM UTC 24
Finished Sep 04 06:47:09 AM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145407774 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.4145407774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.2199409146
Short name T262
Test name
Test status
Simulation time 38359266 ps
CPU time 1.72 seconds
Started Sep 04 06:47:09 AM UTC 24
Finished Sep 04 06:47:12 AM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199409146 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2199409146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2216842198
Short name T267
Test name
Test status
Simulation time 4939544091 ps
CPU time 62.9 seconds
Started Sep 04 06:46:40 AM UTC 24
Finished Sep 04 06:47:44 AM UTC 24
Peak memory 262692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216842198 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2216842198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_error.2857409749
Short name T272
Test name
Test status
Simulation time 5194116022 ps
CPU time 90.29 seconds
Started Sep 04 06:47:05 AM UTC 24
Finished Sep 04 06:48:37 AM UTC 24
Peak memory 279068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857409749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2857409749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.557147725
Short name T263
Test name
Test status
Simulation time 16196500628 ps
CPU time 13.28 seconds
Started Sep 04 06:47:05 AM UTC 24
Finished Sep 04 06:47:19 AM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557147725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.557147725 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.693980389
Short name T421
Test name
Test status
Simulation time 160157070779 ps
CPU time 1478.6 seconds
Started Sep 04 06:46:27 AM UTC 24
Finished Sep 04 07:11:24 AM UTC 24
Peak memory 1688160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693980389 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.693980389 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.1299519860
Short name T280
Test name
Test status
Simulation time 19137725094 ps
CPU time 179.55 seconds
Started Sep 04 06:46:32 AM UTC 24
Finished Sep 04 06:49:35 AM UTC 24
Peak memory 367116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299519860 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1299519860 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.3878915462
Short name T266
Test name
Test status
Simulation time 10867576244 ps
CPU time 64.08 seconds
Started Sep 04 06:46:24 AM UTC 24
Finished Sep 04 06:47:30 AM UTC 24
Peak memory 236136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878915462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3878915462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.3663274899
Short name T412
Test name
Test status
Simulation time 49789484581 ps
CPU time 1305.63 seconds
Started Sep 04 06:47:16 AM UTC 24
Finished Sep 04 07:09:16 AM UTC 24
Peak memory 1121196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663274899 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3663274899 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.220302295
Short name T275
Test name
Test status
Simulation time 20354959 ps
CPU time 1.31 seconds
Started Sep 04 06:48:47 AM UTC 24
Finished Sep 04 06:48:49 AM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220302295 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.220302295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_app.1048446488
Short name T278
Test name
Test status
Simulation time 15141857593 ps
CPU time 68.26 seconds
Started Sep 04 06:47:45 AM UTC 24
Finished Sep 04 06:48:55 AM UTC 24
Peak memory 283240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048446488 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1048446488 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.3778445505
Short name T344
Test name
Test status
Simulation time 30077730464 ps
CPU time 728.66 seconds
Started Sep 04 06:47:31 AM UTC 24
Finished Sep 04 06:59:48 AM UTC 24
Peak memory 256612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778445505 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3778445505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.316232565
Short name T277
Test name
Test status
Simulation time 2123341369 ps
CPU time 25.38 seconds
Started Sep 04 06:48:26 AM UTC 24
Finished Sep 04 06:48:53 AM UTC 24
Peak memory 235872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316232565 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.316232565 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.4162721677
Short name T273
Test name
Test status
Simulation time 14149327 ps
CPU time 1.31 seconds
Started Sep 04 06:48:38 AM UTC 24
Finished Sep 04 06:48:41 AM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162721677 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.4162721677 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.4182264303
Short name T317
Test name
Test status
Simulation time 19743503222 ps
CPU time 472.76 seconds
Started Sep 04 06:47:59 AM UTC 24
Finished Sep 04 06:55:58 AM UTC 24
Peak memory 350892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182264303 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4182264303 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_error.1432402132
Short name T304
Test name
Test status
Simulation time 60778872327 ps
CPU time 351.61 seconds
Started Sep 04 06:48:17 AM UTC 24
Finished Sep 04 06:54:13 AM UTC 24
Peak memory 529064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432402132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1432402132 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.380379757
Short name T274
Test name
Test status
Simulation time 2185851019 ps
CPU time 19.08 seconds
Started Sep 04 06:48:25 AM UTC 24
Finished Sep 04 06:48:45 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380379757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.380379757 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.980120427
Short name T384
Test name
Test status
Simulation time 23168850815 ps
CPU time 1051.83 seconds
Started Sep 04 06:47:23 AM UTC 24
Finished Sep 04 07:05:07 AM UTC 24
Peak memory 1245792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980120427 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.980120427 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.3895055844
Short name T301
Test name
Test status
Simulation time 8858636398 ps
CPU time 375.32 seconds
Started Sep 04 06:47:24 AM UTC 24
Finished Sep 04 06:53:44 AM UTC 24
Peak memory 459432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895055844 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3895055844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.3155120319
Short name T271
Test name
Test status
Simulation time 2329390953 ps
CPU time 63.05 seconds
Started Sep 04 06:47:20 AM UTC 24
Finished Sep 04 06:48:25 AM UTC 24
Peak memory 236240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155120319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3155120319 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1649009139
Short name T330
Test name
Test status
Simulation time 5065401605 ps
CPU time 508.04 seconds
Started Sep 04 06:48:45 AM UTC 24
Finished Sep 04 06:57:20 AM UTC 24
Peak memory 492124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649009139 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1649009139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.2340126249
Short name T287
Test name
Test status
Simulation time 56772425 ps
CPU time 1.3 seconds
Started Sep 04 06:51:41 AM UTC 24
Finished Sep 04 06:51:44 AM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340126249 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2340126249 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2049556203
Short name T292
Test name
Test status
Simulation time 10656607056 ps
CPU time 200.43 seconds
Started Sep 04 06:49:00 AM UTC 24
Finished Sep 04 06:52:24 AM UTC 24
Peak memory 289448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049556203 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2049556203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.4088866775
Short name T352
Test name
Test status
Simulation time 12634677261 ps
CPU time 773.49 seconds
Started Sep 04 06:48:56 AM UTC 24
Finished Sep 04 07:01:59 AM UTC 24
Peak memory 244324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088866775 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.4088866775 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.652137633
Short name T288
Test name
Test status
Simulation time 654398710 ps
CPU time 60.05 seconds
Started Sep 04 06:50:49 AM UTC 24
Finished Sep 04 06:51:50 AM UTC 24
Peak memory 237832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652137633 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.652137633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.3585030957
Short name T284
Test name
Test status
Simulation time 578713912 ps
CPU time 19.31 seconds
Started Sep 04 06:51:07 AM UTC 24
Finished Sep 04 06:51:27 AM UTC 24
Peak memory 244208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585030957 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3585030957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2206863133
Short name T286
Test name
Test status
Simulation time 23040413825 ps
CPU time 126.93 seconds
Started Sep 04 06:49:31 AM UTC 24
Finished Sep 04 06:51:41 AM UTC 24
Peak memory 262832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206863133 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2206863133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_error.37619042
Short name T289
Test name
Test status
Simulation time 17098110108 ps
CPU time 139.13 seconds
Started Sep 04 06:49:35 AM UTC 24
Finished Sep 04 06:51:57 AM UTC 24
Peak memory 344684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37619042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.37619042 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.2335497855
Short name T282
Test name
Test status
Simulation time 749581580 ps
CPU time 6.69 seconds
Started Sep 04 06:50:41 AM UTC 24
Finished Sep 04 06:50:48 AM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335497855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2335497855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.1283472770
Short name T285
Test name
Test status
Simulation time 127645546 ps
CPU time 2 seconds
Started Sep 04 06:51:28 AM UTC 24
Finished Sep 04 06:51:31 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283472770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1283472770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.2287102090
Short name T629
Test name
Test status
Simulation time 88563349520 ps
CPU time 4042.22 seconds
Started Sep 04 06:48:50 AM UTC 24
Finished Sep 04 07:56:54 AM UTC 24
Peak memory 4125392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287102090 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.2287102090 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.2505795656
Short name T303
Test name
Test status
Simulation time 5118635430 ps
CPU time 312.45 seconds
Started Sep 04 06:48:54 AM UTC 24
Finished Sep 04 06:54:10 AM UTC 24
Peak memory 354916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505795656 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2505795656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.2003810921
Short name T279
Test name
Test status
Simulation time 6640561680 ps
CPU time 8.03 seconds
Started Sep 04 06:48:50 AM UTC 24
Finished Sep 04 06:48:59 AM UTC 24
Peak memory 234296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003810921 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2003810921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.1734991542
Short name T296
Test name
Test status
Simulation time 1410569312 ps
CPU time 81.43 seconds
Started Sep 04 06:51:32 AM UTC 24
Finished Sep 04 06:52:56 AM UTC 24
Peak memory 285432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734991542 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1734991542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.47211032
Short name T299
Test name
Test status
Simulation time 46314516 ps
CPU time 1.28 seconds
Started Sep 04 06:53:03 AM UTC 24
Finished Sep 04 06:53:06 AM UTC 24
Peak memory 227924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47211032 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.47211032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_app.1886029904
Short name T322
Test name
Test status
Simulation time 9184308468 ps
CPU time 255.6 seconds
Started Sep 04 06:52:19 AM UTC 24
Finished Sep 04 06:56:38 AM UTC 24
Peak memory 309932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886029904 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1886029904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.3041572230
Short name T393
Test name
Test status
Simulation time 17193474642 ps
CPU time 882.33 seconds
Started Sep 04 06:52:02 AM UTC 24
Finished Sep 04 07:06:55 AM UTC 24
Peak memory 252448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041572230 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3041572230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.857051015
Short name T300
Test name
Test status
Simulation time 476868299 ps
CPU time 42.41 seconds
Started Sep 04 06:52:55 AM UTC 24
Finished Sep 04 06:53:39 AM UTC 24
Peak memory 246064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857051015 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.857051015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1580650526
Short name T297
Test name
Test status
Simulation time 31088372 ps
CPU time 1.71 seconds
Started Sep 04 06:52:56 AM UTC 24
Finished Sep 04 06:52:59 AM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580650526 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1580650526 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.4250440028
Short name T68
Test name
Test status
Simulation time 8489452858 ps
CPU time 323.67 seconds
Started Sep 04 06:52:25 AM UTC 24
Finished Sep 04 06:57:53 AM UTC 24
Peak memory 317972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250440028 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.4250440028 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_error.3970778193
Short name T337
Test name
Test status
Simulation time 127648046217 ps
CPU time 358.16 seconds
Started Sep 04 06:52:25 AM UTC 24
Finished Sep 04 06:58:28 AM UTC 24
Peak memory 449040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970778193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3970778193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.162574293
Short name T295
Test name
Test status
Simulation time 782530742 ps
CPU time 6.14 seconds
Started Sep 04 06:52:47 AM UTC 24
Finished Sep 04 06:52:54 AM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162574293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.162574293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.3596526647
Short name T60
Test name
Test status
Simulation time 167777856 ps
CPU time 1.95 seconds
Started Sep 04 06:52:59 AM UTC 24
Finished Sep 04 06:53:02 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596526647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3596526647 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.3624648151
Short name T293
Test name
Test status
Simulation time 883800809 ps
CPU time 31.05 seconds
Started Sep 04 06:51:51 AM UTC 24
Finished Sep 04 06:52:24 AM UTC 24
Peak memory 254452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624648151 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.3624648151 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.1309799161
Short name T306
Test name
Test status
Simulation time 6455530496 ps
CPU time 145.16 seconds
Started Sep 04 06:51:58 AM UTC 24
Finished Sep 04 06:54:25 AM UTC 24
Peak memory 287328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309799161 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1309799161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.3131451240
Short name T298
Test name
Test status
Simulation time 5624288367 ps
CPU time 74.67 seconds
Started Sep 04 06:51:44 AM UTC 24
Finished Sep 04 06:53:01 AM UTC 24
Peak memory 236068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131451240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3131451240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.596977904
Short name T416
Test name
Test status
Simulation time 13710432397 ps
CPU time 1047.96 seconds
Started Sep 04 06:53:02 AM UTC 24
Finished Sep 04 07:10:42 AM UTC 24
Peak memory 311912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596977904 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.596977904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.3791128607
Short name T311
Test name
Test status
Simulation time 232471654 ps
CPU time 1.28 seconds
Started Sep 04 06:54:41 AM UTC 24
Finished Sep 04 06:54:43 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791128607 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3791128607 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_app.140226818
Short name T312
Test name
Test status
Simulation time 705330477 ps
CPU time 61.12 seconds
Started Sep 04 06:54:11 AM UTC 24
Finished Sep 04 06:55:14 AM UTC 24
Peak memory 248384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140226818 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.140226818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.3827943926
Short name T425
Test name
Test status
Simulation time 13001088257 ps
CPU time 1070.62 seconds
Started Sep 04 06:54:02 AM UTC 24
Finished Sep 04 07:12:06 AM UTC 24
Peak memory 250468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827943926 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3827943926 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.1366571403
Short name T308
Test name
Test status
Simulation time 495082868 ps
CPU time 1.95 seconds
Started Sep 04 06:54:26 AM UTC 24
Finished Sep 04 06:54:29 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366571403 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1366571403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.4050934841
Short name T309
Test name
Test status
Simulation time 181564638 ps
CPU time 1.88 seconds
Started Sep 04 06:54:30 AM UTC 24
Finished Sep 04 06:54:33 AM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050934841 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.4050934841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.975823223
Short name T324
Test name
Test status
Simulation time 7041716271 ps
CPU time 146.09 seconds
Started Sep 04 06:54:14 AM UTC 24
Finished Sep 04 06:56:43 AM UTC 24
Peak memory 277160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975823223 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.975823223 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_error.2941730518
Short name T355
Test name
Test status
Simulation time 10713253937 ps
CPU time 470.96 seconds
Started Sep 04 06:54:17 AM UTC 24
Finished Sep 04 07:02:14 AM UTC 24
Peak memory 387600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941730518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2941730518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.48936068
Short name T310
Test name
Test status
Simulation time 963602719 ps
CPU time 12.59 seconds
Started Sep 04 06:54:26 AM UTC 24
Finished Sep 04 06:54:40 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48936068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.48936068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1024916752
Short name T362
Test name
Test status
Simulation time 21368213277 ps
CPU time 556.32 seconds
Started Sep 04 06:53:40 AM UTC 24
Finished Sep 04 07:03:03 AM UTC 24
Peak memory 535144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024916752 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1024916752 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.2332912362
Short name T313
Test name
Test status
Simulation time 3841105019 ps
CPU time 92.94 seconds
Started Sep 04 06:53:45 AM UTC 24
Finished Sep 04 06:55:20 AM UTC 24
Peak memory 311892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332912362 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2332912362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3022711031
Short name T302
Test name
Test status
Simulation time 21792761239 ps
CPU time 53.29 seconds
Started Sep 04 06:53:07 AM UTC 24
Finished Sep 04 06:54:01 AM UTC 24
Peak memory 236132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022711031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3022711031 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.2386358968
Short name T348
Test name
Test status
Simulation time 18895256947 ps
CPU time 353.45 seconds
Started Sep 04 06:54:38 AM UTC 24
Finished Sep 04 07:00:36 AM UTC 24
Peak memory 326584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386358968 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2386358968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.3568344687
Short name T323
Test name
Test status
Simulation time 17893259 ps
CPU time 1.29 seconds
Started Sep 04 06:56:39 AM UTC 24
Finished Sep 04 06:56:41 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568344687 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3568344687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_app.2109028911
Short name T338
Test name
Test status
Simulation time 4469533150 ps
CPU time 171.23 seconds
Started Sep 04 06:55:35 AM UTC 24
Finished Sep 04 06:58:29 AM UTC 24
Peak memory 283288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109028911 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2109028911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.3825244199
Short name T477
Test name
Test status
Simulation time 14688801118 ps
CPU time 1582.62 seconds
Started Sep 04 06:55:21 AM UTC 24
Finished Sep 04 07:22:02 AM UTC 24
Peak memory 256604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825244199 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3825244199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1300155906
Short name T327
Test name
Test status
Simulation time 571657565 ps
CPU time 56.85 seconds
Started Sep 04 06:56:11 AM UTC 24
Finished Sep 04 06:57:10 AM UTC 24
Peak memory 246056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300155906 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1300155906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3370174138
Short name T320
Test name
Test status
Simulation time 54166942 ps
CPU time 1.07 seconds
Started Sep 04 06:56:13 AM UTC 24
Finished Sep 04 06:56:15 AM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370174138 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3370174138 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1923434646
Short name T326
Test name
Test status
Simulation time 9545650348 ps
CPU time 80.54 seconds
Started Sep 04 06:55:36 AM UTC 24
Finished Sep 04 06:56:59 AM UTC 24
Peak memory 270880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923434646 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1923434646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_error.2093709670
Short name T319
Test name
Test status
Simulation time 363627114 ps
CPU time 15.15 seconds
Started Sep 04 06:55:55 AM UTC 24
Finished Sep 04 06:56:12 AM UTC 24
Peak memory 248276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093709670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2093709670 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.263675589
Short name T318
Test name
Test status
Simulation time 720803711 ps
CPU time 10.5 seconds
Started Sep 04 06:55:59 AM UTC 24
Finished Sep 04 06:56:11 AM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263675589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.263675589 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.3847658620
Short name T321
Test name
Test status
Simulation time 494365640 ps
CPU time 2.19 seconds
Started Sep 04 06:56:16 AM UTC 24
Finished Sep 04 06:56:19 AM UTC 24
Peak memory 231980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847658620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3847658620 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.817490836
Short name T315
Test name
Test status
Simulation time 723264411 ps
CPU time 30.63 seconds
Started Sep 04 06:55:03 AM UTC 24
Finished Sep 04 06:55:35 AM UTC 24
Peak memory 256480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817490836 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.817490836 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.3473480062
Short name T335
Test name
Test status
Simulation time 6194340599 ps
CPU time 160.07 seconds
Started Sep 04 06:55:15 AM UTC 24
Finished Sep 04 06:57:58 AM UTC 24
Peak memory 367324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473480062 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3473480062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.892679382
Short name T325
Test name
Test status
Simulation time 15111849807 ps
CPU time 132.29 seconds
Started Sep 04 06:54:44 AM UTC 24
Finished Sep 04 06:56:58 AM UTC 24
Peak memory 238112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892679382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.892679382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.4292675241
Short name T504
Test name
Test status
Simulation time 278918241861 ps
CPU time 1808.81 seconds
Started Sep 04 06:56:20 AM UTC 24
Finished Sep 04 07:26:49 AM UTC 24
Peak memory 1006128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292675241 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.4292675241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.682317499
Short name T334
Test name
Test status
Simulation time 46079904 ps
CPU time 1.3 seconds
Started Sep 04 06:57:54 AM UTC 24
Finished Sep 04 06:57:56 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682317499 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.682317499 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_app.313416892
Short name T367
Test name
Test status
Simulation time 4927603537 ps
CPU time 405.62 seconds
Started Sep 04 06:57:11 AM UTC 24
Finished Sep 04 07:04:03 AM UTC 24
Peak memory 344680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313416892 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.313416892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.588043135
Short name T371
Test name
Test status
Simulation time 50197072053 ps
CPU time 431.27 seconds
Started Sep 04 06:56:59 AM UTC 24
Finished Sep 04 07:04:16 AM UTC 24
Peak memory 246308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588043135 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.588043135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.3461143969
Short name T333
Test name
Test status
Simulation time 754724204 ps
CPU time 18.52 seconds
Started Sep 04 06:57:27 AM UTC 24
Finished Sep 04 06:57:46 AM UTC 24
Peak memory 231928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461143969 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3461143969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2010888167
Short name T336
Test name
Test status
Simulation time 455057046 ps
CPU time 31.95 seconds
Started Sep 04 06:57:36 AM UTC 24
Finished Sep 04 06:58:09 AM UTC 24
Peak memory 235804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010888167 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2010888167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.607627060
Short name T340
Test name
Test status
Simulation time 4578470615 ps
CPU time 113.37 seconds
Started Sep 04 06:57:18 AM UTC 24
Finished Sep 04 06:59:14 AM UTC 24
Peak memory 258596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607627060 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.607627060 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_error.4200671165
Short name T373
Test name
Test status
Simulation time 16118024362 ps
CPU time 414.87 seconds
Started Sep 04 06:57:20 AM UTC 24
Finished Sep 04 07:04:21 AM UTC 24
Peak memory 350904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200671165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.4200671165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.3522223438
Short name T332
Test name
Test status
Simulation time 971094005 ps
CPU time 12.26 seconds
Started Sep 04 06:57:21 AM UTC 24
Finished Sep 04 06:57:35 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522223438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3522223438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.2395576421
Short name T40
Test name
Test status
Simulation time 36681509 ps
CPU time 2.34 seconds
Started Sep 04 06:57:47 AM UTC 24
Finished Sep 04 06:57:50 AM UTC 24
Peak memory 231980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395576421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2395576421 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.460579543
Short name T699
Test name
Test status
Simulation time 116876058208 ps
CPU time 4364.63 seconds
Started Sep 04 06:56:44 AM UTC 24
Finished Sep 04 08:10:15 AM UTC 24
Peak memory 4375244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460579543 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.460579543 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.3031220111
Short name T365
Test name
Test status
Simulation time 8001481870 ps
CPU time 408.8 seconds
Started Sep 04 06:56:59 AM UTC 24
Finished Sep 04 07:03:54 AM UTC 24
Peak memory 346676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031220111 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3031220111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.376790848
Short name T328
Test name
Test status
Simulation time 1406504522 ps
CPU time 34.54 seconds
Started Sep 04 06:56:42 AM UTC 24
Finished Sep 04 06:57:18 AM UTC 24
Peak memory 236048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376790848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.376790848 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.797405768
Short name T345
Test name
Test status
Simulation time 14228675 ps
CPU time 1.23 seconds
Started Sep 04 06:59:49 AM UTC 24
Finished Sep 04 06:59:51 AM UTC 24
Peak memory 225220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797405768 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.797405768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_app.1349239660
Short name T350
Test name
Test status
Simulation time 2606887584 ps
CPU time 175.89 seconds
Started Sep 04 06:58:29 AM UTC 24
Finished Sep 04 07:01:29 AM UTC 24
Peak memory 279144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349239660 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1349239660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.1180385170
Short name T473
Test name
Test status
Simulation time 113696794886 ps
CPU time 1354.35 seconds
Started Sep 04 06:58:10 AM UTC 24
Finished Sep 04 07:21:00 AM UTC 24
Peak memory 264708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180385170 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1180385170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.3607100857
Short name T342
Test name
Test status
Simulation time 253846514 ps
CPU time 7.56 seconds
Started Sep 04 06:59:25 AM UTC 24
Finished Sep 04 06:59:33 AM UTC 24
Peak memory 232008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607100857 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3607100857 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.68879959
Short name T343
Test name
Test status
Simulation time 30053864 ps
CPU time 1.45 seconds
Started Sep 04 06:59:34 AM UTC 24
Finished Sep 04 06:59:36 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68879959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +
UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.68879959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.725915851
Short name T339
Test name
Test status
Simulation time 1759938857 ps
CPU time 33.84 seconds
Started Sep 04 06:58:30 AM UTC 24
Finished Sep 04 06:59:06 AM UTC 24
Peak memory 246232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725915851 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.725915851 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.835160623
Short name T341
Test name
Test status
Simulation time 1150976096 ps
CPU time 7.86 seconds
Started Sep 04 06:59:15 AM UTC 24
Finished Sep 04 06:59:24 AM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835160623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.835160623 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.2267104212
Short name T452
Test name
Test status
Simulation time 59010897578 ps
CPU time 1126.39 seconds
Started Sep 04 06:57:58 AM UTC 24
Finished Sep 04 07:16:58 AM UTC 24
Peak memory 1260204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267104212 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.2267104212 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.1758550882
Short name T364
Test name
Test status
Simulation time 37856292598 ps
CPU time 312.32 seconds
Started Sep 04 06:58:00 AM UTC 24
Finished Sep 04 07:03:17 AM UTC 24
Peak memory 471648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758550882 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.1758550882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.1907024323
Short name T486
Test name
Test status
Simulation time 57797798017 ps
CPU time 1427.83 seconds
Started Sep 04 06:59:41 AM UTC 24
Finished Sep 04 07:23:46 AM UTC 24
Peak memory 514964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907024323 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1907024323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.1850430641
Short name T359
Test name
Test status
Simulation time 105791659 ps
CPU time 1.24 seconds
Started Sep 04 07:02:19 AM UTC 24
Finished Sep 04 07:02:21 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850430641 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1850430641 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_app.2744362208
Short name T396
Test name
Test status
Simulation time 65940794460 ps
CPU time 422.94 seconds
Started Sep 04 07:00:40 AM UTC 24
Finished Sep 04 07:07:50 AM UTC 24
Peak memory 473696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744362208 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2744362208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.1863854865
Short name T394
Test name
Test status
Simulation time 5182759632 ps
CPU time 377.9 seconds
Started Sep 04 07:00:38 AM UTC 24
Finished Sep 04 07:07:02 AM UTC 24
Peak memory 242248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863854865 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1863854865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.3658633418
Short name T360
Test name
Test status
Simulation time 7975390850 ps
CPU time 46.36 seconds
Started Sep 04 07:02:06 AM UTC 24
Finished Sep 04 07:02:54 AM UTC 24
Peak memory 245972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658633418 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3658633418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.3114419130
Short name T357
Test name
Test status
Simulation time 36006662 ps
CPU time 1.87 seconds
Started Sep 04 07:02:15 AM UTC 24
Finished Sep 04 07:02:18 AM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114419130 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3114419130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.360724846
Short name T363
Test name
Test status
Simulation time 3452585314 ps
CPU time 95.32 seconds
Started Sep 04 07:01:30 AM UTC 24
Finished Sep 04 07:03:08 AM UTC 24
Peak memory 283296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360724846 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.360724846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3280771938
Short name T375
Test name
Test status
Simulation time 3346678207 ps
CPU time 166.74 seconds
Started Sep 04 07:01:37 AM UTC 24
Finished Sep 04 07:04:27 AM UTC 24
Peak memory 287404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280771938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3280771938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.1269835802
Short name T353
Test name
Test status
Simulation time 230044401 ps
CPU time 3.82 seconds
Started Sep 04 07:02:00 AM UTC 24
Finished Sep 04 07:02:05 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269835802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1269835802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.3874047747
Short name T358
Test name
Test status
Simulation time 26945240 ps
CPU time 1.39 seconds
Started Sep 04 07:02:16 AM UTC 24
Finished Sep 04 07:02:18 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874047747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3874047747 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1162814340
Short name T450
Test name
Test status
Simulation time 49550403333 ps
CPU time 988.88 seconds
Started Sep 04 07:00:06 AM UTC 24
Finished Sep 04 07:16:46 AM UTC 24
Peak memory 1360492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162814340 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1162814340 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.4126516988
Short name T366
Test name
Test status
Simulation time 12819011158 ps
CPU time 210.34 seconds
Started Sep 04 07:00:27 AM UTC 24
Finished Sep 04 07:04:02 AM UTC 24
Peak memory 291496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126516988 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.4126516988 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.3754465573
Short name T349
Test name
Test status
Simulation time 938750375 ps
CPU time 44.89 seconds
Started Sep 04 06:59:52 AM UTC 24
Finished Sep 04 07:00:39 AM UTC 24
Peak memory 232092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754465573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.3754465573 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.4088565529
Short name T487
Test name
Test status
Simulation time 31174510615 ps
CPU time 1308.2 seconds
Started Sep 04 07:02:18 AM UTC 24
Finished Sep 04 07:24:21 AM UTC 24
Peak memory 951220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088565529 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.4088565529 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.1464599344
Short name T372
Test name
Test status
Simulation time 89422505 ps
CPU time 1.35 seconds
Started Sep 04 07:04:15 AM UTC 24
Finished Sep 04 07:04:18 AM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464599344 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1464599344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1887704754
Short name T401
Test name
Test status
Simulation time 53926718702 ps
CPU time 309.67 seconds
Started Sep 04 07:03:04 AM UTC 24
Finished Sep 04 07:08:18 AM UTC 24
Peak memory 455208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887704754 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1887704754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.4270652779
Short name T521
Test name
Test status
Simulation time 52274837643 ps
CPU time 1612.85 seconds
Started Sep 04 07:02:58 AM UTC 24
Finished Sep 04 07:30:10 AM UTC 24
Peak memory 256540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270652779 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.4270652779 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.460433415
Short name T374
Test name
Test status
Simulation time 8951158944 ps
CPU time 19.41 seconds
Started Sep 04 07:04:03 AM UTC 24
Finished Sep 04 07:04:24 AM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460433415 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.460433415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2988993418
Short name T368
Test name
Test status
Simulation time 171522179 ps
CPU time 1.64 seconds
Started Sep 04 07:04:04 AM UTC 24
Finished Sep 04 07:04:07 AM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988993418 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2988993418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.4138089108
Short name T377
Test name
Test status
Simulation time 6432906833 ps
CPU time 87.56 seconds
Started Sep 04 07:03:08 AM UTC 24
Finished Sep 04 07:04:38 AM UTC 24
Peak memory 254640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138089108 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.4138089108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_error.3035606637
Short name T379
Test name
Test status
Simulation time 8896190630 ps
CPU time 83.58 seconds
Started Sep 04 07:03:17 AM UTC 24
Finished Sep 04 07:04:43 AM UTC 24
Peak memory 301608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035606637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.3035606637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.309857454
Short name T370
Test name
Test status
Simulation time 2401014549 ps
CPU time 18.37 seconds
Started Sep 04 07:03:55 AM UTC 24
Finished Sep 04 07:04:14 AM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309857454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.309857454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.946488095
Short name T369
Test name
Test status
Simulation time 123959338 ps
CPU time 2.08 seconds
Started Sep 04 07:04:08 AM UTC 24
Finished Sep 04 07:04:12 AM UTC 24
Peak memory 232064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946488095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.946488095 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1344221611
Short name T426
Test name
Test status
Simulation time 15763543276 ps
CPU time 577.23 seconds
Started Sep 04 07:02:22 AM UTC 24
Finished Sep 04 07:12:06 AM UTC 24
Peak memory 973424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344221611 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1344221611 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.3353398479
Short name T435
Test name
Test status
Simulation time 41110066419 ps
CPU time 664.05 seconds
Started Sep 04 07:02:55 AM UTC 24
Finished Sep 04 07:14:08 AM UTC 24
Peak memory 690784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353398479 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.3353398479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.3522702081
Short name T361
Test name
Test status
Simulation time 1527623338 ps
CPU time 37.31 seconds
Started Sep 04 07:02:19 AM UTC 24
Finished Sep 04 07:02:58 AM UTC 24
Peak memory 235976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522702081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3522702081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.3545007856
Short name T462
Test name
Test status
Simulation time 12919671049 ps
CPU time 898.75 seconds
Started Sep 04 07:04:12 AM UTC 24
Finished Sep 04 07:19:21 AM UTC 24
Peak memory 594880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545007856 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3545007856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.1239372469
Short name T122
Test name
Test status
Simulation time 14377355 ps
CPU time 1.24 seconds
Started Sep 04 06:26:09 AM UTC 24
Finished Sep 04 06:26:11 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239372469 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1239372469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_app.369666499
Short name T49
Test name
Test status
Simulation time 10603642098 ps
CPU time 90.49 seconds
Started Sep 04 06:24:35 AM UTC 24
Finished Sep 04 06:26:08 AM UTC 24
Peak memory 260700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369666499 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.369666499 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.1025433257
Short name T34
Test name
Test status
Simulation time 5061476031 ps
CPU time 164.44 seconds
Started Sep 04 06:24:37 AM UTC 24
Finished Sep 04 06:27:24 AM UTC 24
Peak memory 324116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025433257 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1025433257 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.867179418
Short name T149
Test name
Test status
Simulation time 20564125141 ps
CPU time 922.91 seconds
Started Sep 04 06:23:36 AM UTC 24
Finished Sep 04 06:39:10 AM UTC 24
Peak memory 260652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867179418 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.867179418 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2815019757
Short name T102
Test name
Test status
Simulation time 263430277 ps
CPU time 17.84 seconds
Started Sep 04 06:25:28 AM UTC 24
Finished Sep 04 06:25:47 AM UTC 24
Peak memory 252252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815019757 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2815019757 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2139167179
Short name T74
Test name
Test status
Simulation time 39834356 ps
CPU time 1.31 seconds
Started Sep 04 06:25:34 AM UTC 24
Finished Sep 04 06:25:37 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139167179 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2139167179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1884685272
Short name T6
Test name
Test status
Simulation time 4492710031 ps
CPU time 68.69 seconds
Started Sep 04 06:25:38 AM UTC 24
Finished Sep 04 06:26:49 AM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884685272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1884685272 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.2553532981
Short name T76
Test name
Test status
Simulation time 61720515592 ps
CPU time 356.11 seconds
Started Sep 04 06:24:52 AM UTC 24
Finished Sep 04 06:30:53 AM UTC 24
Peak memory 492140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553532981 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2553532981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.344635601
Short name T17
Test name
Test status
Simulation time 2768994184 ps
CPU time 6.01 seconds
Started Sep 04 06:25:26 AM UTC 24
Finished Sep 04 06:25:33 AM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344635601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.344635601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.845802520
Short name T43
Test name
Test status
Simulation time 87478306 ps
CPU time 1.94 seconds
Started Sep 04 06:25:48 AM UTC 24
Finished Sep 04 06:25:51 AM UTC 24
Peak memory 233636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845802520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.845802520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2376248173
Short name T248
Test name
Test status
Simulation time 103742909522 ps
CPU time 1323.56 seconds
Started Sep 04 06:23:27 AM UTC 24
Finished Sep 04 06:45:47 AM UTC 24
Peak memory 1378848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376248173 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2376248173 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.4047236636
Short name T31
Test name
Test status
Simulation time 3281111411 ps
CPU time 144.09 seconds
Started Sep 04 06:24:53 AM UTC 24
Finished Sep 04 06:27:20 AM UTC 24
Peak memory 283512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047236636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.4047236636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.4273517685
Short name T42
Test name
Test status
Simulation time 13703290127 ps
CPU time 60.97 seconds
Started Sep 04 06:25:59 AM UTC 24
Finished Sep 04 06:27:01 AM UTC 24
Peak memory 278324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273517685 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4273517685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.199643851
Short name T103
Test name
Test status
Simulation time 7856275732 ps
CPU time 146.07 seconds
Started Sep 04 06:23:29 AM UTC 24
Finished Sep 04 06:25:58 AM UTC 24
Peak memory 334436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199643851 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.199643851 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.3839841904
Short name T170
Test name
Test status
Simulation time 1515509886 ps
CPU time 54.53 seconds
Started Sep 04 06:23:26 AM UTC 24
Finished Sep 04 06:24:22 AM UTC 24
Peak memory 235984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839841904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3839841904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.553995794
Short name T346
Test name
Test status
Simulation time 156436878915 ps
CPU time 2028.79 seconds
Started Sep 04 06:25:52 AM UTC 24
Finished Sep 04 07:00:04 AM UTC 24
Peak memory 1352616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553995794 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.553995794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.2683205034
Short name T195
Test name
Test status
Simulation time 379383545 ps
CPU time 3.42 seconds
Started Sep 04 06:24:26 AM UTC 24
Finished Sep 04 06:24:30 AM UTC 24
Peak memory 230080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683205034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.2683205034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.1021450338
Short name T196
Test name
Test status
Simulation time 80592011 ps
CPU time 3.93 seconds
Started Sep 04 06:24:31 AM UTC 24
Finished Sep 04 06:24:36 AM UTC 24
Peak memory 230080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021450338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1021450338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2254652076
Short name T54
Test name
Test status
Simulation time 2475142405 ps
CPU time 53.39 seconds
Started Sep 04 06:23:38 AM UTC 24
Finished Sep 04 06:24:34 AM UTC 24
Peak memory 235540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254652076 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2254652076 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.335415265
Short name T413
Test name
Test status
Simulation time 75823832597 ps
CPU time 2724.75 seconds
Started Sep 04 06:23:40 AM UTC 24
Finished Sep 04 07:09:35 AM UTC 24
Peak memory 2980420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335415265 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.335415265 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1873943279
Short name T347
Test name
Test status
Simulation time 114093484550 ps
CPU time 2177.24 seconds
Started Sep 04 06:23:45 AM UTC 24
Finished Sep 04 07:00:27 AM UTC 24
Peak memory 2382280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873943279 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1873943279 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1041208464
Short name T194
Test name
Test status
Simulation time 1201436306 ps
CPU time 22.46 seconds
Started Sep 04 06:24:02 AM UTC 24
Finished Sep 04 06:24:26 AM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041208464 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1041208464 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.3499407645
Short name T187
Test name
Test status
Simulation time 14611258664 ps
CPU time 169.46 seconds
Started Sep 04 06:24:07 AM UTC 24
Finished Sep 04 06:26:59 AM UTC 24
Peak memory 291276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499407645 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3499407645 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2942617545
Short name T351
Test name
Test status
Simulation time 60333451522 ps
CPU time 2209.83 seconds
Started Sep 04 06:24:23 AM UTC 24
Finished Sep 04 07:01:36 AM UTC 24
Peak memory 3060228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942617545 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2942617545 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.368705723
Short name T382
Test name
Test status
Simulation time 15972301 ps
CPU time 1.33 seconds
Started Sep 04 07:04:46 AM UTC 24
Finished Sep 04 07:04:48 AM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368705723 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.368705723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_app.3226143234
Short name T386
Test name
Test status
Simulation time 986077352 ps
CPU time 63.79 seconds
Started Sep 04 07:04:25 AM UTC 24
Finished Sep 04 07:05:30 AM UTC 24
Peak memory 252492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226143234 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3226143234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.2262730634
Short name T380
Test name
Test status
Simulation time 140301331 ps
CPU time 20.8 seconds
Started Sep 04 07:04:22 AM UTC 24
Finished Sep 04 07:04:45 AM UTC 24
Peak memory 234100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262730634 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2262730634 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.3242911662
Short name T354
Test name
Test status
Simulation time 51111499291 ps
CPU time 377.58 seconds
Started Sep 04 07:04:28 AM UTC 24
Finished Sep 04 07:10:50 AM UTC 24
Peak memory 342640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242911662 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3242911662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_error.3096733874
Short name T399
Test name
Test status
Simulation time 14774511164 ps
CPU time 207.15 seconds
Started Sep 04 07:04:29 AM UTC 24
Finished Sep 04 07:07:59 AM UTC 24
Peak memory 303724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096733874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.3096733874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.2249454575
Short name T378
Test name
Test status
Simulation time 305261680 ps
CPU time 2.42 seconds
Started Sep 04 07:04:39 AM UTC 24
Finished Sep 04 07:04:42 AM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249454575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2249454575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.3416989157
Short name T381
Test name
Test status
Simulation time 237402002 ps
CPU time 2.8 seconds
Started Sep 04 07:04:43 AM UTC 24
Finished Sep 04 07:04:47 AM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416989157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3416989157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2639435627
Short name T681
Test name
Test status
Simulation time 388218129628 ps
CPU time 3593.66 seconds
Started Sep 04 07:04:18 AM UTC 24
Finished Sep 04 08:04:52 AM UTC 24
Peak memory 3523184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639435627 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2639435627 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.24528296
Short name T388
Test name
Test status
Simulation time 4076534686 ps
CPU time 120.52 seconds
Started Sep 04 07:04:18 AM UTC 24
Finished Sep 04 07:06:21 AM UTC 24
Peak memory 264740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24528296 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.24528296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.678348939
Short name T383
Test name
Test status
Simulation time 10819378982 ps
CPU time 44.15 seconds
Started Sep 04 07:04:17 AM UTC 24
Finished Sep 04 07:05:03 AM UTC 24
Peak memory 236120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678348939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.678348939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2407211784
Short name T69
Test name
Test status
Simulation time 3492958811 ps
CPU time 92.93 seconds
Started Sep 04 07:04:44 AM UTC 24
Finished Sep 04 07:06:19 AM UTC 24
Peak memory 268864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407211784 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2407211784 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.741257436
Short name T390
Test name
Test status
Simulation time 19429312 ps
CPU time 1.31 seconds
Started Sep 04 07:06:27 AM UTC 24
Finished Sep 04 07:06:29 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741257436 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.741257436 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_app.2076829105
Short name T397
Test name
Test status
Simulation time 8629247925 ps
CPU time 148.74 seconds
Started Sep 04 07:05:20 AM UTC 24
Finished Sep 04 07:07:52 AM UTC 24
Peak memory 272968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076829105 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2076829105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3034466677
Short name T406
Test name
Test status
Simulation time 18564368737 ps
CPU time 202.29 seconds
Started Sep 04 07:05:08 AM UTC 24
Finished Sep 04 07:08:34 AM UTC 24
Peak memory 240288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034466677 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3034466677 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_error.131730429
Short name T407
Test name
Test status
Simulation time 7912042594 ps
CPU time 157.13 seconds
Started Sep 04 07:06:00 AM UTC 24
Finished Sep 04 07:08:40 AM UTC 24
Peak memory 301592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131730429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.131730429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2213046659
Short name T389
Test name
Test status
Simulation time 392647386 ps
CPU time 4.91 seconds
Started Sep 04 07:06:20 AM UTC 24
Finished Sep 04 07:06:26 AM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213046659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2213046659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.3689503092
Short name T63
Test name
Test status
Simulation time 122124828 ps
CPU time 1.92 seconds
Started Sep 04 07:06:22 AM UTC 24
Finished Sep 04 07:06:25 AM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689503092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3689503092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3641218808
Short name T686
Test name
Test status
Simulation time 190170753196 ps
CPU time 3664.78 seconds
Started Sep 04 07:04:49 AM UTC 24
Finished Sep 04 08:06:33 AM UTC 24
Peak memory 3768880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641218808 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3641218808 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.2047086867
Short name T392
Test name
Test status
Simulation time 4576785813 ps
CPU time 104.17 seconds
Started Sep 04 07:05:04 AM UTC 24
Finished Sep 04 07:06:51 AM UTC 24
Peak memory 264748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047086867 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2047086867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.1583282255
Short name T387
Test name
Test status
Simulation time 32648362053 ps
CPU time 70.34 seconds
Started Sep 04 07:04:47 AM UTC 24
Finished Sep 04 07:05:59 AM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583282255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.1583282255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.178648668
Short name T443
Test name
Test status
Simulation time 24420371427 ps
CPU time 561.9 seconds
Started Sep 04 07:06:26 AM UTC 24
Finished Sep 04 07:15:55 AM UTC 24
Peak memory 361384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178648668 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.178648668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.2217016898
Short name T400
Test name
Test status
Simulation time 15530848 ps
CPU time 1.3 seconds
Started Sep 04 07:08:00 AM UTC 24
Finished Sep 04 07:08:03 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217016898 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2217016898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_app.513602667
Short name T404
Test name
Test status
Simulation time 1355915076 ps
CPU time 77.11 seconds
Started Sep 04 07:07:03 AM UTC 24
Finished Sep 04 07:08:22 AM UTC 24
Peak memory 248264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513602667 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.513602667 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.745504214
Short name T395
Test name
Test status
Simulation time 271910869 ps
CPU time 18.57 seconds
Started Sep 04 07:06:56 AM UTC 24
Finished Sep 04 07:07:16 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745504214 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.745504214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1563122502
Short name T398
Test name
Test status
Simulation time 1005022154 ps
CPU time 37.63 seconds
Started Sep 04 07:07:16 AM UTC 24
Finished Sep 04 07:07:56 AM UTC 24
Peak memory 248240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563122502 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1563122502 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_error.3072850038
Short name T402
Test name
Test status
Simulation time 1524246301 ps
CPU time 28.57 seconds
Started Sep 04 07:07:51 AM UTC 24
Finished Sep 04 07:08:21 AM UTC 24
Peak memory 252388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072850038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3072850038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.1225667731
Short name T403
Test name
Test status
Simulation time 8249838060 ps
CPU time 27.66 seconds
Started Sep 04 07:07:53 AM UTC 24
Finished Sep 04 07:08:22 AM UTC 24
Peak memory 228140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225667731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1225667731 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.2460136821
Short name T61
Test name
Test status
Simulation time 234132440 ps
CPU time 2.38 seconds
Started Sep 04 07:07:56 AM UTC 24
Finished Sep 04 07:07:59 AM UTC 24
Peak memory 234048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460136821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2460136821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.4268279369
Short name T703
Test name
Test status
Simulation time 344908674856 ps
CPU time 3808.03 seconds
Started Sep 04 07:06:40 AM UTC 24
Finished Sep 04 08:10:47 AM UTC 24
Peak memory 4063884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268279369 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.4268279369 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.3580916357
Short name T422
Test name
Test status
Simulation time 129446027749 ps
CPU time 284.78 seconds
Started Sep 04 07:06:51 AM UTC 24
Finished Sep 04 07:11:40 AM UTC 24
Peak memory 418392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580916357 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.3580916357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.1310459993
Short name T391
Test name
Test status
Simulation time 515764633 ps
CPU time 8.5 seconds
Started Sep 04 07:06:30 AM UTC 24
Finished Sep 04 07:06:40 AM UTC 24
Peak memory 235520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310459993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1310459993 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.1394626576
Short name T433
Test name
Test status
Simulation time 9799216720 ps
CPU time 340.7 seconds
Started Sep 04 07:08:00 AM UTC 24
Finished Sep 04 07:13:45 AM UTC 24
Peak memory 371236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394626576 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1394626576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.193474252
Short name T411
Test name
Test status
Simulation time 46810426 ps
CPU time 1.27 seconds
Started Sep 04 07:09:13 AM UTC 24
Finished Sep 04 07:09:15 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193474252 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.193474252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_app.195041163
Short name T414
Test name
Test status
Simulation time 9861657948 ps
CPU time 81.33 seconds
Started Sep 04 07:08:23 AM UTC 24
Finished Sep 04 07:09:47 AM UTC 24
Peak memory 283236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195041163 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.195041163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.3359605649
Short name T437
Test name
Test status
Simulation time 3574067684 ps
CPU time 361.21 seconds
Started Sep 04 07:08:22 AM UTC 24
Finished Sep 04 07:14:28 AM UTC 24
Peak memory 252448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359605649 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3359605649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.2105025243
Short name T419
Test name
Test status
Simulation time 32061024909 ps
CPU time 158.11 seconds
Started Sep 04 07:08:26 AM UTC 24
Finished Sep 04 07:11:07 AM UTC 24
Peak memory 350800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105025243 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2105025243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_error.3101507966
Short name T36
Test name
Test status
Simulation time 11740298327 ps
CPU time 458.99 seconds
Started Sep 04 07:08:35 AM UTC 24
Finished Sep 04 07:16:20 AM UTC 24
Peak memory 555752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101507966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3101507966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.1245853249
Short name T408
Test name
Test status
Simulation time 942478890 ps
CPU time 5.21 seconds
Started Sep 04 07:08:41 AM UTC 24
Finished Sep 04 07:08:47 AM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245853249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1245853249 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.3394673478
Short name T410
Test name
Test status
Simulation time 1899110432 ps
CPU time 22.83 seconds
Started Sep 04 07:08:48 AM UTC 24
Finished Sep 04 07:09:12 AM UTC 24
Peak memory 252404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394673478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3394673478 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1207321046
Short name T515
Test name
Test status
Simulation time 35020592357 ps
CPU time 1191.5 seconds
Started Sep 04 07:08:19 AM UTC 24
Finished Sep 04 07:28:23 AM UTC 24
Peak memory 1811112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207321046 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1207321046 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.2952983904
Short name T445
Test name
Test status
Simulation time 5041093888 ps
CPU time 469.97 seconds
Started Sep 04 07:08:21 AM UTC 24
Finished Sep 04 07:16:18 AM UTC 24
Peak memory 367204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952983904 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2952983904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.1815443036
Short name T405
Test name
Test status
Simulation time 639438409 ps
CPU time 20.85 seconds
Started Sep 04 07:08:03 AM UTC 24
Finished Sep 04 07:08:26 AM UTC 24
Peak memory 236012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815443036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1815443036 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.4131639105
Short name T593
Test name
Test status
Simulation time 73038539390 ps
CPU time 2157.12 seconds
Started Sep 04 07:09:11 AM UTC 24
Finished Sep 04 07:45:31 AM UTC 24
Peak memory 1381240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131639105 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.4131639105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2002075876
Short name T420
Test name
Test status
Simulation time 37321463 ps
CPU time 1.23 seconds
Started Sep 04 07:11:08 AM UTC 24
Finished Sep 04 07:11:10 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002075876 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2002075876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_app.1574518417
Short name T431
Test name
Test status
Simulation time 7521252026 ps
CPU time 188.35 seconds
Started Sep 04 07:10:12 AM UTC 24
Finished Sep 04 07:13:24 AM UTC 24
Peak memory 363172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574518417 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1574518417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.2624502548
Short name T492
Test name
Test status
Simulation time 22034501863 ps
CPU time 911.39 seconds
Started Sep 04 07:09:47 AM UTC 24
Finished Sep 04 07:25:10 AM UTC 24
Peak memory 250468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624502548 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.2624502548 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1758174701
Short name T444
Test name
Test status
Simulation time 56949715511 ps
CPU time 351.53 seconds
Started Sep 04 07:10:17 AM UTC 24
Finished Sep 04 07:16:13 AM UTC 24
Peak memory 461424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758174701 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1758174701 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_error.1865581613
Short name T424
Test name
Test status
Simulation time 722388491 ps
CPU time 75.49 seconds
Started Sep 04 07:10:44 AM UTC 24
Finished Sep 04 07:12:01 AM UTC 24
Peak memory 264744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865581613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1865581613 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.2620733699
Short name T417
Test name
Test status
Simulation time 6361765854 ps
CPU time 10.36 seconds
Started Sep 04 07:10:51 AM UTC 24
Finished Sep 04 07:11:02 AM UTC 24
Peak memory 227916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620733699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2620733699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.2002246105
Short name T418
Test name
Test status
Simulation time 278253718 ps
CPU time 2.54 seconds
Started Sep 04 07:11:03 AM UTC 24
Finished Sep 04 07:11:06 AM UTC 24
Peak memory 232060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002246105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2002246105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3496647024
Short name T707
Test name
Test status
Simulation time 79700012791 ps
CPU time 3682.46 seconds
Started Sep 04 07:09:17 AM UTC 24
Finished Sep 04 08:11:18 AM UTC 24
Peak memory 3728088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496647024 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3496647024 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.459757602
Short name T453
Test name
Test status
Simulation time 46151083862 ps
CPU time 443.28 seconds
Started Sep 04 07:09:36 AM UTC 24
Finished Sep 04 07:17:05 AM UTC 24
Peak memory 529000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459757602 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.459757602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.358921628
Short name T415
Test name
Test status
Simulation time 17942238906 ps
CPU time 53.56 seconds
Started Sep 04 07:09:16 AM UTC 24
Finished Sep 04 07:10:11 AM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358921628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.358921628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3345331792
Short name T532
Test name
Test status
Simulation time 60190288925 ps
CPU time 1320.71 seconds
Started Sep 04 07:11:07 AM UTC 24
Finished Sep 04 07:33:22 AM UTC 24
Peak memory 674392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345331792 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3345331792 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.3467968854
Short name T430
Test name
Test status
Simulation time 143289569 ps
CPU time 1.32 seconds
Started Sep 04 07:12:48 AM UTC 24
Finished Sep 04 07:12:54 AM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467968854 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.3467968854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_app.4031977089
Short name T429
Test name
Test status
Simulation time 4227729488 ps
CPU time 43.78 seconds
Started Sep 04 07:12:02 AM UTC 24
Finished Sep 04 07:12:48 AM UTC 24
Peak memory 266840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031977089 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.4031977089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.974947925
Short name T512
Test name
Test status
Simulation time 17747000830 ps
CPU time 946.89 seconds
Started Sep 04 07:11:50 AM UTC 24
Finished Sep 04 07:27:49 AM UTC 24
Peak memory 256612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974947925 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.974947925 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.698705165
Short name T427
Test name
Test status
Simulation time 451668347 ps
CPU time 13.43 seconds
Started Sep 04 07:12:07 AM UTC 24
Finished Sep 04 07:12:21 AM UTC 24
Peak memory 242272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698705165 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.698705165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_error.3569181159
Short name T467
Test name
Test status
Simulation time 5132111308 ps
CPU time 501.59 seconds
Started Sep 04 07:12:07 AM UTC 24
Finished Sep 04 07:20:35 AM UTC 24
Peak memory 371300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569181159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.3569181159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.608385749
Short name T428
Test name
Test status
Simulation time 1375790477 ps
CPU time 11.34 seconds
Started Sep 04 07:12:22 AM UTC 24
Finished Sep 04 07:12:34 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608385749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.608385749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.203858997
Short name T64
Test name
Test status
Simulation time 116790581 ps
CPU time 2.12 seconds
Started Sep 04 07:12:35 AM UTC 24
Finished Sep 04 07:12:38 AM UTC 24
Peak memory 231996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203858997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.203858997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.4207343996
Short name T547
Test name
Test status
Simulation time 74463083190 ps
CPU time 1510.02 seconds
Started Sep 04 07:11:25 AM UTC 24
Finished Sep 04 07:36:52 AM UTC 24
Peak memory 1962612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207343996 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.4207343996 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.3719960566
Short name T446
Test name
Test status
Simulation time 91907991161 ps
CPU time 285.78 seconds
Started Sep 04 07:11:41 AM UTC 24
Finished Sep 04 07:16:31 AM UTC 24
Peak memory 486044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719960566 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3719960566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.794993158
Short name T423
Test name
Test status
Simulation time 1280207082 ps
CPU time 36.44 seconds
Started Sep 04 07:11:11 AM UTC 24
Finished Sep 04 07:11:50 AM UTC 24
Peak memory 235952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794993158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.794993158 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.653402662
Short name T524
Test name
Test status
Simulation time 116940622873 ps
CPU time 1077.33 seconds
Started Sep 04 07:12:39 AM UTC 24
Finished Sep 04 07:30:49 AM UTC 24
Peak memory 1098648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653402662 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.653402662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.3123327411
Short name T441
Test name
Test status
Simulation time 18883772 ps
CPU time 1.39 seconds
Started Sep 04 07:15:13 AM UTC 24
Finished Sep 04 07:15:16 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123327411 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3123327411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_app.3280699062
Short name T439
Test name
Test status
Simulation time 3391147490 ps
CPU time 54.73 seconds
Started Sep 04 07:14:04 AM UTC 24
Finished Sep 04 07:15:00 AM UTC 24
Peak memory 250468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280699062 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3280699062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.3348080080
Short name T583
Test name
Test status
Simulation time 159570729631 ps
CPU time 1774.93 seconds
Started Sep 04 07:13:46 AM UTC 24
Finished Sep 04 07:43:42 AM UTC 24
Peak memory 275036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348080080 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3348080080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.1317349017
Short name T464
Test name
Test status
Simulation time 14305201344 ps
CPU time 366.58 seconds
Started Sep 04 07:14:09 AM UTC 24
Finished Sep 04 07:20:21 AM UTC 24
Peak memory 475692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317349017 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1317349017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_error.379495492
Short name T37
Test name
Test status
Simulation time 9288094362 ps
CPU time 180.34 seconds
Started Sep 04 07:14:19 AM UTC 24
Finished Sep 04 07:17:22 AM UTC 24
Peak memory 299628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379495492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.379495492 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.3060926002
Short name T438
Test name
Test status
Simulation time 6662279036 ps
CPU time 22.38 seconds
Started Sep 04 07:14:29 AM UTC 24
Finished Sep 04 07:14:53 AM UTC 24
Peak memory 227940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060926002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3060926002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3288220706
Short name T692
Test name
Test status
Simulation time 385253203973 ps
CPU time 3219.98 seconds
Started Sep 04 07:13:24 AM UTC 24
Finished Sep 04 08:07:37 AM UTC 24
Peak memory 3678836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288220706 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3288220706 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.4130938378
Short name T455
Test name
Test status
Simulation time 7561322142 ps
CPU time 211.85 seconds
Started Sep 04 07:13:46 AM UTC 24
Finished Sep 04 07:17:22 AM UTC 24
Peak memory 371236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130938378 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.4130938378 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.178975516
Short name T436
Test name
Test status
Simulation time 7495108690 ps
CPU time 81.24 seconds
Started Sep 04 07:12:55 AM UTC 24
Finished Sep 04 07:14:18 AM UTC 24
Peak memory 234340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178975516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.178975516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.2586273585
Short name T628
Test name
Test status
Simulation time 85259581014 ps
CPU time 2470.42 seconds
Started Sep 04 07:15:01 AM UTC 24
Finished Sep 04 07:56:39 AM UTC 24
Peak memory 1289104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586273585 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2586273585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.3135044307
Short name T451
Test name
Test status
Simulation time 16458589 ps
CPU time 1.29 seconds
Started Sep 04 07:16:45 AM UTC 24
Finished Sep 04 07:16:47 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135044307 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3135044307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_app.572542468
Short name T447
Test name
Test status
Simulation time 1239953860 ps
CPU time 23.68 seconds
Started Sep 04 07:16:13 AM UTC 24
Finished Sep 04 07:16:38 AM UTC 24
Peak memory 235656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572542468 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.572542468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.531589849
Short name T465
Test name
Test status
Simulation time 4471980512 ps
CPU time 268.46 seconds
Started Sep 04 07:15:56 AM UTC 24
Finished Sep 04 07:20:29 AM UTC 24
Peak memory 238116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531589849 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.531589849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.4076625351
Short name T471
Test name
Test status
Simulation time 26263068441 ps
CPU time 263.72 seconds
Started Sep 04 07:16:18 AM UTC 24
Finished Sep 04 07:20:46 AM UTC 24
Peak memory 459336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076625351 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.4076625351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_error.1336358947
Short name T475
Test name
Test status
Simulation time 31316117569 ps
CPU time 296.3 seconds
Started Sep 04 07:16:20 AM UTC 24
Finished Sep 04 07:21:21 AM UTC 24
Peak memory 416280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336358947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.1336358947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.3779617298
Short name T449
Test name
Test status
Simulation time 947227977 ps
CPU time 11.61 seconds
Started Sep 04 07:16:32 AM UTC 24
Finished Sep 04 07:16:44 AM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779617298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.3779617298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2290515293
Short name T448
Test name
Test status
Simulation time 49024645 ps
CPU time 2.29 seconds
Started Sep 04 07:16:39 AM UTC 24
Finished Sep 04 07:16:42 AM UTC 24
Peak memory 234044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290515293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2290515293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.3037098209
Short name T580
Test name
Test status
Simulation time 34412593847 ps
CPU time 1648.72 seconds
Started Sep 04 07:15:17 AM UTC 24
Finished Sep 04 07:43:05 AM UTC 24
Peak memory 1653364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037098209 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.3037098209 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.922211202
Short name T463
Test name
Test status
Simulation time 3588700446 ps
CPU time 268.42 seconds
Started Sep 04 07:15:43 AM UTC 24
Finished Sep 04 07:20:16 AM UTC 24
Peak memory 334376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922211202 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.922211202 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.3376068757
Short name T442
Test name
Test status
Simulation time 1322945591 ps
CPU time 24.38 seconds
Started Sep 04 07:15:17 AM UTC 24
Finished Sep 04 07:15:42 AM UTC 24
Peak memory 235944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376068757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3376068757 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.3032773547
Short name T589
Test name
Test status
Simulation time 175739689014 ps
CPU time 1653.75 seconds
Started Sep 04 07:16:43 AM UTC 24
Finished Sep 04 07:44:34 AM UTC 24
Peak memory 957360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032773547 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3032773547 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.1464993209
Short name T459
Test name
Test status
Simulation time 32386433 ps
CPU time 1.23 seconds
Started Sep 04 07:18:02 AM UTC 24
Finished Sep 04 07:18:04 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464993209 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1464993209 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_app.3652337277
Short name T460
Test name
Test status
Simulation time 7597318357 ps
CPU time 73.84 seconds
Started Sep 04 07:17:08 AM UTC 24
Finished Sep 04 07:18:24 AM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652337277 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3652337277 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.4178653175
Short name T483
Test name
Test status
Simulation time 6954855883 ps
CPU time 336.48 seconds
Started Sep 04 07:17:08 AM UTC 24
Finished Sep 04 07:22:49 AM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178653175 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.4178653175 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.1835643479
Short name T458
Test name
Test status
Simulation time 10022158939 ps
CPU time 40.82 seconds
Started Sep 04 07:17:18 AM UTC 24
Finished Sep 04 07:18:01 AM UTC 24
Peak memory 238120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835643479 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.1835643479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_error.1914570629
Short name T488
Test name
Test status
Simulation time 60746063923 ps
CPU time 416.8 seconds
Started Sep 04 07:17:22 AM UTC 24
Finished Sep 04 07:24:26 AM UTC 24
Peak memory 571944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914570629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1914570629 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.4197733025
Short name T456
Test name
Test status
Simulation time 1491637713 ps
CPU time 16.55 seconds
Started Sep 04 07:17:23 AM UTC 24
Finished Sep 04 07:17:43 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197733025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4197733025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.3169071264
Short name T457
Test name
Test status
Simulation time 67792284 ps
CPU time 2.31 seconds
Started Sep 04 07:17:44 AM UTC 24
Finished Sep 04 07:17:47 AM UTC 24
Peak memory 232060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169071264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3169071264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.3290857737
Short name T634
Test name
Test status
Simulation time 68032738757 ps
CPU time 2398.37 seconds
Started Sep 04 07:16:48 AM UTC 24
Finished Sep 04 07:57:13 AM UTC 24
Peak memory 2720368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290857737 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.3290857737 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.2528552303
Short name T497
Test name
Test status
Simulation time 35694083136 ps
CPU time 545.45 seconds
Started Sep 04 07:17:00 AM UTC 24
Finished Sep 04 07:26:12 AM UTC 24
Peak memory 625256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528552303 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2528552303 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.2532435081
Short name T454
Test name
Test status
Simulation time 2868703586 ps
CPU time 18.28 seconds
Started Sep 04 07:16:47 AM UTC 24
Finished Sep 04 07:17:06 AM UTC 24
Peak memory 236044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532435081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2532435081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.3706927764
Short name T676
Test name
Test status
Simulation time 59891198447 ps
CPU time 2733.77 seconds
Started Sep 04 07:17:51 AM UTC 24
Finished Sep 04 08:03:54 AM UTC 24
Peak memory 961380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706927764 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3706927764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.1970181516
Short name T470
Test name
Test status
Simulation time 120509685 ps
CPU time 1.31 seconds
Started Sep 04 07:20:40 AM UTC 24
Finished Sep 04 07:20:43 AM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970181516 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1970181516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_app.2503644838
Short name T466
Test name
Test status
Simulation time 864469677 ps
CPU time 11.94 seconds
Started Sep 04 07:20:17 AM UTC 24
Finished Sep 04 07:20:30 AM UTC 24
Peak memory 236008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503644838 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2503644838 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.828582360
Short name T508
Test name
Test status
Simulation time 15543318372 ps
CPU time 475.69 seconds
Started Sep 04 07:19:22 AM UTC 24
Finished Sep 04 07:27:25 AM UTC 24
Peak memory 242220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828582360 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.828582360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.127261366
Short name T480
Test name
Test status
Simulation time 5517540404 ps
CPU time 128.4 seconds
Started Sep 04 07:20:22 AM UTC 24
Finished Sep 04 07:22:33 AM UTC 24
Peak memory 264884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127261366 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.127261366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_error.181220631
Short name T496
Test name
Test status
Simulation time 14842892493 ps
CPU time 322.21 seconds
Started Sep 04 07:20:30 AM UTC 24
Finished Sep 04 07:25:57 AM UTC 24
Peak memory 334508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181220631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.181220631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.1266926679
Short name T472
Test name
Test status
Simulation time 12274626017 ps
CPU time 14.8 seconds
Started Sep 04 07:20:31 AM UTC 24
Finished Sep 04 07:20:47 AM UTC 24
Peak memory 227924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266926679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1266926679 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.481632946
Short name T469
Test name
Test status
Simulation time 119324060 ps
CPU time 2.36 seconds
Started Sep 04 07:20:36 AM UTC 24
Finished Sep 04 07:20:40 AM UTC 24
Peak memory 234044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481632946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.481632946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.3348069038
Short name T718
Test name
Test status
Simulation time 961771498571 ps
CPU time 4156.85 seconds
Started Sep 04 07:18:25 AM UTC 24
Finished Sep 04 08:28:24 AM UTC 24
Peak memory 4324040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348069038 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.3348069038 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.3011068844
Short name T468
Test name
Test status
Simulation time 2667545100 ps
CPU time 120.93 seconds
Started Sep 04 07:18:35 AM UTC 24
Finished Sep 04 07:20:39 AM UTC 24
Peak memory 293412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011068844 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3011068844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.1411838304
Short name T461
Test name
Test status
Simulation time 485772792 ps
CPU time 28.05 seconds
Started Sep 04 07:18:05 AM UTC 24
Finished Sep 04 07:18:34 AM UTC 24
Peak memory 236012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411838304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1411838304 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.1575550372
Short name T714
Test name
Test status
Simulation time 309768748556 ps
CPU time 3476.14 seconds
Started Sep 04 07:20:40 AM UTC 24
Finished Sep 04 08:19:16 AM UTC 24
Peak memory 1285040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575550372 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.1575550372 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.103064755
Short name T197
Test name
Test status
Simulation time 50275391 ps
CPU time 1.24 seconds
Started Sep 04 06:28:57 AM UTC 24
Finished Sep 04 06:28:59 AM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103064755 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.103064755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_app.709210542
Short name T210
Test name
Test status
Simulation time 39298616936 ps
CPU time 348.11 seconds
Started Sep 04 06:27:25 AM UTC 24
Finished Sep 04 06:33:18 AM UTC 24
Peak memory 399968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709210542 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.709210542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.1761029009
Short name T208
Test name
Test status
Simulation time 150740874636 ps
CPU time 319.56 seconds
Started Sep 04 06:27:27 AM UTC 24
Finished Sep 04 06:32:51 AM UTC 24
Peak memory 449192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761029009 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.1761029009 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.4258958593
Short name T147
Test name
Test status
Simulation time 31173682470 ps
CPU time 373.11 seconds
Started Sep 04 06:26:27 AM UTC 24
Finished Sep 04 06:32:45 AM UTC 24
Peak memory 246380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258958593 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4258958593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.4256040440
Short name T139
Test name
Test status
Simulation time 541223016 ps
CPU time 18.91 seconds
Started Sep 04 06:28:06 AM UTC 24
Finished Sep 04 06:28:26 AM UTC 24
Peak memory 235596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256040440 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4256040440 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.1373071837
Short name T75
Test name
Test status
Simulation time 78153288 ps
CPU time 1.48 seconds
Started Sep 04 06:28:16 AM UTC 24
Finished Sep 04 06:28:18 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373071837 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1373071837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.821183491
Short name T168
Test name
Test status
Simulation time 7088038556 ps
CPU time 106.32 seconds
Started Sep 04 06:28:19 AM UTC 24
Finished Sep 04 06:30:08 AM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821183491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.821183491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.4169486827
Short name T65
Test name
Test status
Simulation time 6680614674 ps
CPU time 32.95 seconds
Started Sep 04 06:27:30 AM UTC 24
Finished Sep 04 06:28:05 AM UTC 24
Peak memory 248568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169486827 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.4169486827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_error.116584618
Short name T85
Test name
Test status
Simulation time 5089266073 ps
CPU time 531.53 seconds
Started Sep 04 06:27:34 AM UTC 24
Finished Sep 04 06:36:33 AM UTC 24
Peak memory 375336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116584618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.116584618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.4075375122
Short name T101
Test name
Test status
Simulation time 2286993512 ps
CPU time 8.7 seconds
Started Sep 04 06:28:06 AM UTC 24
Finished Sep 04 06:28:16 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075375122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.4075375122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1727720691
Short name T44
Test name
Test status
Simulation time 66757061 ps
CPU time 2.04 seconds
Started Sep 04 06:28:27 AM UTC 24
Finished Sep 04 06:28:30 AM UTC 24
Peak memory 234148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727720691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1727720691 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.2675734928
Short name T294
Test name
Test status
Simulation time 14448605874 ps
CPU time 1576.15 seconds
Started Sep 04 06:26:12 AM UTC 24
Finished Sep 04 06:52:47 AM UTC 24
Peak memory 1006100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675734928 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2675734928 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.1802803450
Short name T90
Test name
Test status
Simulation time 4112264621 ps
CPU time 208.65 seconds
Started Sep 04 06:27:33 AM UTC 24
Finished Sep 04 06:31:05 AM UTC 24
Peak memory 310160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802803450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1802803450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.4242464550
Short name T104
Test name
Test status
Simulation time 61911126911 ps
CPU time 141.15 seconds
Started Sep 04 06:28:53 AM UTC 24
Finished Sep 04 06:31:17 AM UTC 24
Peak memory 322040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242464550 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.4242464550 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.720057465
Short name T190
Test name
Test status
Simulation time 7163540859 ps
CPU time 322.14 seconds
Started Sep 04 06:26:23 AM UTC 24
Finished Sep 04 06:31:50 AM UTC 24
Peak memory 440928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720057465 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.720057465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.2556436576
Short name T138
Test name
Test status
Simulation time 1196854071 ps
CPU time 8.84 seconds
Started Sep 04 06:26:12 AM UTC 24
Finished Sep 04 06:26:22 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556436576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.2556436576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.3956477938
Short name T151
Test name
Test status
Simulation time 53473551394 ps
CPU time 1115.48 seconds
Started Sep 04 06:28:31 AM UTC 24
Finished Sep 04 06:47:20 AM UTC 24
Peak memory 328236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956477938 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.3956477938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.3336004766
Short name T97
Test name
Test status
Simulation time 117510751 ps
CPU time 4.17 seconds
Started Sep 04 06:27:21 AM UTC 24
Finished Sep 04 06:27:27 AM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336004766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.3336004766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.4161079489
Short name T98
Test name
Test status
Simulation time 299860761 ps
CPU time 3.32 seconds
Started Sep 04 06:27:25 AM UTC 24
Finished Sep 04 06:27:30 AM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161079489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.4161079489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.767440258
Short name T100
Test name
Test status
Simulation time 2672550166 ps
CPU time 41.89 seconds
Started Sep 04 06:26:50 AM UTC 24
Finished Sep 04 06:27:33 AM UTC 24
Peak memory 235172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767440258 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.767440258 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.3689493065
Short name T376
Test name
Test status
Simulation time 117798594623 ps
CPU time 2232.69 seconds
Started Sep 04 06:26:52 AM UTC 24
Finished Sep 04 07:04:28 AM UTC 24
Peak memory 3035592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689493065 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3689493065 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3718500998
Short name T96
Test name
Test status
Simulation time 874301364 ps
CPU time 30.05 seconds
Started Sep 04 06:26:53 AM UTC 24
Finished Sep 04 06:27:24 AM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718500998 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3718500998 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.250557861
Short name T329
Test name
Test status
Simulation time 434471026559 ps
CPU time 1799.61 seconds
Started Sep 04 06:27:00 AM UTC 24
Finished Sep 04 06:57:19 AM UTC 24
Peak memory 1753540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250557861 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.250557861 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.2290741336
Short name T198
Test name
Test status
Simulation time 7224846838 ps
CPU time 169.9 seconds
Started Sep 04 06:27:02 AM UTC 24
Finished Sep 04 06:29:55 AM UTC 24
Peak memory 291296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290741336 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2290741336 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.533825448
Short name T199
Test name
Test status
Simulation time 4118715282 ps
CPU time 169.5 seconds
Started Sep 04 06:27:12 AM UTC 24
Finished Sep 04 06:30:05 AM UTC 24
Peak memory 266752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533825448 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.533825448 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.3976520581
Short name T481
Test name
Test status
Simulation time 30154556 ps
CPU time 1.38 seconds
Started Sep 04 07:22:34 AM UTC 24
Finished Sep 04 07:22:36 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976520581 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3976520581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_app.3253511594
Short name T495
Test name
Test status
Simulation time 38772948511 ps
CPU time 275.77 seconds
Started Sep 04 07:21:14 AM UTC 24
Finished Sep 04 07:25:54 AM UTC 24
Peak memory 449192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253511594 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3253511594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.1317179234
Short name T600
Test name
Test status
Simulation time 46121731710 ps
CPU time 1522.73 seconds
Started Sep 04 07:21:01 AM UTC 24
Finished Sep 04 07:46:41 AM UTC 24
Peak memory 254504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317179234 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1317179234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.667601383
Short name T499
Test name
Test status
Simulation time 13532320013 ps
CPU time 292.27 seconds
Started Sep 04 07:21:22 AM UTC 24
Finished Sep 04 07:26:19 AM UTC 24
Peak memory 442952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667601383 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.667601383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_error.3061092023
Short name T507
Test name
Test status
Simulation time 3365527556 ps
CPU time 335.63 seconds
Started Sep 04 07:21:38 AM UTC 24
Finished Sep 04 07:27:19 AM UTC 24
Peak memory 334436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061092023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3061092023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.4022022244
Short name T478
Test name
Test status
Simulation time 337581013 ps
CPU time 6.03 seconds
Started Sep 04 07:22:03 AM UTC 24
Finished Sep 04 07:22:11 AM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022022244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.4022022244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.339543178
Short name T479
Test name
Test status
Simulation time 59157761 ps
CPU time 2.54 seconds
Started Sep 04 07:22:12 AM UTC 24
Finished Sep 04 07:22:15 AM UTC 24
Peak memory 232080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339543178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.339543178 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3488100004
Short name T506
Test name
Test status
Simulation time 24868134188 ps
CPU time 375.24 seconds
Started Sep 04 07:20:47 AM UTC 24
Finished Sep 04 07:27:07 AM UTC 24
Peak memory 655920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488100004 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3488100004 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.3850732637
Short name T482
Test name
Test status
Simulation time 3657440678 ps
CPU time 115.1 seconds
Started Sep 04 07:20:48 AM UTC 24
Finished Sep 04 07:22:45 AM UTC 24
Peak memory 293480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850732637 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3850732637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.1227747755
Short name T474
Test name
Test status
Simulation time 12711997401 ps
CPU time 28.41 seconds
Started Sep 04 07:20:43 AM UTC 24
Finished Sep 04 07:21:13 AM UTC 24
Peak memory 236052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227747755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1227747755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.1899421185
Short name T590
Test name
Test status
Simulation time 154920161014 ps
CPU time 1348.89 seconds
Started Sep 04 07:22:16 AM UTC 24
Finished Sep 04 07:45:00 AM UTC 24
Peak memory 398288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899421185 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1899421185 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.2912027970
Short name T491
Test name
Test status
Simulation time 104000194 ps
CPU time 1.35 seconds
Started Sep 04 07:24:50 AM UTC 24
Finished Sep 04 07:24:52 AM UTC 24
Peak memory 226660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912027970 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2912027970 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_app.1021813146
Short name T523
Test name
Test status
Simulation time 14391728854 ps
CPU time 422.01 seconds
Started Sep 04 07:23:20 AM UTC 24
Finished Sep 04 07:30:27 AM UTC 24
Peak memory 352812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021813146 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1021813146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.2532318313
Short name T520
Test name
Test status
Simulation time 26896437219 ps
CPU time 410.99 seconds
Started Sep 04 07:23:10 AM UTC 24
Finished Sep 04 07:30:07 AM UTC 24
Peak memory 244316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532318313 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.2532318313 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.2629702523
Short name T494
Test name
Test status
Simulation time 53297077922 ps
CPU time 109.1 seconds
Started Sep 04 07:23:47 AM UTC 24
Finished Sep 04 07:25:38 AM UTC 24
Peak memory 270956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629702523 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2629702523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_error.345872300
Short name T519
Test name
Test status
Simulation time 9699882565 ps
CPU time 335.68 seconds
Started Sep 04 07:24:22 AM UTC 24
Finished Sep 04 07:30:03 AM UTC 24
Peak memory 492048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345872300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.345872300 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.3743817517
Short name T489
Test name
Test status
Simulation time 987478773 ps
CPU time 11.75 seconds
Started Sep 04 07:24:27 AM UTC 24
Finished Sep 04 07:24:40 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743817517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3743817517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.227912834
Short name T712
Test name
Test status
Simulation time 54847509973 ps
CPU time 3083.31 seconds
Started Sep 04 07:22:46 AM UTC 24
Finished Sep 04 08:14:43 AM UTC 24
Peak memory 1829492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227912834 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.227912834 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.1446272661
Short name T493
Test name
Test status
Simulation time 4830444278 ps
CPU time 140.54 seconds
Started Sep 04 07:22:50 AM UTC 24
Finished Sep 04 07:25:13 AM UTC 24
Peak memory 277012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446272661 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1446272661 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.4199296124
Short name T484
Test name
Test status
Simulation time 876644205 ps
CPU time 30.74 seconds
Started Sep 04 07:22:37 AM UTC 24
Finished Sep 04 07:23:09 AM UTC 24
Peak memory 234140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199296124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.4199296124 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.2876756901
Short name T598
Test name
Test status
Simulation time 43068077738 ps
CPU time 1299.02 seconds
Started Sep 04 07:24:46 AM UTC 24
Finished Sep 04 07:46:39 AM UTC 24
Peak memory 1416108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876756901 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2876756901 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.503363316
Short name T502
Test name
Test status
Simulation time 23658694 ps
CPU time 1.28 seconds
Started Sep 04 07:26:25 AM UTC 24
Finished Sep 04 07:26:27 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503363316 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.503363316 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_app.1151522583
Short name T498
Test name
Test status
Simulation time 3175603143 ps
CPU time 19.18 seconds
Started Sep 04 07:25:55 AM UTC 24
Finished Sep 04 07:26:15 AM UTC 24
Peak memory 242276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151522583 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1151522583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.3605959285
Short name T574
Test name
Test status
Simulation time 20913597083 ps
CPU time 982.32 seconds
Started Sep 04 07:25:39 AM UTC 24
Finished Sep 04 07:42:14 AM UTC 24
Peak memory 262732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605959285 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3605959285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.3458354987
Short name T528
Test name
Test status
Simulation time 62800304003 ps
CPU time 378.1 seconds
Started Sep 04 07:25:58 AM UTC 24
Finished Sep 04 07:32:21 AM UTC 24
Peak memory 342636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458354987 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3458354987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_error.3144574342
Short name T518
Test name
Test status
Simulation time 43392110335 ps
CPU time 224.79 seconds
Started Sep 04 07:26:13 AM UTC 24
Finished Sep 04 07:30:02 AM UTC 24
Peak memory 455328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144574342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3144574342 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2092784810
Short name T503
Test name
Test status
Simulation time 20378440116 ps
CPU time 12.24 seconds
Started Sep 04 07:26:16 AM UTC 24
Finished Sep 04 07:26:29 AM UTC 24
Peak memory 229996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092784810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2092784810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.2523885497
Short name T501
Test name
Test status
Simulation time 51485241 ps
CPU time 2.26 seconds
Started Sep 04 07:26:20 AM UTC 24
Finished Sep 04 07:26:24 AM UTC 24
Peak memory 234044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523885497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2523885497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.3108657814
Short name T544
Test name
Test status
Simulation time 15143112468 ps
CPU time 671.99 seconds
Started Sep 04 07:25:11 AM UTC 24
Finished Sep 04 07:36:31 AM UTC 24
Peak memory 905788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108657814 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.3108657814 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.4079839099
Short name T522
Test name
Test status
Simulation time 32598188283 ps
CPU time 307.5 seconds
Started Sep 04 07:25:14 AM UTC 24
Finished Sep 04 07:30:26 AM UTC 24
Peak memory 397860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079839099 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.4079839099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.3431098711
Short name T500
Test name
Test status
Simulation time 2075787996 ps
CPU time 85.08 seconds
Started Sep 04 07:24:53 AM UTC 24
Finished Sep 04 07:26:20 AM UTC 24
Peak memory 236028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431098711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3431098711 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.740727946
Short name T689
Test name
Test status
Simulation time 69041676927 ps
CPU time 2410.07 seconds
Started Sep 04 07:26:21 AM UTC 24
Finished Sep 04 08:06:59 AM UTC 24
Peak memory 1377352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740727946 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.740727946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2754813182
Short name T514
Test name
Test status
Simulation time 19652651 ps
CPU time 1.34 seconds
Started Sep 04 07:27:50 AM UTC 24
Finished Sep 04 07:27:53 AM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754813182 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2754813182 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_app.3202422876
Short name T509
Test name
Test status
Simulation time 875788867 ps
CPU time 27.96 seconds
Started Sep 04 07:27:07 AM UTC 24
Finished Sep 04 07:27:37 AM UTC 24
Peak memory 252352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202422876 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3202422876 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.2373978073
Short name T516
Test name
Test status
Simulation time 5222304780 ps
CPU time 81.21 seconds
Started Sep 04 07:27:01 AM UTC 24
Finished Sep 04 07:28:24 AM UTC 24
Peak memory 236068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373978073 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.2373978073 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3110172737
Short name T510
Test name
Test status
Simulation time 643280586 ps
CPU time 22.85 seconds
Started Sep 04 07:27:21 AM UTC 24
Finished Sep 04 07:27:45 AM UTC 24
Peak memory 252332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110172737 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3110172737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_error.2055472720
Short name T525
Test name
Test status
Simulation time 5809156769 ps
CPU time 236.72 seconds
Started Sep 04 07:27:26 AM UTC 24
Finished Sep 04 07:31:26 AM UTC 24
Peak memory 387688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055472720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2055472720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.3526284399
Short name T511
Test name
Test status
Simulation time 777226464 ps
CPU time 9.66 seconds
Started Sep 04 07:27:38 AM UTC 24
Finished Sep 04 07:27:49 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526284399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3526284399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.2617834294
Short name T513
Test name
Test status
Simulation time 38893618 ps
CPU time 2.78 seconds
Started Sep 04 07:27:46 AM UTC 24
Finished Sep 04 07:27:50 AM UTC 24
Peak memory 232000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617834294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2617834294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.2149468856
Short name T632
Test name
Test status
Simulation time 234472165250 ps
CPU time 1812.99 seconds
Started Sep 04 07:26:31 AM UTC 24
Finished Sep 04 07:57:04 AM UTC 24
Peak memory 2093684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149468856 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.2149468856 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.3617043182
Short name T530
Test name
Test status
Simulation time 17320460924 ps
CPU time 377.14 seconds
Started Sep 04 07:26:50 AM UTC 24
Finished Sep 04 07:33:12 AM UTC 24
Peak memory 481832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617043182 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3617043182 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.3766403624
Short name T505
Test name
Test status
Simulation time 1012486881 ps
CPU time 31.35 seconds
Started Sep 04 07:26:28 AM UTC 24
Finished Sep 04 07:27:01 AM UTC 24
Peak memory 236008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766403624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3766403624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.56696332
Short name T575
Test name
Test status
Simulation time 111901705107 ps
CPU time 856.6 seconds
Started Sep 04 07:27:49 AM UTC 24
Finished Sep 04 07:42:16 AM UTC 24
Peak memory 439224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56696332 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.56696332 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3268522477
Short name T526
Test name
Test status
Simulation time 42480735 ps
CPU time 0.92 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:31:52 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268522477 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3268522477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_app.1310350181
Short name T561
Test name
Test status
Simulation time 33968311881 ps
CPU time 433.02 seconds
Started Sep 04 07:31:48 AM UTC 24
Finished Sep 04 07:39:07 AM UTC 24
Peak memory 496232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310350181 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1310350181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.568231850
Short name T617
Test name
Test status
Simulation time 13428471982 ps
CPU time 1490.93 seconds
Started Sep 04 07:28:25 AM UTC 24
Finished Sep 04 07:53:34 AM UTC 24
Peak memory 256560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568231850 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.568231850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3250603337
Short name T537
Test name
Test status
Simulation time 18144376350 ps
CPU time 142.67 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:34:15 AM UTC 24
Peak memory 303660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250603337 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3250603337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_error.1016474531
Short name T559
Test name
Test status
Simulation time 31225081952 ps
CPU time 426.89 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:39:02 AM UTC 24
Peak memory 385708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016474531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1016474531 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.2373975922
Short name T527
Test name
Test status
Simulation time 1036384750 ps
CPU time 8.2 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:31:59 AM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373975922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2373975922 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.404500065
Short name T82
Test name
Test status
Simulation time 162378811 ps
CPU time 2.77 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:31:54 AM UTC 24
Peak memory 234104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404500065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.404500065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.201107285
Short name T623
Test name
Test status
Simulation time 15028715440 ps
CPU time 1583.42 seconds
Started Sep 04 07:27:54 AM UTC 24
Finished Sep 04 07:54:35 AM UTC 24
Peak memory 1116760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201107285 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.201107285 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.2657178863
Short name T540
Test name
Test status
Simulation time 29382378376 ps
CPU time 397.79 seconds
Started Sep 04 07:28:24 AM UTC 24
Finished Sep 04 07:35:07 AM UTC 24
Peak memory 561704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657178863 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2657178863 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.3571031165
Short name T517
Test name
Test status
Simulation time 8809736996 ps
CPU time 58.85 seconds
Started Sep 04 07:27:50 AM UTC 24
Finished Sep 04 07:28:51 AM UTC 24
Peak memory 234296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571031165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3571031165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.1007687192
Short name T541
Test name
Test status
Simulation time 5802724068 ps
CPU time 210.35 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:35:24 AM UTC 24
Peak memory 313924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007687192 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1007687192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1497054829
Short name T534
Test name
Test status
Simulation time 16271163 ps
CPU time 1.3 seconds
Started Sep 04 07:33:25 AM UTC 24
Finished Sep 04 07:33:27 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497054829 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1497054829 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_app.1374105415
Short name T535
Test name
Test status
Simulation time 5933282124 ps
CPU time 115.64 seconds
Started Sep 04 07:32:00 AM UTC 24
Finished Sep 04 07:33:58 AM UTC 24
Peak memory 264784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374105415 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1374105415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.1425417327
Short name T596
Test name
Test status
Simulation time 8160641608 ps
CPU time 847.71 seconds
Started Sep 04 07:31:55 AM UTC 24
Finished Sep 04 07:46:13 AM UTC 24
Peak memory 252456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425417327 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.1425417327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.3758234825
Short name T538
Test name
Test status
Simulation time 4942453230 ps
CPU time 127.97 seconds
Started Sep 04 07:32:22 AM UTC 24
Finished Sep 04 07:34:32 AM UTC 24
Peak memory 324220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758234825 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.3758234825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_error.552289083
Short name T549
Test name
Test status
Simulation time 42326502755 ps
CPU time 311.67 seconds
Started Sep 04 07:32:43 AM UTC 24
Finished Sep 04 07:37:59 AM UTC 24
Peak memory 471652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552289083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.552289083 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.1700767206
Short name T531
Test name
Test status
Simulation time 1795866421 ps
CPU time 5.11 seconds
Started Sep 04 07:33:13 AM UTC 24
Finished Sep 04 07:33:20 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700767206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1700767206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.1849158863
Short name T533
Test name
Test status
Simulation time 81330018 ps
CPU time 2.25 seconds
Started Sep 04 07:33:20 AM UTC 24
Finished Sep 04 07:33:24 AM UTC 24
Peak memory 232000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849158863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1849158863 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.2998281456
Short name T581
Test name
Test status
Simulation time 23526481566 ps
CPU time 675.7 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:43:14 AM UTC 24
Peak memory 1165880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998281456 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.2998281456 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.1713139486
Short name T539
Test name
Test status
Simulation time 4174762229 ps
CPU time 173.95 seconds
Started Sep 04 07:31:53 AM UTC 24
Finished Sep 04 07:34:51 AM UTC 24
Peak memory 346732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713139486 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1713139486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.4163544324
Short name T529
Test name
Test status
Simulation time 2605122867 ps
CPU time 49.98 seconds
Started Sep 04 07:31:50 AM UTC 24
Finished Sep 04 07:32:42 AM UTC 24
Peak memory 236200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163544324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4163544324 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.703965198
Short name T545
Test name
Test status
Simulation time 42222757965 ps
CPU time 188.7 seconds
Started Sep 04 07:33:23 AM UTC 24
Finished Sep 04 07:36:34 AM UTC 24
Peak memory 303728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703965198 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.703965198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.3273681338
Short name T546
Test name
Test status
Simulation time 20791481 ps
CPU time 1.2 seconds
Started Sep 04 07:36:33 AM UTC 24
Finished Sep 04 07:36:36 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273681338 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3273681338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_app.1137763722
Short name T552
Test name
Test status
Simulation time 14210296684 ps
CPU time 220.64 seconds
Started Sep 04 07:34:34 AM UTC 24
Finished Sep 04 07:38:18 AM UTC 24
Peak memory 377512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137763722 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.1137763722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.2420557817
Short name T650
Test name
Test status
Simulation time 26018572284 ps
CPU time 1562.05 seconds
Started Sep 04 07:34:16 AM UTC 24
Finished Sep 04 08:00:36 AM UTC 24
Peak memory 272992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420557817 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2420557817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3273563296
Short name T571
Test name
Test status
Simulation time 15091335563 ps
CPU time 430.91 seconds
Started Sep 04 07:34:52 AM UTC 24
Finished Sep 04 07:42:08 AM UTC 24
Peak memory 451148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273563296 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3273563296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_error.1649442048
Short name T551
Test name
Test status
Simulation time 16380921790 ps
CPU time 169.35 seconds
Started Sep 04 07:35:08 AM UTC 24
Finished Sep 04 07:38:00 AM UTC 24
Peak memory 334432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649442048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1649442048 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.1462195358
Short name T542
Test name
Test status
Simulation time 1427297967 ps
CPU time 16.79 seconds
Started Sep 04 07:35:25 AM UTC 24
Finished Sep 04 07:35:43 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462195358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1462195358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2484678893
Short name T543
Test name
Test status
Simulation time 37095753 ps
CPU time 2.08 seconds
Started Sep 04 07:35:44 AM UTC 24
Finished Sep 04 07:35:47 AM UTC 24
Peak memory 232068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484678893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2484678893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3278479621
Short name T719
Test name
Test status
Simulation time 108912082132 ps
CPU time 3548.6 seconds
Started Sep 04 07:33:58 AM UTC 24
Finished Sep 04 08:33:45 AM UTC 24
Peak memory 3814080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278479621 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3278479621 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1807649778
Short name T562
Test name
Test status
Simulation time 8782790667 ps
CPU time 296.33 seconds
Started Sep 04 07:34:10 AM UTC 24
Finished Sep 04 07:39:11 AM UTC 24
Peak memory 414304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807649778 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1807649778 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.1801055722
Short name T536
Test name
Test status
Simulation time 4971606466 ps
CPU time 39.92 seconds
Started Sep 04 07:33:28 AM UTC 24
Finished Sep 04 07:34:09 AM UTC 24
Peak memory 236140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801055722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1801055722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.688792895
Short name T548
Test name
Test status
Simulation time 2183575805 ps
CPU time 68.13 seconds
Started Sep 04 07:35:48 AM UTC 24
Finished Sep 04 07:36:58 AM UTC 24
Peak memory 275120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688792895 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.688792895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.2366035642
Short name T556
Test name
Test status
Simulation time 20902542 ps
CPU time 1.26 seconds
Started Sep 04 07:38:34 AM UTC 24
Finished Sep 04 07:38:37 AM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366035642 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2366035642 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_app.4231979764
Short name T560
Test name
Test status
Simulation time 1856800096 ps
CPU time 63.23 seconds
Started Sep 04 07:38:00 AM UTC 24
Finished Sep 04 07:39:05 AM UTC 24
Peak memory 252380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231979764 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.4231979764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.607215886
Short name T564
Test name
Test status
Simulation time 2487113239 ps
CPU time 148.41 seconds
Started Sep 04 07:36:59 AM UTC 24
Finished Sep 04 07:39:30 AM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607215886 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.607215886 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1559630496
Short name T572
Test name
Test status
Simulation time 9107360140 ps
CPU time 245.92 seconds
Started Sep 04 07:38:01 AM UTC 24
Finished Sep 04 07:42:10 AM UTC 24
Peak memory 357008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559630496 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1559630496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_error.1956675335
Short name T563
Test name
Test status
Simulation time 1091215828 ps
CPU time 79.26 seconds
Started Sep 04 07:38:02 AM UTC 24
Finished Sep 04 07:39:23 AM UTC 24
Peak memory 264672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956675335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1956675335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.3971275295
Short name T553
Test name
Test status
Simulation time 262634296 ps
CPU time 4.5 seconds
Started Sep 04 07:38:19 AM UTC 24
Finished Sep 04 07:38:24 AM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971275295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3971275295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3778435954
Short name T554
Test name
Test status
Simulation time 71552596 ps
CPU time 2.2 seconds
Started Sep 04 07:38:25 AM UTC 24
Finished Sep 04 07:38:28 AM UTC 24
Peak memory 234048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778435954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3778435954 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.2545227007
Short name T721
Test name
Test status
Simulation time 135898490237 ps
CPU time 3630.77 seconds
Started Sep 04 07:36:37 AM UTC 24
Finished Sep 04 08:37:46 AM UTC 24
Peak memory 3949204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545227007 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.2545227007 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.3682467342
Short name T550
Test name
Test status
Simulation time 3276476902 ps
CPU time 64.43 seconds
Started Sep 04 07:36:53 AM UTC 24
Finished Sep 04 07:37:59 AM UTC 24
Peak memory 270892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682467342 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.3682467342 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.572939713
Short name T557
Test name
Test status
Simulation time 4550698561 ps
CPU time 132.23 seconds
Started Sep 04 07:36:36 AM UTC 24
Finished Sep 04 07:38:51 AM UTC 24
Peak memory 238164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572939713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.572939713 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.3253734907
Short name T558
Test name
Test status
Simulation time 271824137 ps
CPU time 27.42 seconds
Started Sep 04 07:38:29 AM UTC 24
Finished Sep 04 07:38:58 AM UTC 24
Peak memory 235792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253734907 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3253734907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.3544825130
Short name T567
Test name
Test status
Simulation time 13292019 ps
CPU time 1.26 seconds
Started Sep 04 07:39:47 AM UTC 24
Finished Sep 04 07:39:49 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544825130 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3544825130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_app.98862122
Short name T570
Test name
Test status
Simulation time 1732388322 ps
CPU time 138.12 seconds
Started Sep 04 07:39:06 AM UTC 24
Finished Sep 04 07:41:27 AM UTC 24
Peak memory 270832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98862122 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.98862122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2520372325
Short name T645
Test name
Test status
Simulation time 48646952121 ps
CPU time 1248.43 seconds
Started Sep 04 07:39:03 AM UTC 24
Finished Sep 04 08:00:06 AM UTC 24
Peak memory 254504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520372325 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2520372325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.1255212458
Short name T592
Test name
Test status
Simulation time 13003361662 ps
CPU time 362.36 seconds
Started Sep 04 07:39:08 AM UTC 24
Finished Sep 04 07:45:16 AM UTC 24
Peak memory 330280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255212458 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.1255212458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_error.3195471038
Short name T578
Test name
Test status
Simulation time 2771210750 ps
CPU time 221.5 seconds
Started Sep 04 07:39:11 AM UTC 24
Finished Sep 04 07:42:56 AM UTC 24
Peak memory 328296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195471038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3195471038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.1990503657
Short name T566
Test name
Test status
Simulation time 5364514818 ps
CPU time 21.05 seconds
Started Sep 04 07:39:24 AM UTC 24
Finished Sep 04 07:39:46 AM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990503657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.1990503657 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.3121258660
Short name T565
Test name
Test status
Simulation time 139058920 ps
CPU time 2.18 seconds
Started Sep 04 07:39:31 AM UTC 24
Finished Sep 04 07:39:34 AM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121258660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3121258660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.1652243574
Short name T720
Test name
Test status
Simulation time 523933279611 ps
CPU time 3288.2 seconds
Started Sep 04 07:38:52 AM UTC 24
Finished Sep 04 08:34:15 AM UTC 24
Peak memory 3613232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652243574 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.1652243574 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2517703563
Short name T585
Test name
Test status
Simulation time 46139847394 ps
CPU time 319.73 seconds
Started Sep 04 07:38:59 AM UTC 24
Finished Sep 04 07:44:24 AM UTC 24
Peak memory 401948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517703563 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2517703563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.885921540
Short name T568
Test name
Test status
Simulation time 2175686414 ps
CPU time 82.29 seconds
Started Sep 04 07:38:37 AM UTC 24
Finished Sep 04 07:40:02 AM UTC 24
Peak memory 236044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885921540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.885921540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.207105843
Short name T701
Test name
Test status
Simulation time 82402142747 ps
CPU time 1819.67 seconds
Started Sep 04 07:39:35 AM UTC 24
Finished Sep 04 08:10:15 AM UTC 24
Peak memory 678832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207105843 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.207105843 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.3368753854
Short name T577
Test name
Test status
Simulation time 18510870 ps
CPU time 1.16 seconds
Started Sep 04 07:42:22 AM UTC 24
Finished Sep 04 07:42:24 AM UTC 24
Peak memory 226720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368753854 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3368753854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_app.2921912656
Short name T579
Test name
Test status
Simulation time 2367452907 ps
CPU time 50.92 seconds
Started Sep 04 07:42:10 AM UTC 24
Finished Sep 04 07:43:02 AM UTC 24
Peak memory 244264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921912656 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2921912656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.2261037610
Short name T626
Test name
Test status
Simulation time 20203761676 ps
CPU time 864.08 seconds
Started Sep 04 07:41:28 AM UTC 24
Finished Sep 04 07:56:02 AM UTC 24
Peak memory 252464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261037610 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2261037610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.10630165
Short name T584
Test name
Test status
Simulation time 6113925513 ps
CPU time 114.92 seconds
Started Sep 04 07:42:11 AM UTC 24
Finished Sep 04 07:44:08 AM UTC 24
Peak memory 266860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10630165 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.10630165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_error.1456455734
Short name T604
Test name
Test status
Simulation time 42363062716 ps
CPU time 402.3 seconds
Started Sep 04 07:42:14 AM UTC 24
Finished Sep 04 07:49:02 AM UTC 24
Peak memory 526760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456455734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1456455734 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.1542680449
Short name T576
Test name
Test status
Simulation time 325048597 ps
CPU time 5.29 seconds
Started Sep 04 07:42:14 AM UTC 24
Finished Sep 04 07:42:20 AM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542680449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1542680449 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.2997744790
Short name T81
Test name
Test status
Simulation time 61537777 ps
CPU time 2.08 seconds
Started Sep 04 07:42:17 AM UTC 24
Finished Sep 04 07:42:20 AM UTC 24
Peak memory 234156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997744790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2997744790 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2617884135
Short name T658
Test name
Test status
Simulation time 156240592221 ps
CPU time 1282.96 seconds
Started Sep 04 07:40:02 AM UTC 24
Finished Sep 04 08:01:41 AM UTC 24
Peak memory 1380916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617884135 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2617884135 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1133381987
Short name T573
Test name
Test status
Simulation time 980206187 ps
CPU time 99.37 seconds
Started Sep 04 07:40:32 AM UTC 24
Finished Sep 04 07:42:13 AM UTC 24
Peak memory 258464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133381987 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1133381987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.2690597744
Short name T569
Test name
Test status
Simulation time 6385052047 ps
CPU time 39.16 seconds
Started Sep 04 07:39:50 AM UTC 24
Finished Sep 04 07:40:31 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690597744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.2690597744 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.2266589174
Short name T660
Test name
Test status
Simulation time 24836785893 ps
CPU time 1146.9 seconds
Started Sep 04 07:42:22 AM UTC 24
Finished Sep 04 08:01:42 AM UTC 24
Peak memory 547700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266589174 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2266589174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.3354091939
Short name T206
Test name
Test status
Simulation time 13597918 ps
CPU time 1.27 seconds
Started Sep 04 06:32:03 AM UTC 24
Finished Sep 04 06:32:06 AM UTC 24
Peak memory 225044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354091939 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3354091939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_app.4247349409
Short name T217
Test name
Test status
Simulation time 33222975003 ps
CPU time 256.16 seconds
Started Sep 04 06:30:49 AM UTC 24
Finished Sep 04 06:35:09 AM UTC 24
Peak memory 414316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247349409 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.4247349409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.2075487806
Short name T218
Test name
Test status
Simulation time 25111277920 ps
CPU time 259.52 seconds
Started Sep 04 06:30:53 AM UTC 24
Finished Sep 04 06:35:17 AM UTC 24
Peak memory 328228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075487806 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2075487806 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.1986693693
Short name T146
Test name
Test status
Simulation time 3329559888 ps
CPU time 173.95 seconds
Started Sep 04 06:29:38 AM UTC 24
Finished Sep 04 06:32:34 AM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986693693 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1986693693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.4097215584
Short name T205
Test name
Test status
Simulation time 6776036062 ps
CPU time 43.5 seconds
Started Sep 04 06:31:18 AM UTC 24
Finished Sep 04 06:32:03 AM UTC 24
Peak memory 234168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097215584 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.4097215584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.1206605311
Short name T79
Test name
Test status
Simulation time 19242601 ps
CPU time 1.53 seconds
Started Sep 04 06:31:30 AM UTC 24
Finished Sep 04 06:31:33 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206605311 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1206605311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.177939277
Short name T207
Test name
Test status
Simulation time 2669200333 ps
CPU time 62.33 seconds
Started Sep 04 06:31:34 AM UTC 24
Finished Sep 04 06:32:38 AM UTC 24
Peak memory 236068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177939277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.177939277 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3453898307
Short name T77
Test name
Test status
Simulation time 2383651876 ps
CPU time 53.04 seconds
Started Sep 04 06:30:55 AM UTC 24
Finished Sep 04 06:31:49 AM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453898307 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3453898307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_error.1784851793
Short name T86
Test name
Test status
Simulation time 1799515305 ps
CPU time 110.78 seconds
Started Sep 04 06:31:06 AM UTC 24
Finished Sep 04 06:32:59 AM UTC 24
Peak memory 264620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784851793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1784851793 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.3330744112
Short name T123
Test name
Test status
Simulation time 1656222392 ps
CPU time 20.59 seconds
Started Sep 04 06:31:08 AM UTC 24
Finished Sep 04 06:31:29 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330744112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3330744112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.1473830243
Short name T38
Test name
Test status
Simulation time 215979692 ps
CPU time 1.88 seconds
Started Sep 04 06:31:47 AM UTC 24
Finished Sep 04 06:31:50 AM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473830243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1473830243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1563511615
Short name T476
Test name
Test status
Simulation time 69279049980 ps
CPU time 3108.73 seconds
Started Sep 04 06:29:13 AM UTC 24
Finished Sep 04 07:21:37 AM UTC 24
Peak memory 3275264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563511615 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1563511615 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.3036747200
Short name T92
Test name
Test status
Simulation time 9677380744 ps
CPU time 311.86 seconds
Started Sep 04 06:31:04 AM UTC 24
Finished Sep 04 06:36:21 AM UTC 24
Peak memory 457716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036747200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3036747200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.141381441
Short name T124
Test name
Test status
Simulation time 14253138659 ps
CPU time 48.3 seconds
Started Sep 04 06:31:51 AM UTC 24
Finished Sep 04 06:32:41 AM UTC 24
Peak memory 282452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141381441 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.141381441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.3741444884
Short name T219
Test name
Test status
Simulation time 15426074520 ps
CPU time 347.74 seconds
Started Sep 04 06:29:35 AM UTC 24
Finished Sep 04 06:35:28 AM UTC 24
Peak memory 518744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741444884 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3741444884 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.1048937913
Short name T193
Test name
Test status
Simulation time 1945121978 ps
CPU time 62.46 seconds
Started Sep 04 06:29:00 AM UTC 24
Finished Sep 04 06:30:04 AM UTC 24
Peak memory 234112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048937913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1048937913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.1063877466
Short name T188
Test name
Test status
Simulation time 4495127806 ps
CPU time 126.34 seconds
Started Sep 04 06:31:50 AM UTC 24
Finished Sep 04 06:33:59 AM UTC 24
Peak memory 281200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063877466 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1063877466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1737160708
Short name T202
Test name
Test status
Simulation time 861861077 ps
CPU time 5.27 seconds
Started Sep 04 06:30:36 AM UTC 24
Finished Sep 04 06:30:43 AM UTC 24
Peak memory 230016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737160708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1737160708 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.4240813355
Short name T203
Test name
Test status
Simulation time 81476388 ps
CPU time 4.44 seconds
Started Sep 04 06:30:43 AM UTC 24
Finished Sep 04 06:30:49 AM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240813355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4240813355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.3038237689
Short name T201
Test name
Test status
Simulation time 2851556632 ps
CPU time 51.47 seconds
Started Sep 04 06:29:43 AM UTC 24
Finished Sep 04 06:30:36 AM UTC 24
Peak memory 262624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038237689 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.3038237689 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.2450239361
Short name T356
Test name
Test status
Simulation time 17195690122 ps
CPU time 1919.58 seconds
Started Sep 04 06:29:56 AM UTC 24
Finished Sep 04 07:02:16 AM UTC 24
Peak memory 1108428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450239361 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2450239361 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.4111974437
Short name T204
Test name
Test status
Simulation time 1873534747 ps
CPU time 46.24 seconds
Started Sep 04 06:30:05 AM UTC 24
Finished Sep 04 06:30:53 AM UTC 24
Peak memory 242092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111974437 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.4111974437 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.2312284077
Short name T200
Test name
Test status
Simulation time 1093965441 ps
CPU time 26.13 seconds
Started Sep 04 06:30:06 AM UTC 24
Finished Sep 04 06:30:33 AM UTC 24
Peak memory 234016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312284077 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2312284077 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.643632432
Short name T214
Test name
Test status
Simulation time 19901102722 ps
CPU time 229.95 seconds
Started Sep 04 06:30:08 AM UTC 24
Finished Sep 04 06:34:01 AM UTC 24
Peak memory 442824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643632432 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.643632432 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.2454575765
Short name T588
Test name
Test status
Simulation time 63796140 ps
CPU time 1.21 seconds
Started Sep 04 07:44:29 AM UTC 24
Finished Sep 04 07:44:31 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454575765 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2454575765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_app.3571273813
Short name T595
Test name
Test status
Simulation time 6735322144 ps
CPU time 171.6 seconds
Started Sep 04 07:43:15 AM UTC 24
Finished Sep 04 07:46:09 AM UTC 24
Peak memory 287336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571273813 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3571273813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.2458189345
Short name T704
Test name
Test status
Simulation time 81123665755 ps
CPU time 1642.77 seconds
Started Sep 04 07:43:06 AM UTC 24
Finished Sep 04 08:10:49 AM UTC 24
Peak memory 272936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458189345 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2458189345 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.1232878397
Short name T605
Test name
Test status
Simulation time 12531302945 ps
CPU time 363.21 seconds
Started Sep 04 07:43:27 AM UTC 24
Finished Sep 04 07:49:35 AM UTC 24
Peak memory 414312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232878397 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1232878397 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_error.936470614
Short name T606
Test name
Test status
Simulation time 37343326431 ps
CPU time 365.98 seconds
Started Sep 04 07:43:43 AM UTC 24
Finished Sep 04 07:49:54 AM UTC 24
Peak memory 463408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936470614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.936470614 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.4094053236
Short name T587
Test name
Test status
Simulation time 1347421872 ps
CPU time 17.5 seconds
Started Sep 04 07:44:09 AM UTC 24
Finished Sep 04 07:44:28 AM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094053236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.4094053236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.4059677062
Short name T586
Test name
Test status
Simulation time 39192881 ps
CPU time 1.94 seconds
Started Sep 04 07:44:24 AM UTC 24
Finished Sep 04 07:44:27 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059677062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.4059677062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2197585729
Short name T671
Test name
Test status
Simulation time 10758763995 ps
CPU time 1196.16 seconds
Started Sep 04 07:42:57 AM UTC 24
Finished Sep 04 08:03:07 AM UTC 24
Peak memory 897656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197585729 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2197585729 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.2944487858
Short name T614
Test name
Test status
Simulation time 24821040884 ps
CPU time 516.07 seconds
Started Sep 04 07:43:03 AM UTC 24
Finished Sep 04 07:51:45 AM UTC 24
Peak memory 678496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944487858 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2944487858 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.1076275033
Short name T582
Test name
Test status
Simulation time 4713555756 ps
CPU time 59 seconds
Started Sep 04 07:42:25 AM UTC 24
Finished Sep 04 07:43:25 AM UTC 24
Peak memory 236112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076275033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1076275033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.2871483083
Short name T644
Test name
Test status
Simulation time 10960572396 ps
CPU time 902.92 seconds
Started Sep 04 07:44:29 AM UTC 24
Finished Sep 04 07:59:41 AM UTC 24
Peak memory 674396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871483083 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2871483083 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.3980287063
Short name T601
Test name
Test status
Simulation time 35586131 ps
CPU time 1.23 seconds
Started Sep 04 07:46:42 AM UTC 24
Finished Sep 04 07:46:44 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980287063 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3980287063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_app.1399520689
Short name T610
Test name
Test status
Simulation time 141084482879 ps
CPU time 312.5 seconds
Started Sep 04 07:45:32 AM UTC 24
Finished Sep 04 07:50:49 AM UTC 24
Peak memory 477792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399520689 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1399520689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.1176910580
Short name T613
Test name
Test status
Simulation time 6008494677 ps
CPU time 377.74 seconds
Started Sep 04 07:45:16 AM UTC 24
Finished Sep 04 07:51:40 AM UTC 24
Peak memory 238168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176910580 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1176910580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.54294937
Short name T618
Test name
Test status
Simulation time 35310164494 ps
CPU time 477.1 seconds
Started Sep 04 07:45:47 AM UTC 24
Finished Sep 04 07:53:50 AM UTC 24
Peak memory 533088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54294937 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.54294937 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1572551323
Short name T602
Test name
Test status
Simulation time 5021649197 ps
CPU time 138.75 seconds
Started Sep 04 07:46:10 AM UTC 24
Finished Sep 04 07:48:32 AM UTC 24
Peak memory 285232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572551323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1572551323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.3512221186
Short name T597
Test name
Test status
Simulation time 2137942466 ps
CPU time 21.82 seconds
Started Sep 04 07:46:13 AM UTC 24
Finished Sep 04 07:46:36 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512221186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.3512221186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.2657520792
Short name T599
Test name
Test status
Simulation time 39612711 ps
CPU time 2.03 seconds
Started Sep 04 07:46:38 AM UTC 24
Finished Sep 04 07:46:41 AM UTC 24
Peak memory 234116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657520792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.2657520792 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.547376858
Short name T724
Test name
Test status
Simulation time 376645129301 ps
CPU time 4289.58 seconds
Started Sep 04 07:44:35 AM UTC 24
Finished Sep 04 08:56:51 AM UTC 24
Peak memory 4235928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547376858 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.547376858 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.294687333
Short name T620
Test name
Test status
Simulation time 83700611358 ps
CPU time 561.27 seconds
Started Sep 04 07:45:00 AM UTC 24
Finished Sep 04 07:54:29 AM UTC 24
Peak memory 539252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294687333 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.294687333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.2886566092
Short name T594
Test name
Test status
Simulation time 3615633358 ps
CPU time 72.91 seconds
Started Sep 04 07:44:32 AM UTC 24
Finished Sep 04 07:45:47 AM UTC 24
Peak memory 236076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886566092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2886566092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.1778427221
Short name T690
Test name
Test status
Simulation time 28334170382 ps
CPU time 1206.98 seconds
Started Sep 04 07:46:40 AM UTC 24
Finished Sep 04 08:07:01 AM UTC 24
Peak memory 1448544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778427221 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.1778427221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.2999727943
Short name T611
Test name
Test status
Simulation time 11349199 ps
CPU time 1.26 seconds
Started Sep 04 07:50:50 AM UTC 24
Finished Sep 04 07:50:52 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999727943 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2999727943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_app.3424497752
Short name T615
Test name
Test status
Simulation time 11490435042 ps
CPU time 175.03 seconds
Started Sep 04 07:49:03 AM UTC 24
Finished Sep 04 07:52:01 AM UTC 24
Peak memory 289312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424497752 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3424497752 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.857417566
Short name T697
Test name
Test status
Simulation time 72888461634 ps
CPU time 1196.72 seconds
Started Sep 04 07:48:34 AM UTC 24
Finished Sep 04 08:08:46 AM UTC 24
Peak memory 262680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857417566 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.857417566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.3045248231
Short name T607
Test name
Test status
Simulation time 5811254753 ps
CPU time 45.65 seconds
Started Sep 04 07:49:37 AM UTC 24
Finished Sep 04 07:50:24 AM UTC 24
Peak memory 244348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045248231 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.3045248231 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_error.169934632
Short name T627
Test name
Test status
Simulation time 21043614681 ps
CPU time 380.13 seconds
Started Sep 04 07:49:55 AM UTC 24
Finished Sep 04 07:56:20 AM UTC 24
Peak memory 350824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169934632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.169934632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.405936
Short name T608
Test name
Test status
Simulation time 11387870634 ps
CPU time 17.16 seconds
Started Sep 04 07:50:25 AM UTC 24
Finished Sep 04 07:50:43 AM UTC 24
Peak memory 230104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ
=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.405936 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.1435850515
Short name T609
Test name
Test status
Simulation time 40108800 ps
CPU time 2.02 seconds
Started Sep 04 07:50:44 AM UTC 24
Finished Sep 04 07:50:47 AM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435850515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1435850515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.3131805601
Short name T677
Test name
Test status
Simulation time 62310057002 ps
CPU time 1046.36 seconds
Started Sep 04 07:46:45 AM UTC 24
Finished Sep 04 08:04:24 AM UTC 24
Peak memory 1327664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131805601 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.3131805601 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.4147824803
Short name T653
Test name
Test status
Simulation time 94755187283 ps
CPU time 743.01 seconds
Started Sep 04 07:48:33 AM UTC 24
Finished Sep 04 08:01:06 AM UTC 24
Peak memory 676424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147824803 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.4147824803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.1755420241
Short name T603
Test name
Test status
Simulation time 40206463088 ps
CPU time 109.04 seconds
Started Sep 04 07:46:42 AM UTC 24
Finished Sep 04 07:48:33 AM UTC 24
Peak memory 238164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755420241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1755420241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2594383069
Short name T616
Test name
Test status
Simulation time 3805471074 ps
CPU time 118.12 seconds
Started Sep 04 07:50:48 AM UTC 24
Finished Sep 04 07:52:49 AM UTC 24
Peak memory 311888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594383069 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2594383069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.48477795
Short name T622
Test name
Test status
Simulation time 24827672 ps
CPU time 1.3 seconds
Started Sep 04 07:54:31 AM UTC 24
Finished Sep 04 07:54:34 AM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48477795 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.48477795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_app.2861649328
Short name T624
Test name
Test status
Simulation time 7545952521 ps
CPU time 170.11 seconds
Started Sep 04 07:52:02 AM UTC 24
Finished Sep 04 07:54:55 AM UTC 24
Peak memory 361056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861649328 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2861649328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.510874045
Short name T666
Test name
Test status
Simulation time 60647010923 ps
CPU time 637.05 seconds
Started Sep 04 07:51:46 AM UTC 24
Finished Sep 04 08:02:31 AM UTC 24
Peak memory 254568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510874045 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.510874045 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.327269825
Short name T78
Test name
Test status
Simulation time 36893809479 ps
CPU time 394.91 seconds
Started Sep 04 07:52:50 AM UTC 24
Finished Sep 04 07:59:30 AM UTC 24
Peak memory 514728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327269825 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.327269825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_error.2718729339
Short name T642
Test name
Test status
Simulation time 7711854210 ps
CPU time 347.66 seconds
Started Sep 04 07:53:35 AM UTC 24
Finished Sep 04 07:59:27 AM UTC 24
Peak memory 459372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718729339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2718729339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.3976570441
Short name T619
Test name
Test status
Simulation time 5212040711 ps
CPU time 17.58 seconds
Started Sep 04 07:53:51 AM UTC 24
Finished Sep 04 07:54:10 AM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976570441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3976570441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.370115544
Short name T621
Test name
Test status
Simulation time 1286172564 ps
CPU time 19.39 seconds
Started Sep 04 07:54:10 AM UTC 24
Finished Sep 04 07:54:31 AM UTC 24
Peak memory 244768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370115544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.370115544 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.975553253
Short name T713
Test name
Test status
Simulation time 29532876465 ps
CPU time 1589.2 seconds
Started Sep 04 07:51:17 AM UTC 24
Finished Sep 04 08:18:04 AM UTC 24
Peak memory 1077928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975553253 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.975553253 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.1519111748
Short name T636
Test name
Test status
Simulation time 14468866615 ps
CPU time 358.11 seconds
Started Sep 04 07:51:40 AM UTC 24
Finished Sep 04 07:57:43 AM UTC 24
Peak memory 572076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519111748 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1519111748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.3746830421
Short name T612
Test name
Test status
Simulation time 2193490482 ps
CPU time 22.26 seconds
Started Sep 04 07:50:53 AM UTC 24
Finished Sep 04 07:51:16 AM UTC 24
Peak memory 232160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746830421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.3746830421 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.4291049825
Short name T637
Test name
Test status
Simulation time 10174002614 ps
CPU time 221.78 seconds
Started Sep 04 07:54:30 AM UTC 24
Finished Sep 04 07:58:16 AM UTC 24
Peak memory 311896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291049825 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4291049825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.174140498
Short name T633
Test name
Test status
Simulation time 103834040 ps
CPU time 1.32 seconds
Started Sep 04 07:57:05 AM UTC 24
Finished Sep 04 07:57:07 AM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174140498 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.174140498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_app.4030469997
Short name T651
Test name
Test status
Simulation time 4340170089 ps
CPU time 274.57 seconds
Started Sep 04 07:56:04 AM UTC 24
Finished Sep 04 08:00:42 AM UTC 24
Peak memory 320028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030469997 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.4030469997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.2325524276
Short name T635
Test name
Test status
Simulation time 1271805908 ps
CPU time 140.5 seconds
Started Sep 04 07:55:10 AM UTC 24
Finished Sep 04 07:57:33 AM UTC 24
Peak memory 235936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325524276 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2325524276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.1776117621
Short name T640
Test name
Test status
Simulation time 13979337515 ps
CPU time 162.29 seconds
Started Sep 04 07:56:22 AM UTC 24
Finished Sep 04 07:59:07 AM UTC 24
Peak memory 357040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776117621 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1776117621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_error.4200563754
Short name T691
Test name
Test status
Simulation time 82939406314 ps
CPU time 638.43 seconds
Started Sep 04 07:56:40 AM UTC 24
Finished Sep 04 08:07:27 AM UTC 24
Peak memory 676464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200563754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.4200563754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.4209284727
Short name T630
Test name
Test status
Simulation time 99960533 ps
CPU time 2.2 seconds
Started Sep 04 07:56:55 AM UTC 24
Finished Sep 04 07:56:58 AM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209284727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.4209284727 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.1317884426
Short name T631
Test name
Test status
Simulation time 84683267 ps
CPU time 2.24 seconds
Started Sep 04 07:56:59 AM UTC 24
Finished Sep 04 07:57:03 AM UTC 24
Peak memory 232060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317884426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1317884426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.553007560
Short name T706
Test name
Test status
Simulation time 42691200956 ps
CPU time 968.77 seconds
Started Sep 04 07:54:37 AM UTC 24
Finished Sep 04 08:10:58 AM UTC 24
Peak memory 1178160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553007560 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.553007560 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.535255108
Short name T659
Test name
Test status
Simulation time 9281112529 ps
CPU time 400.47 seconds
Started Sep 04 07:54:56 AM UTC 24
Finished Sep 04 08:01:42 AM UTC 24
Peak memory 477796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535255108 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.535255108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.2469234188
Short name T625
Test name
Test status
Simulation time 3405056336 ps
CPU time 32.68 seconds
Started Sep 04 07:54:34 AM UTC 24
Finished Sep 04 07:55:09 AM UTC 24
Peak memory 236132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469234188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2469234188 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.1336525401
Short name T684
Test name
Test status
Simulation time 117015736765 ps
CPU time 495.35 seconds
Started Sep 04 07:57:04 AM UTC 24
Finished Sep 04 08:05:25 AM UTC 24
Peak memory 484076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336525401 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1336525401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.1213711037
Short name T643
Test name
Test status
Simulation time 20268396 ps
CPU time 1.24 seconds
Started Sep 04 07:59:29 AM UTC 24
Finished Sep 04 07:59:31 AM UTC 24
Peak memory 224620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213711037 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1213711037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_app.331918902
Short name T675
Test name
Test status
Simulation time 5334370111 ps
CPU time 328.11 seconds
Started Sep 04 07:58:17 AM UTC 24
Finished Sep 04 08:03:50 AM UTC 24
Peak memory 336500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331918902 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.331918902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2324820088
Short name T702
Test name
Test status
Simulation time 71888682422 ps
CPU time 771.3 seconds
Started Sep 04 07:57:44 AM UTC 24
Finished Sep 04 08:10:45 AM UTC 24
Peak memory 254628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324820088 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2324820088 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3028367431
Short name T639
Test name
Test status
Simulation time 53979560 ps
CPU time 3.06 seconds
Started Sep 04 07:58:55 AM UTC 24
Finished Sep 04 07:58:59 AM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028367431 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3028367431 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_error.2436647713
Short name T696
Test name
Test status
Simulation time 24745829595 ps
CPU time 571.68 seconds
Started Sep 04 07:59:00 AM UTC 24
Finished Sep 04 08:08:40 AM UTC 24
Peak memory 645756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436647713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2436647713 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.348329330
Short name T641
Test name
Test status
Simulation time 3937153103 ps
CPU time 14.98 seconds
Started Sep 04 07:59:07 AM UTC 24
Finished Sep 04 07:59:24 AM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348329330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.348329330 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2350105539
Short name T56
Test name
Test status
Simulation time 59291839 ps
CPU time 2.32 seconds
Started Sep 04 07:59:25 AM UTC 24
Finished Sep 04 07:59:28 AM UTC 24
Peak memory 232000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350105539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2350105539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.476687325
Short name T680
Test name
Test status
Simulation time 10797662934 ps
CPU time 442.25 seconds
Started Sep 04 07:57:14 AM UTC 24
Finished Sep 04 08:04:42 AM UTC 24
Peak memory 713316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476687325 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.476687325 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.124769397
Short name T646
Test name
Test status
Simulation time 5482286355 ps
CPU time 164.05 seconds
Started Sep 04 07:57:34 AM UTC 24
Finished Sep 04 08:00:22 AM UTC 24
Peak memory 338528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124769397 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.124769397 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2707178813
Short name T638
Test name
Test status
Simulation time 3001631019 ps
CPU time 103.77 seconds
Started Sep 04 07:57:08 AM UTC 24
Finished Sep 04 07:58:54 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707178813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2707178813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.651604817
Short name T695
Test name
Test status
Simulation time 6819335149 ps
CPU time 521.13 seconds
Started Sep 04 07:59:28 AM UTC 24
Finished Sep 04 08:08:16 AM UTC 24
Peak memory 322424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651604817 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.651604817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.1025799395
Short name T649
Test name
Test status
Simulation time 53521523 ps
CPU time 1.23 seconds
Started Sep 04 08:00:27 AM UTC 24
Finished Sep 04 08:00:30 AM UTC 24
Peak memory 224852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025799395 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1025799395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_app.4132021660
Short name T682
Test name
Test status
Simulation time 6184945356 ps
CPU time 284.36 seconds
Started Sep 04 08:00:04 AM UTC 24
Finished Sep 04 08:04:53 AM UTC 24
Peak memory 324192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132021660 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.4132021660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.671717643
Short name T708
Test name
Test status
Simulation time 61574629788 ps
CPU time 795.76 seconds
Started Sep 04 07:59:49 AM UTC 24
Finished Sep 04 08:13:14 AM UTC 24
Peak memory 258584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671717643 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.671717643 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2367902497
Short name T679
Test name
Test status
Simulation time 9780735379 ps
CPU time 270.79 seconds
Started Sep 04 08:00:06 AM UTC 24
Finished Sep 04 08:04:41 AM UTC 24
Peak memory 367124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367902497 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2367902497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_error.1785118582
Short name T668
Test name
Test status
Simulation time 8589578957 ps
CPU time 138.01 seconds
Started Sep 04 08:00:19 AM UTC 24
Finished Sep 04 08:02:40 AM UTC 24
Peak memory 350760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785118582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1785118582 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.957447455
Short name T647
Test name
Test status
Simulation time 240003104 ps
CPU time 2.36 seconds
Started Sep 04 08:00:22 AM UTC 24
Finished Sep 04 08:00:26 AM UTC 24
Peak memory 227728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957447455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.957447455 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.3792396641
Short name T648
Test name
Test status
Simulation time 349268901 ps
CPU time 1.72 seconds
Started Sep 04 08:00:24 AM UTC 24
Finished Sep 04 08:00:27 AM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792396641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3792396641 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.3473209182
Short name T715
Test name
Test status
Simulation time 34039792029 ps
CPU time 1244.13 seconds
Started Sep 04 07:59:32 AM UTC 24
Finished Sep 04 08:20:31 AM UTC 24
Peak memory 1649260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473209182 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.3473209182 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.2174828363
Short name T673
Test name
Test status
Simulation time 36555000113 ps
CPU time 209.98 seconds
Started Sep 04 07:59:43 AM UTC 24
Finished Sep 04 08:03:16 AM UTC 24
Peak memory 387704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174828363 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2174828363 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.406209314
Short name T652
Test name
Test status
Simulation time 2695351582 ps
CPU time 77.39 seconds
Started Sep 04 07:59:31 AM UTC 24
Finished Sep 04 08:00:50 AM UTC 24
Peak memory 236140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406209314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.406209314 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1737847380
Short name T711
Test name
Test status
Simulation time 24666075497 ps
CPU time 815.94 seconds
Started Sep 04 08:00:27 AM UTC 24
Finished Sep 04 08:14:13 AM UTC 24
Peak memory 391592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737847380 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1737847380 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.1044425762
Short name T656
Test name
Test status
Simulation time 38375885 ps
CPU time 1.2 seconds
Started Sep 04 08:01:22 AM UTC 24
Finished Sep 04 08:01:25 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044425762 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1044425762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_app.2309038460
Short name T664
Test name
Test status
Simulation time 2989807822 ps
CPU time 90.74 seconds
Started Sep 04 08:00:49 AM UTC 24
Finished Sep 04 08:02:22 AM UTC 24
Peak memory 281148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309038460 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2309038460 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.3621652134
Short name T710
Test name
Test status
Simulation time 71427675505 ps
CPU time 783.89 seconds
Started Sep 04 08:00:44 AM UTC 24
Finished Sep 04 08:13:57 AM UTC 24
Peak memory 252452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621652134 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3621652134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.2956888276
Short name T687
Test name
Test status
Simulation time 73624931579 ps
CPU time 345.37 seconds
Started Sep 04 08:00:51 AM UTC 24
Finished Sep 04 08:06:41 AM UTC 24
Peak memory 463596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956888276 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2956888276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_error.555579786
Short name T693
Test name
Test status
Simulation time 13681586005 ps
CPU time 406 seconds
Started Sep 04 08:00:56 AM UTC 24
Finished Sep 04 08:07:48 AM UTC 24
Peak memory 524972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555579786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.555579786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.26848738
Short name T654
Test name
Test status
Simulation time 354867323 ps
CPU time 5.48 seconds
Started Sep 04 08:01:07 AM UTC 24
Finished Sep 04 08:01:13 AM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26848738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.26848738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.664361912
Short name T655
Test name
Test status
Simulation time 124831852 ps
CPU time 2.04 seconds
Started Sep 04 08:01:14 AM UTC 24
Finished Sep 04 08:01:17 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664361912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.664361912 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.1663133191
Short name T723
Test name
Test status
Simulation time 25253701549 ps
CPU time 2589.5 seconds
Started Sep 04 08:00:37 AM UTC 24
Finished Sep 04 08:44:16 AM UTC 24
Peak memory 1684020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663133191 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.1663133191 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.2141372779
Short name T667
Test name
Test status
Simulation time 2754301960 ps
CPU time 114.92 seconds
Started Sep 04 08:00:41 AM UTC 24
Finished Sep 04 08:02:38 AM UTC 24
Peak memory 307808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141372779 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2141372779 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.4062832416
Short name T657
Test name
Test status
Simulation time 4387697156 ps
CPU time 57.07 seconds
Started Sep 04 08:00:30 AM UTC 24
Finished Sep 04 08:01:29 AM UTC 24
Peak memory 236112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062832416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.4062832416 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.2525993662
Short name T709
Test name
Test status
Simulation time 18449046442 ps
CPU time 718.52 seconds
Started Sep 04 08:01:18 AM UTC 24
Finished Sep 04 08:13:26 AM UTC 24
Peak memory 351072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525993662 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2525993662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.310882147
Short name T665
Test name
Test status
Simulation time 29240140 ps
CPU time 1.27 seconds
Started Sep 04 08:02:23 AM UTC 24
Finished Sep 04 08:02:25 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310882147 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.310882147 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_app.2686275638
Short name T678
Test name
Test status
Simulation time 14349906686 ps
CPU time 160.79 seconds
Started Sep 04 08:01:43 AM UTC 24
Finished Sep 04 08:04:27 AM UTC 24
Peak memory 379496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686275638 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.2686275638 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.2263917654
Short name T700
Test name
Test status
Simulation time 8487282508 ps
CPU time 506.13 seconds
Started Sep 04 08:01:42 AM UTC 24
Finished Sep 04 08:10:15 AM UTC 24
Peak memory 252456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263917654 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2263917654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.1595579967
Short name T683
Test name
Test status
Simulation time 16946554100 ps
CPU time 217.42 seconds
Started Sep 04 08:01:43 AM UTC 24
Finished Sep 04 08:05:24 AM UTC 24
Peak memory 291432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595579967 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1595579967 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_error.3747008179
Short name T688
Test name
Test status
Simulation time 5746532354 ps
CPU time 285.2 seconds
Started Sep 04 08:01:59 AM UTC 24
Finished Sep 04 08:06:49 AM UTC 24
Peak memory 318052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747008179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3747008179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.2166991014
Short name T662
Test name
Test status
Simulation time 1291292556 ps
CPU time 8.13 seconds
Started Sep 04 08:02:09 AM UTC 24
Finished Sep 04 08:02:18 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166991014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2166991014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.681928140
Short name T663
Test name
Test status
Simulation time 140785518 ps
CPU time 1.98 seconds
Started Sep 04 08:02:18 AM UTC 24
Finished Sep 04 08:02:21 AM UTC 24
Peak memory 231612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681928140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.681928140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.1110567657
Short name T722
Test name
Test status
Simulation time 75612635563 ps
CPU time 2390.51 seconds
Started Sep 04 08:01:31 AM UTC 24
Finished Sep 04 08:41:48 AM UTC 24
Peak memory 2851428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110567657 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.1110567657 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.4131789142
Short name T705
Test name
Test status
Simulation time 49245098998 ps
CPU time 544.23 seconds
Started Sep 04 08:01:38 AM UTC 24
Finished Sep 04 08:10:50 AM UTC 24
Peak memory 594664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131789142 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.4131789142 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.1506553366
Short name T661
Test name
Test status
Simulation time 1480964311 ps
CPU time 30.76 seconds
Started Sep 04 08:01:26 AM UTC 24
Finished Sep 04 08:01:58 AM UTC 24
Peak memory 235944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506553366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.1506553366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.3931990071
Short name T694
Test name
Test status
Simulation time 94043157187 ps
CPU time 346.79 seconds
Started Sep 04 08:02:19 AM UTC 24
Finished Sep 04 08:08:11 AM UTC 24
Peak memory 402028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931990071 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3931990071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3675745646
Short name T672
Test name
Test status
Simulation time 32190774 ps
CPU time 1.26 seconds
Started Sep 04 08:03:12 AM UTC 24
Finished Sep 04 08:03:14 AM UTC 24
Peak memory 224980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675745646 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3675745646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_app.300226852
Short name T685
Test name
Test status
Simulation time 29652398326 ps
CPU time 214.71 seconds
Started Sep 04 08:02:39 AM UTC 24
Finished Sep 04 08:06:17 AM UTC 24
Peak memory 295504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300226852 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.300226852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.4113419475
Short name T716
Test name
Test status
Simulation time 54194794206 ps
CPU time 1446.54 seconds
Started Sep 04 08:02:31 AM UTC 24
Finished Sep 04 08:26:56 AM UTC 24
Peak memory 277080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113419475 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.4113419475 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.2333442385
Short name T698
Test name
Test status
Simulation time 62543071738 ps
CPU time 380.69 seconds
Started Sep 04 08:02:41 AM UTC 24
Finished Sep 04 08:09:07 AM UTC 24
Peak memory 500336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333442385 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.2333442385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_error.650172911
Short name T669
Test name
Test status
Simulation time 1191020455 ps
CPU time 7.77 seconds
Started Sep 04 08:02:49 AM UTC 24
Finished Sep 04 08:02:58 AM UTC 24
Peak memory 240176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650172911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.650172911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.2911067767
Short name T670
Test name
Test status
Simulation time 3708820079 ps
CPU time 6.51 seconds
Started Sep 04 08:02:59 AM UTC 24
Finished Sep 04 08:03:07 AM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911067767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2911067767 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.1423884513
Short name T725
Test name
Test status
Simulation time 162037227460 ps
CPU time 3557.79 seconds
Started Sep 04 08:02:25 AM UTC 24
Finished Sep 04 09:02:21 AM UTC 24
Peak memory 4006552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423884513 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.1423884513 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.3600961527
Short name T591
Test name
Test status
Simulation time 3442035661 ps
CPU time 125.42 seconds
Started Sep 04 08:02:26 AM UTC 24
Finished Sep 04 08:04:34 AM UTC 24
Peak memory 309800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600961527 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3600961527 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.1088637656
Short name T674
Test name
Test status
Simulation time 1075644551 ps
CPU time 55.32 seconds
Started Sep 04 08:02:23 AM UTC 24
Finished Sep 04 08:03:20 AM UTC 24
Peak memory 236004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088637656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1088637656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.3982108665
Short name T717
Test name
Test status
Simulation time 51629728935 ps
CPU time 1455.69 seconds
Started Sep 04 08:03:07 AM UTC 24
Finished Sep 04 08:27:40 AM UTC 24
Peak memory 1449024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982108665 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.3982108665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.4071505862
Short name T215
Test name
Test status
Simulation time 56007329 ps
CPU time 1.22 seconds
Started Sep 04 06:34:00 AM UTC 24
Finished Sep 04 06:34:02 AM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071505862 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.4071505862 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_app.188029410
Short name T121
Test name
Test status
Simulation time 5124028088 ps
CPU time 28.61 seconds
Started Sep 04 06:32:46 AM UTC 24
Finished Sep 04 06:33:16 AM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188029410 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.188029410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.1083973002
Short name T27
Test name
Test status
Simulation time 19924305414 ps
CPU time 296.8 seconds
Started Sep 04 06:32:52 AM UTC 24
Finished Sep 04 06:37:53 AM UTC 24
Peak memory 447084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083973002 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1083973002 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.1089241485
Short name T268
Test name
Test status
Simulation time 13858879450 ps
CPU time 904.47 seconds
Started Sep 04 06:32:42 AM UTC 24
Finished Sep 04 06:47:58 AM UTC 24
Peak memory 248420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089241485 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1089241485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1124329133
Short name T213
Test name
Test status
Simulation time 314460593 ps
CPU time 26.64 seconds
Started Sep 04 06:33:24 AM UTC 24
Finished Sep 04 06:33:52 AM UTC 24
Peak memory 248368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124329133 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1124329133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.800812322
Short name T212
Test name
Test status
Simulation time 51405692 ps
CPU time 1.84 seconds
Started Sep 04 06:33:36 AM UTC 24
Finished Sep 04 06:33:39 AM UTC 24
Peak memory 227900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800812322 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.800812322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.3054412530
Short name T169
Test name
Test status
Simulation time 19238076233 ps
CPU time 79.18 seconds
Started Sep 04 06:33:37 AM UTC 24
Finished Sep 04 06:34:59 AM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054412530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3054412530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2353684472
Short name T209
Test name
Test status
Simulation time 667996887 ps
CPU time 13.9 seconds
Started Sep 04 06:33:00 AM UTC 24
Finished Sep 04 06:33:15 AM UTC 24
Peak memory 235104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353684472 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2353684472 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_error.188376827
Short name T160
Test name
Test status
Simulation time 37163383472 ps
CPU time 362.72 seconds
Started Sep 04 06:33:18 AM UTC 24
Finished Sep 04 06:39:26 AM UTC 24
Peak memory 481876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188376827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.188376827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.2604425258
Short name T211
Test name
Test status
Simulation time 227144638 ps
CPU time 2.06 seconds
Started Sep 04 06:33:20 AM UTC 24
Finished Sep 04 06:33:23 AM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604425258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2604425258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.3075885840
Short name T316
Test name
Test status
Simulation time 95759232366 ps
CPU time 1382.23 seconds
Started Sep 04 06:32:36 AM UTC 24
Finished Sep 04 06:55:54 AM UTC 24
Peak memory 901668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075885840 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.3075885840 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.508892946
Short name T93
Test name
Test status
Simulation time 26322980803 ps
CPU time 295.92 seconds
Started Sep 04 06:33:16 AM UTC 24
Finished Sep 04 06:38:16 AM UTC 24
Peak memory 416836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508892946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.508892946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.3716167670
Short name T232
Test name
Test status
Simulation time 24329386415 ps
CPU time 416.59 seconds
Started Sep 04 06:32:39 AM UTC 24
Finished Sep 04 06:39:41 AM UTC 24
Peak memory 479844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716167670 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3716167670 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.4023411716
Short name T192
Test name
Test status
Simulation time 6621712183 ps
CPU time 87.67 seconds
Started Sep 04 06:32:06 AM UTC 24
Finished Sep 04 06:33:36 AM UTC 24
Peak memory 234368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023411716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.4023411716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.1404367034
Short name T91
Test name
Test status
Simulation time 6764059942 ps
CPU time 140.7 seconds
Started Sep 04 06:33:45 AM UTC 24
Finished Sep 04 06:36:08 AM UTC 24
Peak memory 353108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404367034 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1404367034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.1971462765
Short name T28
Test name
Test status
Simulation time 12095026964 ps
CPU time 265.06 seconds
Started Sep 04 06:33:53 AM UTC 24
Finished Sep 04 06:38:22 AM UTC 24
Peak memory 297648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1971462765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_r
and_reset.1971462765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1884647080
Short name T224
Test name
Test status
Simulation time 53943395 ps
CPU time 1.3 seconds
Started Sep 04 06:36:33 AM UTC 24
Finished Sep 04 06:36:36 AM UTC 24
Peak memory 226304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884647080 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1884647080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_app.4007479653
Short name T185
Test name
Test status
Simulation time 39443458937 ps
CPU time 255.61 seconds
Started Sep 04 06:35:10 AM UTC 24
Finished Sep 04 06:39:29 AM UTC 24
Peak memory 416272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007479653 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4007479653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.2551825887
Short name T236
Test name
Test status
Simulation time 52902903702 ps
CPU time 381.73 seconds
Started Sep 04 06:35:17 AM UTC 24
Finished Sep 04 06:41:45 AM UTC 24
Peak memory 483976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551825887 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2551825887 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.530166278
Short name T269
Test name
Test status
Simulation time 20922177452 ps
CPU time 786.8 seconds
Started Sep 04 06:35:00 AM UTC 24
Finished Sep 04 06:48:16 AM UTC 24
Peak memory 258728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530166278 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.530166278 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.2689612486
Short name T70
Test name
Test status
Simulation time 78527364 ps
CPU time 1.72 seconds
Started Sep 04 06:36:18 AM UTC 24
Finished Sep 04 06:36:21 AM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689612486 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2689612486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3615390874
Short name T222
Test name
Test status
Simulation time 21500158 ps
CPU time 1.16 seconds
Started Sep 04 06:36:21 AM UTC 24
Finished Sep 04 06:36:23 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615390874 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3615390874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3260802419
Short name T225
Test name
Test status
Simulation time 12390351164 ps
CPU time 97.91 seconds
Started Sep 04 06:36:22 AM UTC 24
Finished Sep 04 06:38:02 AM UTC 24
Peak memory 234288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260802419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3260802419 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2879563081
Short name T223
Test name
Test status
Simulation time 4170298574 ps
CPU time 66.19 seconds
Started Sep 04 06:35:22 AM UTC 24
Finished Sep 04 06:36:31 AM UTC 24
Peak memory 258748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879563081 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2879563081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_error.4244871964
Short name T158
Test name
Test status
Simulation time 11938891418 ps
CPU time 238.06 seconds
Started Sep 04 06:36:00 AM UTC 24
Finished Sep 04 06:40:01 AM UTC 24
Peak memory 383592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244871964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.4244871964 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.984251955
Short name T221
Test name
Test status
Simulation time 1766902809 ps
CPU time 7.34 seconds
Started Sep 04 06:36:09 AM UTC 24
Finished Sep 04 06:36:17 AM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984251955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.984251955 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.3159944524
Short name T184
Test name
Test status
Simulation time 35718148 ps
CPU time 2.06 seconds
Started Sep 04 06:36:24 AM UTC 24
Finished Sep 04 06:36:27 AM UTC 24
Peak memory 234108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159944524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3159944524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.4043135319
Short name T440
Test name
Test status
Simulation time 21495813850 ps
CPU time 2446.49 seconds
Started Sep 04 06:34:03 AM UTC 24
Finished Sep 04 07:15:16 AM UTC 24
Peak memory 1528564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043135319 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.4043135319 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3931953528
Short name T94
Test name
Test status
Simulation time 13484747379 ps
CPU time 301.39 seconds
Started Sep 04 06:35:29 AM UTC 24
Finished Sep 04 06:40:34 AM UTC 24
Peak memory 316340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931953528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3931953528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.2726789622
Short name T189
Test name
Test status
Simulation time 1248691021 ps
CPU time 131.85 seconds
Started Sep 04 06:34:22 AM UTC 24
Finished Sep 04 06:36:36 AM UTC 24
Peak memory 266724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726789622 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2726789622 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.199999840
Short name T220
Test name
Test status
Simulation time 4125282228 ps
CPU time 114.98 seconds
Started Sep 04 06:34:02 AM UTC 24
Finished Sep 04 06:35:59 AM UTC 24
Peak memory 238192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199999840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.199999840 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.1828479238
Short name T409
Test name
Test status
Simulation time 46278725573 ps
CPU time 1939.69 seconds
Started Sep 04 06:36:28 AM UTC 24
Finished Sep 04 07:09:10 AM UTC 24
Peak memory 582552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828479238 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1828479238 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.3637030320
Short name T231
Test name
Test status
Simulation time 45306397 ps
CPU time 1.26 seconds
Started Sep 04 06:39:34 AM UTC 24
Finished Sep 04 06:39:37 AM UTC 24
Peak memory 226720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637030320 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3637030320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_app.1572789983
Short name T235
Test name
Test status
Simulation time 29491460137 ps
CPU time 206.77 seconds
Started Sep 04 06:37:37 AM UTC 24
Finished Sep 04 06:41:07 AM UTC 24
Peak memory 375344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572789983 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1572789983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.764809997
Short name T254
Test name
Test status
Simulation time 85988340893 ps
CPU time 502.56 seconds
Started Sep 04 06:37:54 AM UTC 24
Finished Sep 04 06:46:23 AM UTC 24
Peak memory 594540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764809997 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.764809997 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3218875557
Short name T150
Test name
Test status
Simulation time 4244025765 ps
CPU time 537.6 seconds
Started Sep 04 06:37:34 AM UTC 24
Finished Sep 04 06:46:39 AM UTC 24
Peak memory 242272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218875557 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3218875557 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.3491126182
Short name T230
Test name
Test status
Simulation time 480842228 ps
CPU time 50.55 seconds
Started Sep 04 06:38:42 AM UTC 24
Finished Sep 04 06:39:34 AM UTC 24
Peak memory 235892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491126182 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3491126182 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2656715587
Short name T228
Test name
Test status
Simulation time 22567953 ps
CPU time 1.25 seconds
Started Sep 04 06:39:11 AM UTC 24
Finished Sep 04 06:39:13 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656715587 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2656715587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.3674287154
Short name T234
Test name
Test status
Simulation time 4185705054 ps
CPU time 64.13 seconds
Started Sep 04 06:39:14 AM UTC 24
Finished Sep 04 06:40:20 AM UTC 24
Peak memory 234300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674287154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3674287154 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.1161513649
Short name T247
Test name
Test status
Simulation time 162180842158 ps
CPU time 429.85 seconds
Started Sep 04 06:38:03 AM UTC 24
Finished Sep 04 06:45:19 AM UTC 24
Peak memory 510512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161513649 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1161513649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_error.1464285345
Short name T21
Test name
Test status
Simulation time 82200370771 ps
CPU time 338.42 seconds
Started Sep 04 06:38:17 AM UTC 24
Finished Sep 04 06:43:59 AM UTC 24
Peak memory 506404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464285345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1464285345 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.3425901906
Short name T227
Test name
Test status
Simulation time 5345457587 ps
CPU time 17.36 seconds
Started Sep 04 06:38:23 AM UTC 24
Finished Sep 04 06:38:41 AM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425901906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3425901906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.1287417066
Short name T57
Test name
Test status
Simulation time 520072254 ps
CPU time 22.82 seconds
Started Sep 04 06:39:25 AM UTC 24
Finished Sep 04 06:39:49 AM UTC 24
Peak memory 246328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287417066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1287417066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.3338986058
Short name T314
Test name
Test status
Simulation time 11084081823 ps
CPU time 1124 seconds
Started Sep 04 06:36:37 AM UTC 24
Finished Sep 04 06:55:34 AM UTC 24
Peak memory 858720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338986058 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.3338986058 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.2362079067
Short name T95
Test name
Test status
Simulation time 5546750573 ps
CPU time 336.1 seconds
Started Sep 04 06:38:05 AM UTC 24
Finished Sep 04 06:43:46 AM UTC 24
Peak memory 336888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362079067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2362079067 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.2407812045
Short name T229
Test name
Test status
Simulation time 4099371517 ps
CPU time 108.8 seconds
Started Sep 04 06:37:33 AM UTC 24
Finished Sep 04 06:39:24 AM UTC 24
Peak memory 313960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407812045 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2407812045 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.915151814
Short name T226
Test name
Test status
Simulation time 17065585822 ps
CPU time 85.73 seconds
Started Sep 04 06:36:36 AM UTC 24
Finished Sep 04 06:38:04 AM UTC 24
Peak memory 236056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915151814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.915151814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.2874433133
Short name T485
Test name
Test status
Simulation time 311441137631 ps
CPU time 2604.52 seconds
Started Sep 04 06:39:26 AM UTC 24
Finished Sep 04 07:23:19 AM UTC 24
Peak memory 2085736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874433133 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2874433133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.1645101809
Short name T83
Test name
Test status
Simulation time 10268892460 ps
CPU time 129 seconds
Started Sep 04 06:39:30 AM UTC 24
Finished Sep 04 06:41:42 AM UTC 24
Peak memory 295660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1645101809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_r
and_reset.1645101809 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.66113740
Short name T242
Test name
Test status
Simulation time 62028856 ps
CPU time 1.33 seconds
Started Sep 04 06:42:40 AM UTC 24
Finished Sep 04 06:42:43 AM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66113740 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.66113740 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_app.2634866724
Short name T249
Test name
Test status
Simulation time 15247515682 ps
CPU time 357.57 seconds
Started Sep 04 06:39:50 AM UTC 24
Finished Sep 04 06:45:52 AM UTC 24
Peak memory 477804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634866724 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2634866724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.1526927081
Short name T260
Test name
Test status
Simulation time 33770128921 ps
CPU time 416.04 seconds
Started Sep 04 06:40:02 AM UTC 24
Finished Sep 04 06:47:04 AM UTC 24
Peak memory 334352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526927081 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1526927081 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.2227462146
Short name T331
Test name
Test status
Simulation time 23658160561 ps
CPU time 1048.03 seconds
Started Sep 04 06:39:45 AM UTC 24
Finished Sep 04 06:57:25 AM UTC 24
Peak memory 264804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227462146 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2227462146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.2130965670
Short name T241
Test name
Test status
Simulation time 678961623 ps
CPU time 51.8 seconds
Started Sep 04 06:41:46 AM UTC 24
Finished Sep 04 06:42:39 AM UTC 24
Peak memory 251724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130965670 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2130965670 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.2611332441
Short name T238
Test name
Test status
Simulation time 21606272 ps
CPU time 1.41 seconds
Started Sep 04 06:41:54 AM UTC 24
Finished Sep 04 06:41:56 AM UTC 24
Peak memory 225400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611332441 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2611332441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.3171805945
Short name T240
Test name
Test status
Simulation time 422409110 ps
CPU time 8.15 seconds
Started Sep 04 06:41:57 AM UTC 24
Finished Sep 04 06:42:06 AM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171805945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3171805945 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.858459383
Short name T246
Test name
Test status
Simulation time 33200175789 ps
CPU time 255.83 seconds
Started Sep 04 06:40:21 AM UTC 24
Finished Sep 04 06:44:41 AM UTC 24
Peak memory 422508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858459383 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.858459383 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_error.216705226
Short name T159
Test name
Test status
Simulation time 10976092303 ps
CPU time 277.71 seconds
Started Sep 04 06:41:08 AM UTC 24
Finished Sep 04 06:45:50 AM UTC 24
Peak memory 465444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216705226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.216705226 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.41331717
Short name T237
Test name
Test status
Simulation time 1291016382 ps
CPU time 9.14 seconds
Started Sep 04 06:41:43 AM UTC 24
Finished Sep 04 06:41:53 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41331717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.41331717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.457533140
Short name T239
Test name
Test status
Simulation time 37136000 ps
CPU time 1.77 seconds
Started Sep 04 06:41:57 AM UTC 24
Finished Sep 04 06:42:00 AM UTC 24
Peak memory 229624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457533140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.457533140 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.798337988
Short name T490
Test name
Test status
Simulation time 98563932454 ps
CPU time 2678.69 seconds
Started Sep 04 06:39:42 AM UTC 24
Finished Sep 04 07:24:49 AM UTC 24
Peak memory 1661592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798337988 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.798337988 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.1578720228
Short name T255
Test name
Test status
Simulation time 23562490114 ps
CPU time 343.02 seconds
Started Sep 04 06:40:35 AM UTC 24
Finished Sep 04 06:46:24 AM UTC 24
Peak memory 455596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578720228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1578720228 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.835574464
Short name T258
Test name
Test status
Simulation time 30790210026 ps
CPU time 403.87 seconds
Started Sep 04 06:39:43 AM UTC 24
Finished Sep 04 06:46:32 AM UTC 24
Peak memory 453264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835574464 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.835574464 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.1581979463
Short name T233
Test name
Test status
Simulation time 113493904 ps
CPU time 4.77 seconds
Started Sep 04 06:39:38 AM UTC 24
Finished Sep 04 06:39:44 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581979463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1581979463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.3325292871
Short name T257
Test name
Test status
Simulation time 27997161030 ps
CPU time 266.4 seconds
Started Sep 04 06:42:00 AM UTC 24
Finished Sep 04 06:46:30 AM UTC 24
Peak memory 406036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325292871 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.3325292871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.3831499038
Short name T131
Test name
Test status
Simulation time 6418024086 ps
CPU time 101.03 seconds
Started Sep 04 06:42:07 AM UTC 24
Finished Sep 04 06:43:50 AM UTC 24
Peak memory 279216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3831499038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_r
and_reset.3831499038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.1665777396
Short name T256
Test name
Test status
Simulation time 22255173 ps
CPU time 1.37 seconds
Started Sep 04 06:46:24 AM UTC 24
Finished Sep 04 06:46:27 AM UTC 24
Peak memory 224684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665777396 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1665777396 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_app.4151324822
Short name T245
Test name
Test status
Simulation time 1138244337 ps
CPU time 37.29 seconds
Started Sep 04 06:43:54 AM UTC 24
Finished Sep 04 06:44:33 AM UTC 24
Peak memory 252328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151324822 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.4151324822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.133788157
Short name T250
Test name
Test status
Simulation time 15207490923 ps
CPU time 112.77 seconds
Started Sep 04 06:44:00 AM UTC 24
Finished Sep 04 06:45:55 AM UTC 24
Peak memory 285228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133788157 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.133788157 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.3598455056
Short name T283
Test name
Test status
Simulation time 6561626342 ps
CPU time 428.81 seconds
Started Sep 04 06:43:51 AM UTC 24
Finished Sep 04 06:51:06 AM UTC 24
Peak memory 252460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598455056 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3598455056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.1044803054
Short name T259
Test name
Test status
Simulation time 2108861639 ps
CPU time 45.62 seconds
Started Sep 04 06:45:51 AM UTC 24
Finished Sep 04 06:46:38 AM UTC 24
Peak memory 246320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044803054 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1044803054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3126264532
Short name T251
Test name
Test status
Simulation time 48509719 ps
CPU time 1.38 seconds
Started Sep 04 06:45:53 AM UTC 24
Finished Sep 04 06:45:55 AM UTC 24
Peak memory 224740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126264532 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3126264532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2474341193
Short name T261
Test name
Test status
Simulation time 5158904713 ps
CPU time 67.32 seconds
Started Sep 04 06:45:56 AM UTC 24
Finished Sep 04 06:47:05 AM UTC 24
Peak memory 234300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474341193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2474341193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1000127438
Short name T276
Test name
Test status
Simulation time 37422524457 ps
CPU time 251.99 seconds
Started Sep 04 06:44:33 AM UTC 24
Finished Sep 04 06:48:49 AM UTC 24
Peak memory 387688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000127438 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1000127438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_error.200427037
Short name T22
Test name
Test status
Simulation time 8068336979 ps
CPU time 246.95 seconds
Started Sep 04 06:45:20 AM UTC 24
Finished Sep 04 06:49:30 AM UTC 24
Peak memory 393836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200427037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.200427037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.663918994
Short name T253
Test name
Test status
Simulation time 12952959371 ps
CPU time 15.17 seconds
Started Sep 04 06:45:48 AM UTC 24
Finished Sep 04 06:46:04 AM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663918994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.663918994 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.2479456126
Short name T252
Test name
Test status
Simulation time 133830870 ps
CPU time 2.22 seconds
Started Sep 04 06:45:56 AM UTC 24
Finished Sep 04 06:45:59 AM UTC 24
Peak memory 232000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479456126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.2479456126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.984351811
Short name T555
Test name
Test status
Simulation time 88820663931 ps
CPU time 3287.66 seconds
Started Sep 04 06:43:11 AM UTC 24
Finished Sep 04 07:38:34 AM UTC 24
Peak memory 1942168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984351811 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.984351811 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.1901094144
Short name T307
Test name
Test status
Simulation time 27399504464 ps
CPU time 576.27 seconds
Started Sep 04 06:44:41 AM UTC 24
Finished Sep 04 06:54:25 AM UTC 24
Peak memory 519028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901094144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1901094144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.3122456084
Short name T244
Test name
Test status
Simulation time 51225329 ps
CPU time 5.63 seconds
Started Sep 04 06:43:47 AM UTC 24
Finished Sep 04 06:43:54 AM UTC 24
Peak memory 234516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122456084 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3122456084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.1507026234
Short name T243
Test name
Test status
Simulation time 694704013 ps
CPU time 22.92 seconds
Started Sep 04 06:42:44 AM UTC 24
Finished Sep 04 06:43:09 AM UTC 24
Peak memory 236008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507026234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1507026234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.1722650892
Short name T72
Test name
Test status
Simulation time 17717208253 ps
CPU time 534.86 seconds
Started Sep 04 06:46:00 AM UTC 24
Finished Sep 04 06:55:02 AM UTC 24
Peak memory 350796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722650892 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_03/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.1722650892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/9.kmac_stress_all/latest
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