Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16347478	1			T1	1663		T2	1968		T3	3181
all_values[1]	16347478	1			T1	1663		T2	1968		T3	3181
all_values[2]	16347478	1			T1	1663		T2	1968		T3	3181

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462874

1

T1

46

T2

20

T3

11

auto[1]

48579560

1

T1

4943

T2

5884

T3

9532

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48810279

1

T1

4257

T2

5442

T3

8940

auto[1]

232155

1

T1

732

T2

462

T3

603

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	147501	1			T3	5		T29	57		T30	139
all_values[0]	auto[0]	auto[1]	1323	1			T3	6		T29	4		T30	6
all_values[0]	auto[1]	auto[0]	16122592	1			T1	1419		T2	1814		T3	2975
all_values[0]	auto[1]	auto[1]	76062	1			T1	244		T2	154		T3	195
all_values[1]	auto[0]	auto[0]	163728	1			T2	13		T9	2		T10	225
all_values[1]	auto[0]	auto[1]	951	1			T2	7		T10	3		T12	5
all_values[1]	auto[1]	auto[0]	16106365	1			T1	1419		T2	1801		T3	2980
all_values[1]	auto[1]	auto[1]	76434	1			T1	244		T2	147		T3	201
all_values[2]	auto[0]	auto[0]	148370	1			T1	39		T29	57		T30	4
all_values[2]	auto[0]	auto[1]	1001	1			T1	7		T29	4		T30	2
all_values[2]	auto[1]	auto[0]	16121723	1			T1	1380		T2	1814		T3	2980
all_values[2]	auto[1]	auto[1]	76384	1			T1	237		T2	154		T3	201