Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16347478	1			T1	1663		T2	1968		T3	3181
all_pins[1]	16347478	1			T1	1663		T2	1968		T3	3181
all_pins[2]	16347478	1			T1	1663		T2	1968		T3	3181

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48631838	1			T1	4745		T2	5750		T3	9348
values[0x1]	410596	1			T1	244		T2	154		T3	195
transitions[0x0=>0x1]	408288	1			T1	244		T2	154		T3	195
transitions[0x1=>0x0]	408312	1			T1	244		T2	154		T3	195

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16271416	1			T1	1419		T2	1814		T3	2986
all_pins[0]	values[0x1]	76062	1			T1	244		T2	154		T3	195
all_pins[0]	transitions[0x0=>0x1]	76040	1			T1	244		T2	154		T3	195
all_pins[0]	transitions[0x1=>0x0]	5196	1			T30	1		T15	3		T58	14
all_pins[1]	values[0x0]	16342260	1			T1	1663		T2	1968		T3	3181
all_pins[1]	values[0x1]	5218	1			T30	1		T15	3		T58	14
all_pins[1]	transitions[0x0=>0x1]	4921	1			T30	1		T15	3		T58	14
all_pins[1]	transitions[0x1=>0x0]	329019	1			T12	10		T31	6743		T58	915
all_pins[2]	values[0x0]	16018162	1			T1	1663		T2	1968		T3	3181
all_pins[2]	values[0x1]	329316	1			T12	10		T31	6743		T58	915
all_pins[2]	transitions[0x0=>0x1]	327327	1			T12	10		T31	6697		T58	915
all_pins[2]	transitions[0x1=>0x0]	74097	1			T1	244		T2	154		T3	195